[Sparc] Use synthetic instruction clr to zero register instead of sethi

[dcederman]

Summary

Using clr reg/mov %g0, reg/or %g0, %g0, reg to zero a register looks much better than sethi 0, reg.

lib/Target/Sparc/SparcInstrInfo.td

def WRPRri : F3_2<2, 0b110010,
                    (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                    "wrpr $rs1, $simm13, $rd", []>;
 }
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
+// Zero immediate.
+def : Pat<(i32 0),
+          (ORrr (i32 G0), (i32 G0))>;
 // Small immediates.
 def : Pat<(i32 simm13:$val),
           (ORri (i32 G0), imm:$val)>;
 // Arbitrary immediates.
 def : Pat<(i32 imm:$val),
           (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 
 

test/CodeGen/SPARC/atomics.ll

 ; CHECK:       sll %o3, %o1, %o5
 ; CHECK:       xor %o5, -1, %o3
 ; CHECK:       mov  123, %o4
 ; CHECK:       ld [%o2], %g2
 ; CHECK:       sll %o4, %o1, %o4
 ; CHECK:       and %o0, 255, %o0
 ; CHECK:       sll %o0, %o1, %o0
 ; CHECK:       andn %g2, %o5, %g2
-; CHECK:       sethi 0, %o5
+; CHECK:       mov %g0, %o5
 ; CHECK:      [[LABEL1:\.L.*]]:
 ; CHECK:       or %g2, %o4, %g3
 ; CHECK:       or %g2, %o0, %g4
 ; CHECK:       cas [%o2], %g4, %g3
 ; CHECK:       cmp %g3, %g4
 ; CHECK:       mov  %o5, %g4
 ; CHECK:       move %icc, 1, %g4
 ; CHECK:       cmp %g4, 0

 ; CHECK:       sll %o4, %o1, %o5
 ; CHECK:       xor %o5, -1, %o3
 ; CHECK:       and %o0, %o4, %o4
 ; CHECK:       ld [%o2], %g2
 ; CHECK:       mov  123, %o0
 ; CHECK:       sll %o0, %o1, %o0
 ; CHECK:       sll %o4, %o1, %o4
 ; CHECK:       andn %g2, %o5, %g2
-; CHECK:       sethi 0, %o5
+; CHECK:       mov %g0, %o5
 ; CHECK:      [[LABEL1:\.L.*]]:
 ; CHECK:       or %g2, %o0, %g3
 ; CHECK:       or %g2, %o4, %g4
 ; CHECK:       cas [%o2], %g4, %g3
 ; CHECK:       cmp %g3, %g4
 ; CHECK:       mov  %o5, %g4
 ; CHECK:       move %icc, 1, %g4
 ; CHECK:       cmp %g4, 0

 define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
 entry:
   %0 = atomicrmw sub i16* %p, i16 %v seq_cst
   ret i16 %0
 }
 
 ; CHECK-LABEL: test_load_add_i32
 ; CHECK: membar
+; CHECK: mov %g0
 ; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
 ; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
 ; CHECK: cas [%o0], [[V]], [[V2]]
 ; CHECK: membar
 define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %0

test/CodeGen/SPARC/imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC
+
+; Materializing constants
+
+define i32 @zero() nounwind {
+; SPARC-LABEL: zero:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov %g0, %o0
+ret i32 0
+}
+
+define i32 @pos_small() nounwind {
+; SPARC-LABEL: pos_small:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov 2047, %o0
+  ret i32 2047
+}
+
+define i32 @neg_small() nounwind {
+; SPARC-LABEL: neg_small:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov -2047, %o0
+  ret i32 -2047
+}
+
+define i32 @pos_i32() nounwind {
+; SPARC-LABEL: pos_i32:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    sethi 1695242, %o0
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    or %o0, 751, %o0
+  ret i32 1735928559
+}
+
+define i32 @neg_i32() nounwind {
+; SPARC-LABEL: neg_i32:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    sethi 3648367, %o0
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    or %o0, 751, %o0
+  ret i32 -559038737
+}

test/CodeGen/SPARC/inlineasm.ll

entry:
   %conv = sext i32 %foo to i64
   tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
   ret i32 %o
 }
 attributes #0 = { "no-frame-pointer-elim"="true" }
 
 ;; Ensures that tied in and out gets allocated properly.
 ; CHECK-LABEL: test_i64_inout:
-; CHECK: sethi 0, %o2
+; CHECK: mov %g0, %o2
 ; CHECK: mov 5, %o3
 ; CHECK: xor %o2, %g0, %o2
 ; CHECK: mov %o2, %o0
 ; CHECK: ret
 define i64 @test_i64_inout() {
 entry:
   %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
   ret i64 %0

test/CodeGen/SPARC/vector-extract-elt.ll

 ; RUN: llc -march=sparc < %s | FileCheck %s
 
 
 ; If computeKnownSignBits (in SelectionDAG) can do a simple
 ; look-thru for extractelement then we know that the add will yield a
 ; non-negative result.
 define i1 @test1(<4 x i16>* %in) {
 ; CHECK-LABEL: ! %bb.0:
 ; CHECK-NEXT:        retl
-; CHECK-NEXT:        sethi 0, %o0
+; CHECK-NEXT:        mov %g0, %o0
   %vec2 = load <4 x i16>, <4 x i16>* %in, align 1
   %vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
   %vec4 = sext <4 x i16> %vec3 to <4 x i32>
   %elt0 = extractelement <4 x i32> %vec4, i32 0
   %elt1 = extractelement <4 x i32> %vec4, i32 1
   %sum = add i32 %elt0, %elt1
   %bool = icmp slt i32 %sum, 0
   ret i1 %bool
 }