[mips] Accept 32-bit offsets for lb and lbu commands

[atanasyan]

Summary

lb and lbu commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, lb command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken.

This patch restores support for 32-bit offsets. It replaces mem_simm16 operand for LB and LBu definitions by the new mem_simmptr operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible.

Some issues remain:

• The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch.

• GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM:

lb      $4, 0x80000004

# gas
lui     a0, 0x8000
lb      a0, 4(a0)

• In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LVVM. This issue is for a separate patch.

lb      $4, 0x800000001

# gas
li      a0, 0x8000
dsll    a0, a0, 0x14
lb      a0, 4(a0)

[sdardis]

I don't think this is quite the correct approach, especially if you're going to be implementing support for 64-bit pointers with those instructions, as we would need to modify the existing lb64 and friends to be available to the AsmParser with a different set of operands.

Instead, we should use the 'mem' operand for the lb and lbu instructions. That will allow the parser to match larger offsets than those instructions permit.

Then in MipsAsmParser during the expansion of the instruction, we can check the size of the offset and error out there if >32 bits. There's currently a bug there in that offsets are truncated to signed 32bit values before checking if they're out of range.

The other instructions in the base MIPS architecture which appear to have this issue are: ld, lh, lhu and sd.

[atanasyan]

In D45020#1056816, @sdardis wrote:

I don't think this is quite the correct approach, especially if you're going to be implementing support for 64-bit pointers with those instructions, as we would need to modify the existing lb64 and friends to be available to the AsmParser with a different set of operands.

Instead, we should use the 'mem' operand for the lb and lbu instructions. That will allow the parser to match larger offsets than those instructions permit.

Thanks for review. I will provide another patch soon.

[atanasyan]

In D45020#1056816, @sdardis wrote:

we should use the 'mem' operand for the lb and lbu instructions. That will allow the parser to match larger offsets than those instructions permit.

BTW do you suggest to escape sub-classing the 'mem' operand at all? If so, we won't be able to diagnose that an operand does not fit 32 or 64 bit range.

[sdardis]

In D45020#1065586, @atanasyan wrote:

In D45020#1056816, @sdardis wrote:

we should use the 'mem' operand for the lb and lbu instructions. That will allow the parser to match larger offsets than those instructions permit.

BTW do you suggest to escape sub-classing the 'mem' operand at all? If so, we won't be able to diagnose that an operand does not fit 32 or 64 bit range.

We can diagnose the case if the operand does not fit a 32 or 64 bit range though the chain of processInstruction() -> expandMemInst() -> expand(Load|Store)Inst(). If we accept a full 64bit offset during parsing, we can determine if we should reject it after parsing while processing the instructions.

[atanasyan]

I created an alternative patch D46105 which replaces mem_simm16 by mem and performs range checking in the expandLoadInst routine. But there is a problem with that patch - in the expandLoadInst routine we do not know position of invalid operand, so an error message points to the beginning of the incorrect instructions. This patch attempts to use new mem_simmptr operand for lb and lbu instructions and performs range checking in a uniform way with other instructions which use ParserMatchClass.

[sdardis]

LGTM.

In comparison to the other patch you submitted, this is clearly the better option as it points to the problematic operand.

Nit: You should correct the spelling of LLVM in the last sentence in the summary.

[atanasyan]

Thanks for review.

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (isa<MCTargetExpr>(getMemOff()) ||
         (isConstantMemOff() &&
          isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
       return true;
     MCValue Res;
     bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
     return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
   }
 
+  bool isMemWithPtrSizeOffset() const {
+    if (!isMem())
+      return false;
+    if (!getMemBase()->isGPRAsmReg())
+      return false;
+    const unsigned PtrBits = 32;
+    if (isa<MCTargetExpr>(getMemOff()) ||
+        (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
+      return true;
+    MCValue Res;
+    bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
+    return IsReloc && isIntN(PtrBits, Res.getConstant());
+  }
+
   bool isMemWithGRPMM16Base() const {
     return isMem() && getMemBase()->isMM16AsmReg();
   }
 
   template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
     return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
       && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
   }
case Match_MemSImm11:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected memory with 11-bit signed offset");
   case Match_MemSImm12:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected memory with 12-bit signed offset");
   case Match_MemSImm16:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected memory with 16-bit signed offset");
+  case Match_MemSImmPtr:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected memory with 32-bit signed offset");
   case Match_RequiresPosSizeRange0_32: {
     SMLoc ErrorStart = Operands[3]->getStartLoc();
     SMLoc ErrorEnd = Operands[4]->getEndLoc();
     return Error(ErrorStart, "size plus position are not in the range 0 .. 32",
                  SMRange(ErrorStart, ErrorEnd));
     }
   case Match_RequiresPosSizeUImm6: {
     SMLoc ErrorStart = Operands[3]->getStartLoc();

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

def MipsMemSimm16AsmOperand : AsmOperandClass {
   let Name = "MemOffsetSimm16";
   let SuperClasses = [MipsMemAsmOperand];
   let RenderMethod = "addMemOperands";
   let ParserMethod = "parseMemOperand";
   let PredicateMethod = "isMemWithSimmOffset<16>";
   let DiagnosticType = "MemSImm16";
 }
 
+def MipsMemSimmPtrAsmOperand : AsmOperandClass {
+  let Name = "MemOffsetSimmPtr";
+  let SuperClasses = [MipsMemAsmOperand];
+  let RenderMethod = "addMemOperands";
+  let ParserMethod = "parseMemOperand";
+  let PredicateMethod = "isMemWithPtrSizeOffset";
+  let DiagnosticType = "MemSImmPtr";
+}
+
 def MipsInvertedImmoperand : AsmOperandClass {
   let Name = "InvNum";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "parseInvNum";
 }
 
 def InvertedImOperand : Operand<i32> {
   let ParserMatchClass = MipsInvertedImmoperand;

 }
 
 def mem_simm16 : mem_generic {
   let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let ParserMatchClass = MipsMemSimm16AsmOperand;
 }
 
+def mem_simmptr : mem_generic {
+  let ParserMatchClass = MipsMemSimmPtrAsmOperand;
+}
+
 def mem_ea : Operand<iPTR> {
   let PrintMethod = "printMemOperandEA";
   let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let OperandType = "OPERAND_MEMORY";
 }
 
 def PtrRC : Operand<iPTR> {
def ROTR  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
                                       immZExt5>,
               SRA_FM<2, 1>, ISA_MIPS32R2;
   def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
               SRLV_FM<6, 1>, ISA_MIPS32R2;
 }
 
 /// Load and Store Instructions
 ///  aligned
-def LB  : LoadMemory<"lb", GPR32Opnd, mem_simm16, sextloadi8, II_LB>, MMRel,
+def LB  : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,
           LW_FM<0x20>;
-def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simm16, zextloadi8, II_LBU,
+def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,
                      addrDefault>, MMRel, LW_FM<0x24>;
 let AdditionalPredicates = [NotInMicroMips] in {
   def LH  : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
                        addrDefault>, MMRel, LW_FM<0x21>;
   def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
             MMRel, LW_FM<0x25>;
   def LW  : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
             LW_FM<0x23>;

llvm/trunk/test/MC/Mips/micromips/invalid.s

# RUN: FileCheck %s < %t1
   ori $3, -1          # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
   ori $3, 65536       # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
   xori $3, $4, -1     # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
   xori $3, $4, 65536  # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
   xori $3, -1         # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   xori $3, 65536      # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   not $3, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   lb $32, 8($5)       # CHECK: :[[@LINE]]:6: error: invalid register number
-  lb $4, -32769($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
-  lb $4, 32768($5)    # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+  lb $4, -2147483649($5)  # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
+  lb $4, 2147483648($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
   lb $4, 8($32)       # CHECK: :[[@LINE]]:12: error: invalid register number
   lbu $32, 8($5)      # CHECK: :[[@LINE]]:7: error: invalid register number
-  lbu $4, -32769($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  lbu $4, 32768($5)   # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+  lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
+  lbu $4, 2147483648($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
   lbu $4, 8($32)      # CHECK: :[[@LINE]]:13: error: invalid register number

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   ori $3, -1               # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
   ori $3, 65536            # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
   xori $3, $4, -1          # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
   xori $3, $4, 65536       # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
   xori $3, -1              # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   xori $3, 65536           # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   not $3, 4                # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   lb $32, 8($5)            # CHECK: :[[@LINE]]:6: error: invalid register number
-  lb $4, -32769($5)        # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
-  lb $4, 32768($5)         # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
+  lb $4, -2147483649($5)   # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
+  lb $4, 2147483648($5)    # CHECK: :[[@LINE]]:10: error: expected memory with 32-bit signed offset
   lb $4, 8($32)            # CHECK: :[[@LINE]]:12: error: invalid register number
   lbu $32, 8($5)           # CHECK: :[[@LINE]]:7: error: invalid register number
-  lbu $4, -32769($5)       # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  lbu $4, 32768($5)        # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
+  lbu $4, -2147483649($5)  # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
+  lbu $4, 2147483648($5)   # CHECK: :[[@LINE]]:11: error: expected memory with 32-bit signed offset
   lbu $4, 8($32)           # CHECK: :[[@LINE]]:13: error: invalid register number
   ldc1 $f32, 300($10)      # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
   ldc1 $f7, -32769($10)    # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
   ldc1 $f7, 32768($10)     # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
   ldc1 $f7, 300($32)       # CHECK: :[[@LINE]]:17: error: invalid register number
   sdc1 $f32, 64($10)       # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
   sdc1 $f7, -32769($10)    # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
   sdc1 $f7, 32768($10)     # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset

llvm/trunk/test/MC/Mips/mips-expansions.s

 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
 # RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-LE
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
 # RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-BE
 
 # Check that the IAS expands macro instructions in the same way as GAS.
 
 # Load address, done by MipsAsmParser::expandLoadAddressReg()
 # and MipsAsmParser::expandLoadAddressImm():
   la $8, 1f
 # CHECK-LE: lui     $8, %hi($tmp0)        # encoding: [A,A,0x08,0x3c]
 # CHECK-LE:                               #   fixup A - offset: 0, value: %hi($tmp0), kind: fixup_Mips_HI16
 # CHECK-LE: addiu   $8, $8, %lo($tmp0)    # encoding: [A,A,0x08,0x25]
 # CHECK-LE:                               #   fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16
 
+  lb $4, 0x8000
+# CHECK-LE: lui     $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK-LE: lb      $4, -32768($4)          # encoding: [0x00,0x80,0x84,0x80]
+
+  lb  $4, 0x20004($3)
+# CHECK-LE: lui     $4, 2                   # encoding: [0x02,0x00,0x04,0x3c]
+# CHECK-LE: addu    $4, $4, $3              # encoding: [0x21,0x20,0x83,0x00]
+# CHECK-LE: lb      $4, 4($4)               # encoding: [0x04,0x00,0x84,0x80]
+
+  lbu $4, 0x8000
+# CHECK-LE: lui     $4, 1                   # encoding: [0x01,0x00,0x04,0x3c]
+# CHECK-LE: lbu     $4, -32768($4)          # encoding: [0x00,0x80,0x84,0x90]
+
+  lbu  $4, 0x20004($3)
+# CHECK-LE: lui     $4, 2                   # encoding: [0x02,0x00,0x04,0x3c]
+# CHECK-LE: addu    $4, $4, $3              # encoding: [0x21,0x20,0x83,0x00]
+# CHECK-LE: lbu     $4, 4($4)               # encoding: [0x04,0x00,0x84,0x90]
+
 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
   .set noat
   lw $10, symbol($4)
 # CHECK-LE: lui     $10, %hi(symbol)        # encoding: [A,A,0x0a,0x3c]
 # CHECK-LE:                                 #   fixup A - offset: 0, value: %hi(symbol), kind: fixup_Mips_HI16
 # CHECK-LE: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
 # CHECK-LE: lw      $10, %lo(symbol)($10)   # encoding: [A,A,0x4a,0x8d]
 # CHECK-LE:                                 #   fixup A - offset: 0, value: %lo(symbol), kind: fixup_Mips_LO16

llvm/trunk/test/MC/Mips/mips32r5/invalid.s

# RUN: FileCheck %s < %t1
         mtc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mtc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mtc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc0  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -32769($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
-        lb $4, 32768($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+        lb $4, -2147483649($5)  # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
+        lb $4, 2147483648($5)   # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -32769($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
-        lbu $4, 32768($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+        lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
+        lbu $4, 2147483648($5)  # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset

llvm/trunk/test/MC/Mips/mips32r6/invalid.s

local_label:
         mfc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sdc2 $20, 1024($s2)  # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sync -1              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         sync 32              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -32769($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
-        lb $4, 32768($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+        lb $4, -2147483649($5)  # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
+        lb $4, 2147483648($5)   # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -32769($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
-        lbu $4, 32768($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+        lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
+        lbu $4, 2147483648($5)  # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset

llvm/trunk/test/MC/Mips/mips64r5/invalid.s

# RUN: FileCheck %s < %t1
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         dmtc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmtc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         sd $32, 65536($32)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -32769($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
-        lb $4, 32768($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+        lb $4, -2147483649($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
+        lb $4, 2147483648($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -32769($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
-        lbu $4, 32768($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+        lbu $4, -2147483649($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
+        lbu $4, 2147483648($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset

llvm/trunk/test/MC/Mips/mips64r6/invalid.s

.set noat
         dsrl $2, $4, 64      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
         dsrl $2, $4, -2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
         dsrl $32, $32, 32    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         dsrl32 $2, $4, 32    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
         dsrl32 $32, $32, 32  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         dsrlv $2, $4, 2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         dsrlv $32, $32, $32  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -32769($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
-        lb $4, 32768($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset
+        lb $4, -2147483649($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
+        lb $4, 2147483648($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -32769($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
-        lbu $4, 32768($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset
+        lbu $4, -2147483649($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
+        lbu $4, 2147483648($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset