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Differential D44933

[X86] Add sched override for MMX_PMOVMSKBrr in SandyBridge.
AbandonedPublic

Authored by courbet on Mar 27 2018, 7:22 AM.

Details

Reviewers
RKSimon
craig.topper
Summary

Latency should be 1. See the discussion on D44924.

Diff Detail

Event Timeline

courbet created this revision.Mar 27 2018, 7:22 AM
courbet mentioned this in D44924: [X86] Add WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK scheduler classes.Mar 27 2018, 7:23 AM
RKSimon added a comment.Mar 27 2018, 7:30 AM

I've added WriteMMXMOVMSK to D44924 which helps avoid the creation of an extra scheduler class in the X86GenSubtargetInfo.inc tables - that might be better?

courbet added a comment.Mar 27 2018, 7:55 AM

I don't have a strong opinion on this, either way is fine.

RKSimon added a comment.Mar 28 2018, 1:54 AM

Abandon? D44924.has landed and covers this now.

courbet abandoned this revision.Mar 28 2018, 2:00 AM

Yep, thanks.

Revision Contents

PathSize
lib/
Target/
X86/
3 lines

Diff 139922

lib/Target/X86/X86SchedSandyBridge.td

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Lines
// Remaining SNB instrs. // Remaining SNB instrs.
def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr", def: InstRW<[SBWriteResGroup0], (instregex "MMX_PMOVMSKBrr",
"(V?)CVTSS2SDrr",
"(V?)PSLLDri", "(V?)PSLLDri",
"(V?)PSLLQri", "(V?)PSLLQri",
"(V?)PSLLWri", "(V?)PSLLWri",
"(V?)PSRADri", "(V?)PSRADri",
"(V?)PSRAWri", "(V?)PSRAWri",
"(V?)PSRLDri", "(V?)PSRLDri",
"(V?)PSRLQri", "(V?)PSRLQri",
"(V?)PSRLWri", "(V?)PSRLWri",
▲ Show 20 Lines • Show All 1,790 Lines • Show Last 20 Lines