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Differential D44767

[ARM] Enable the full InstRW overlap check for ARMScheduleR52.td
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Authored by craig.topper on Mar 21 2018, 6:12 PM.

Details

Reviewers
javed.absar
Commits
rG7ccb5ebed87c: [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td
rL328216: [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td
Summary

This fixes a few issues with the R52 instregexs to enable the full overlap checking

Diff Detail

Event Timeline

craig.topper created this revision.Mar 21 2018, 6:12 PM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptMar 21 2018, 6:12 PM
craig.topper added inline comments.Mar 21 2018, 6:15 PM
lib/Target/ARM/ARMScheduleR52.td
223

Without the $ these also matched _ldr version below

515

Was matching _ldr as well.

533

This was matching VADDHNv2i32 and similar instructions which are already matched on line 780

798

This exact line appeard 5 lines above.

javed.absar accepted this revision.Mar 22 2018, 9:53 AM

Thanks for this.

This revision is now accepted and ready to land.Mar 22 2018, 9:53 AM
Closed by commit rL328216: [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td (authored by ctopper). · Explain WhyMar 22 2018, 10:21 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
ARM/
11 lines

Diff 139403

lib/Target/ARM/ARMScheduleR52.td

Show All 19 Lines
// This scheduler is a MachineScheduler. See TargetSchedule.td for details. // This scheduler is a MachineScheduler. See TargetSchedule.td for details.
def CortexR52Model : SchedMachineModel { def CortexR52Model : SchedMachineModel {
let MicroOpBufferSize = 0; // R52 is in-order processor let MicroOpBufferSize = 0; // R52 is in-order processor
let IssueWidth = 2; // 2 micro-ops dispatched per cycle let IssueWidth = 2; // 2 micro-ops dispatched per cycle
let LoadLatency = 1; // Optimistic, assuming no misses let LoadLatency = 1; // Optimistic, assuming no misses
let MispredictPenalty = 8; // A branch direction mispredict, including PFU let MispredictPenalty = 8; // A branch direction mispredict, including PFU
let CompleteModel = 0; // Covers instructions applicable to cortex-r52. let CompleteModel = 0; // Covers instructions applicable to cortex-r52.
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available. // Define each kind of processor resource and number available.
// Modeling each pipeline as a ProcResource using the BufferSize = 0 since // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
// Cortex-R52 is an in-order processor. // Cortex-R52 is an in-order processor.
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def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS],
(instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
"t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>; "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>;
def : InstRW<[R52WriteALU_EX1, R52Read_ISS], def : InstRW<[R52WriteALU_EX1, R52Read_ISS],
(instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi", (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi",
"t2MOVi", "t2MOV_ga_dyn")>; "t2MOVi", "t2MOV_ga_dyn")>;
def : InstRW<[R52WriteALU_EX2, R52Read_EX1], def : InstRW<[R52WriteALU_EX2, R52Read_EX1],
(instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel")>; (instregex "MOV_ga_pcrel$", "t2MOV_ga_pcrel$")>;
craig.topperAuthorUnsubmitted
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Without the $ these also matched _ldr version below

craig.topper: Without the $ these also matched _ldr version below
def : InstRW<[R52WriteLd,R52Read_ISS], def : InstRW<[R52WriteLd,R52Read_ISS],
(instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>; def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>;
def : InstRW< [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS], def : InstRW< [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS],
(instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
"(t|t2)UBFX", "(t|t2)SBFX")>; "(t|t2)UBFX", "(t|t2)SBFX")>;
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def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2], def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2],
(instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2], def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2],
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
"PUSH", "tPUSH")>; "PUSH", "tPUSH")>;
// LDRLIT pseudo instructions, they expand to LDR + PICADD // LDRLIT pseudo instructions, they expand to LDR + PICADD
def : InstRW<[R52WriteLd], def : InstRW<[R52WriteLd],
(instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>; (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel$")>;
craig.topperAuthorUnsubmitted
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Was matching _ldr as well.

craig.topper: Was matching _ldr as well.
// LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
def : InstRW<[R52WriteLd], (instregex "LDRLIT_ga_pcrel_ldr")>; def : InstRW<[R52WriteLd], (instregex "LDRLIT_ga_pcrel_ldr")>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VFP, Floating Point Support // VFP, Floating Point Support
def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fd|hd)")>; def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fd|hd)")>;
def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fq|hq)")>; def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fq|hq)")>;
def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(D|S|H)")>; def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(D|S|H)")>;
def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(fd|hd)")>; def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(fd|hd)")>;
def : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VABS(fq|hq)")>; def : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VABS(fq|hq)")>;
def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fd|hd)")>; def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fd|hd)")>;
def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fq|hq)")>; def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fq|hq)")>;
def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(D|S|H|fd|hd)")>; def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(D|S|H|fd|hd)$")>;
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This was matching VADDHNv2i32 and similar instructions which are already matched on line 780

craig.topper: This was matching VADDHNv2i32 and similar instructions which are already matched on line 780
def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(fq|hq)")>; def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(fq|hq)")>;
def : InstRW<[R52WriteFPLd_F4, R52Read_ISS, R52Read_F1], (instregex "VLDR")>; def : InstRW<[R52WriteFPLd_F4, R52Read_ISS, R52Read_F1], (instregex "VLDR")>;
def : InstRW<[R52WriteFPST_F4, R52Read_ISS, R52Read_F1], (instregex "VSTR")>; def : InstRW<[R52WriteFPST_F4, R52Read_ISS, R52Read_F1], (instregex "VSTR")>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Neon Support // Neon Support
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def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>; def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>;
def : InstRW<[R52WriteFPALU_F3, R52Read_F2], (instregex "VBICi(v4i16|v2i32)")>; def : InstRW<[R52WriteFPALU_F3, R52Read_F2], (instregex "VBICi(v4i16|v2i32)")>;
def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>; def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>;
def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d")>; def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d")>;
def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q")>; def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q")>;
def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>;
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This exact line appeard 5 lines above.

craig.topper: This exact line appeard 5 lines above.
def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1],
(instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>; (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1],
(instregex "VCVT", "VSITO", "VUITO", "VTO")>; (instregex "VCVT", "VSITO", "VUITO", "VTO")>;
def : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>; def : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>;
def : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>; def : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>;
def : InstRW<[R52WriteFPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)d")>; def : InstRW<[R52WriteFPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)d")>;
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