[Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt

[lei]

Summary

Followup to: https://reviews.llvm.org/D44506

Legalize and emit code for quad-precision floating point operations:

• xscpsgnqp
• xsabsqp
• xsnabsqp
• xsnegqp
• xssqrtqp

[nemanjai]

LGTM. Of course, please make sure you commit the two patches in the right order since this one clearly depends on the first one.

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
                          list<dag> pattern>
     : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isDOT;
 
   //===--------------------------------------------------------------------===//
   // Quad-Precision Scalar Move Instructions:
 
   // Copy Sign
-  def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", []>;
+  def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
+                                [(set f128:$vT,
+                                      (fcopysign f128:$vB, f128:$vA))]>;
 
   // Absolute/Negative-Absolute/Negate
-  def XSABSQP   : X_VT5_XO5_VB5<63,  0, 804, "xsabsqp" , []>;
-  def XSNABSQP  : X_VT5_XO5_VB5<63,  8, 804, "xsnabsqp", []>;
-  def XSNEGQP   : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp" , []>;
+  def XSABSQP   : X_VT5_XO5_VB5<63,  0, 804, "xsabsqp",
+                                [(set f128:$vT, (fabs f128:$vB))]>;
+  def XSNABSQP  : X_VT5_XO5_VB5<63,  8, 804, "xsnabsqp",
+                                [(set f128:$vT, (fneg (fabs f128:$vB)))]>;
+  def XSNEGQP   : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",
+                                [(set f128:$vT, (fneg f128:$vB))]>;
 
   //===--------------------------------------------------------------------===//
   // Quad-Precision Scalar Floating-Point Arithmetic Instructions:
 
   // Add/Divide/Multiply/Subtract
   let isCommutable = 1 in {
   def XSADDQP   : X_VT5_VA5_VB5   <63,   4, "xsaddqp",
                                    [(set f128:$vT, (fadd f128:$vA, f128:$vB))]>;
   def XSADDQPO  : X_VT5_VA5_VB5_Ro<63,   4, "xsaddqpo", []>;
   def XSMULQP   : X_VT5_VA5_VB5   <63,  36, "xsmulqp",
                                    [(set f128:$vT, (fmul f128:$vA, f128:$vB))]>;
   def XSMULQPO  : X_VT5_VA5_VB5_Ro<63,  36, "xsmulqpo", []>;
   }
 
   def XSSUBQP   : X_VT5_VA5_VB5   <63, 516, "xssubqp" ,
                                    [(set f128:$vT, (fsub f128:$vA, f128:$vB))]>;
   def XSSUBQPO  : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", []>;
   def XSDIVQP   : X_VT5_VA5_VB5   <63, 548, "xsdivqp",
                                    [(set f128:$vT, (fdiv f128:$vA, f128:$vB))]>;
   def XSDIVQPO  : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", []>;
 
   // Square-Root
-  def XSSQRTQP  : X_VT5_XO5_VB5   <63, 27, 804, "xssqrtqp" , []>;
+  def XSSQRTQP  : X_VT5_XO5_VB5   <63, 27, 804, "xssqrtqp",
+                                   [(set f128:$vT, (fsqrt f128:$vB))]>;
   def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", []>;
 
   // (Negative) Multiply-{Add/Subtract}
   def XSMADDQP  : X_VT5_VA5_VB5   <63, 388, "xsmaddqp"  , []>;
   def XSMADDQPO : X_VT5_VA5_VB5_Ro<63, 388, "xsmaddqpo" , []>;
   def XSMSUBQP  : X_VT5_VA5_VB5   <63, 420, "xsmsubqp"  , []>;
   def XSMSUBQPO : X_VT5_VA5_VB5_Ro<63, 420, "xsmsubqpo" , []>;
   def XSNMADDQP : X_VT5_VA5_VB5   <63, 452, "xsnmaddqp" , []>;

llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll

entry:
   %3 = bitcast i8* %add.ptr1 to fp128*
   store fp128 %1, fp128* %3, align 16
   ret void
 ; CHECK-LABEL: testLdNSt
 ; CHECK lxvx
 ; CHECK stxvx
 ; CHECK-NEXT blr
 }
+
+define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
+  store fp128 %1, fp128* %res, align 16
+  ret void
+
+; CHECK-LABEL: qpSqrt
+; CHECK-NOT bl sqrtl
+; CHECK xssqrtqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.sqrt.f128(fp128 %Val)
+
+define void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b,
+                     fp128* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
+  store fp128 %2, fp128* %res, align 16
+  ret void
+
+; CHECK-LABEL: qpSqrt
+; CHECK-NOT rldimi
+; CHECK xscpsgnqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
+
+define void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
+  store fp128 %1, fp128* %res, align 16
+  ret void
+
+; CHECK-LABEL: qpAbs
+; CHECK-NOT clrldi
+; CHECK xsabsqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.fabs.f128(fp128 %Val)
+
+define void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
+  %neg = fsub fp128 0xL00000000000000008000000000000000, %1
+  store fp128 %neg, fp128* %res, align 16
+  ret void
+
+; CHECK-LABEL: qpNAbs
+; CHECK-NOT bl __subtf3
+; CHECK xsnabsqp
+; CHECK stxv
+; CHECK blr
+}
+
+define void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %sub = fsub fp128 0xL00000000000000008000000000000000, %0
+  store fp128 %sub, fp128* %res, align 16
+  ret void
+
+; CHECK-LABEL: qpNeg
+; CHECK-NOT bl __subtf3
+; CHECK xsnegqp
+; CHECK stxv
+; CHECK blr
+}