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[AMDGPU] Widened vector length for global/constant address space.
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Authored by FarhanaAleen on Mar 6 2018, 4:11 PM.

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Summary

GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.

This is a re-submission.

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Repository
rL LLVM

Event Timeline

FarhanaAleen created this revision.Mar 6 2018, 4:11 PM
rampitec accepted this revision.Mar 6 2018, 4:15 PM

LGTM.

This revision is now accepted and ready to land.Mar 6 2018, 4:15 PM
This revision was automatically updated to reflect the committed changes.