Make it possible for ints/floats to return different values from getBooleanContents()

[dsanders]

Summary

On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer
comparisons return 0 or 1.

Updated the various uses of getBooleanContents. Two simplifications had to be
disabled when float and int boolean contents differ:

• ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially discoverable (i.e. when the condition of the VSELECT is a SETCC node).
• visitVSELECT (select C, 0, 1) -> (xor C, 1). Come to think of it, this one could test for the common case of 'C' being a SETCC too.

Preserved existing behaviour for all other targets and updated the affected
MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low'
variable was counting in the wrong direction because it thought it could simply
add the result of the comparison.

[hfinkel]

include/llvm/Target/TargetLowering.h

285

Please remove this (we don't need the OLD version any more).

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4524

I'm missing something here... why not?

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

265

Again, please explain.

[dsanders]

include/llvm/Target/TargetLowering.h

285

Ok.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4524

We can't tell whether we have an integer-based boolean or a floating-point-based boolean unless we can find the SETCC that produced it and inspect its operands. This is fairly easy if C is the SETCC node, but it can potentially be undiscoverable (or not reasonably discoverable). For example, it could be in another basic block or it could require searching a complicated expression.

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

265

It's the same reason as the other one but here I attempt to cover the most likely case where Cond is a SETCC.

[hfinkel]

include/llvm/Target/TargetLowering.h

960

I would really like to do this without causing churn to all of the targets (and causing pain for all out-of-tree targets). How about we do this:

void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; BooleanFloatContents = Ty; }

void setBooleanContents(BooleanContent Ty, BooleanContent FTy) { BooleanContents = Ty; BooleanFloatContents = FTy; }

do that the current target code will continue to do the right thing.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4524

Okay, this is reasonable. Please make the source-code comment as informative as your reply :-)

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

265

Please make the comment reference the comment above (in DAGCombiner::visitSELECT) for an explanation.

[dsanders]

Removed getBooleanContentsOLD().

Explained the two difficult cases when integer boolean contents differ from floating point boolean contents.
I was a bit concerned about people calling setBooleanContents() after setBooleanFloatContents() so I've
noted that setBooleanContents() affects both in the comments.

Removed the need to update all (including out-of-tree) targets.

[dsanders]

include/llvm/Target/TargetLowering.h

960

That makes sense to me. I've made this change in the updated patch. I've also added a comment that should ensure that people call setBooleanFloatContents() after setBooleanContents().

[hfinkel]

Assuming you take my suggestion regarding setBooleanContents (or otherwise make it so that the function-call order does not matter), LGTM. Thanks!

include/llvm/Target/TargetLowering.h

966

I'd really prefer that you do this as I suggested:
void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; BooleanFloatContents = Ty; }

void setBooleanContents(BooleanContent Ty, BooleanContent FTy) { BooleanContents = Ty; BooleanFloatContents = FTy; }

The reason is that, as you've implemented it, the order in which you call setBooleanContents and setBooleanFloatContents matters, and I think that will prove confusing.

[hfinkel]

• Original Message -----

From: "Daniel Sanders" <[e-mail]>
To: "daniel sanders" <[e-mail]>
Cc: [e-mail], "justin holewinski" <[e-mail]>, [e-mail],
[e-mail]
Sent: Wednesday, July 9, 2014 2:31:53 PM
Subject: Re: [PATCH] Make it possible for ints/floats to return different values from getBooleanContents()

Comment at: include/llvm/Target/TargetLowering.h:960
@@ +959,3 @@
+ /// value from i1 to a wider type. See getBooleanContents.
+ void setBooleanFloatContents(BooleanContent Ty) {
BooleanFloatContents = Ty; }

+

[e-mail] wrote:

I would really like to do this without causing churn to all of the
targets (and causing pain for all out-of-tree targets). How about
we do this:

void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty;
BooleanFloatContents = Ty; }

void setBooleanContents(BooleanContent Ty, BooleanContent FTy) {
BooleanContents = Ty; BooleanFloatContents = FTy; }

do that the current target code will continue to do the right
thing.

That makes sense to me. I've made this change in the updated patch.
I've also added a comment that should ensure that people call
setBooleanFloatContents() after setBooleanContents().

Now you see I was so speedy with my review, that I submitted it before I saw this reply ;) -- I stand by my preference, however. I think that, even with a comment, someone will manage to incorrectly order these as they refactor code.

Thanks again,
Hal

http://reviews.llvm.org/D4389

[dsanders]

include/llvm/Target/TargetLowering.h

966

Sorry, I'm trying to do a couple things in parallel at the moment and I didn't notice that it was an overloaded function. I agree that the overloaded function approach is better because it's harder to make mistakes. I'll do another update to switch to your suggestion.

[dsanders]

Correctly implement Hal's suggestion.

[hfinkel]

LGTM. Thanks!

include/llvm/CodeGen/SelectionDAG.h

#endif
   SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
 
   /// getZeroExtendInReg - Return the expression required to zero extend the Op
   /// value assuming it was the smaller SrcTy value.
   SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);
 
   /// getBoolExtOrTrunc - Convert Op, which must be of integer type, to the
   /// integer type VT, by using an extension appropriate for the target's
-  /// BooleanContent or truncating it.
-  SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT);
+  /// BooleanContent for type OpVT or truncating it.
+  SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT);
 
   /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
   SDValue getNOT(SDLoc DL, SDValue Val, EVT VT);
 
   /// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
   SDValue getLogicalNOT(SDLoc DL, SDValue Val, EVT VT);
 
   /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have

include/llvm/Target/TargetLowering.h

public:
   ///
   /// "Boolean values" are special true/false values produced by nodes like
   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
   /// Not to be confused with general values promoted from i1.  Some cpus
   /// distinguish between vectors of boolean and scalars; the isVec parameter
   /// selects between the two kinds.  For example on X86 a scalar boolean should
   /// be zero extended from i1, while the elements of a vector of booleans
   /// should be sign extended from i1.
-  BooleanContent getBooleanContents(bool isVec) const {
+  ///
+  /// Some cpus also treat floating point types the same way as they treat
+  /// vectors instead of the way they treat scalars.
+  BooleanContent getBooleanContentsOLD(bool isVec) const {
     return isVec ? BooleanVectorContents : BooleanContents;
   }
 
+  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
+    if (isVec)
+      return BooleanVectorContents;
+    return isFloat ? BooleanFloatContents : BooleanContents;
+  }
+
+  BooleanContent getBooleanContents(EVT Type) const {
+    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
+  }
+
   /// Return target scheduling preference.
   Sched::Preference getSchedulingPreference() const {
     return SchedPreferenceInfo;
   }
 
   /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
   /// for different nodes. This function returns the preference (or none) for
   /// the given node.
public:
   /// \brief Reset the operation actions based on target options.
   virtual void resetOperationActions() {}
 
 protected:
   /// Specify how the target extends the result of a boolean value from i1 to a
   /// wider type.  See getBooleanContents.
   void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
 
+  /// Specify how the target extends the result of a floating point boolean
+  /// value from i1 to a wider type.  See getBooleanContents.
+  void setBooleanFloatContents(BooleanContent Ty) { BooleanFloatContents = Ty; }
+
   /// Specify how the target extends the result of a vector boolean value from a
   /// vector of i1 to a wider type.  See getBooleanContents.
   void setBooleanVectorContents(BooleanContent Ty) {
     BooleanVectorContents = Ty;
   }
 
   /// Specify the target scheduling preference.
   void setSchedulingPreference(Sched::Preference Pref) {
     SchedPreferenceInfo = Pref;
   }
 
   /// Indicate whether this target prefers to use _setjmp to implement
   /// llvm.setjmp or the version without _.  Defaults to false.
private:
 
   /// Number of blocks threshold to use jump tables.
   int MinimumJumpTableEntries;
 
   /// Information about the contents of the high-bits in boolean values held in
   /// a type wider than i1. See getBooleanContents.
   BooleanContent BooleanContents;
 
+  /// Information about the contents of the high-bits in boolean values held in
+  /// a type wider than i1. See getBooleanContents.
+  BooleanContent BooleanFloatContents;
+
   /// Information about the contents of the high-bits in boolean vector values
   /// when the element type is wider than i1. See getBooleanContents.
   BooleanContent BooleanVectorContents;
 
   /// The target scheduling preference: shortest possible total cycles or lowest
   /// register usage.
   Sched::Preference SchedPreferenceInfo;
 

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitSHL(SDNode *N) {
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
     if (FoldedVOp.getNode()) return FoldedVOp;
 
     BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
     // If setcc produces all-one true value then:
     // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
     if (N1CV && N1CV->isConstant()) {
-      if (N0.getOpcode() == ISD::AND &&
-          TLI.getBooleanContents(true) ==
-          TargetLowering::ZeroOrNegativeOneBooleanContent) {
+      if (N0.getOpcode() == ISD::AND) {
         SDValue N00 = N0->getOperand(0);
         SDValue N01 = N0->getOperand(1);
         BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
 
-        if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC) {
+        if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
+            TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
+                TargetLowering::ZeroOrNegativeOneBooleanContent) {
           SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
           if (C.getNode())
             return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
         }
       } else {
         N1C = isConstOrConstSplat(N1);
       }
     }
if (N0C && !N0C->isNullValue())
     return N1;
   // fold (select false, X, Y) -> Y
   if (N0C && N0C->isNullValue())
     return N2;
   // fold (select C, 1, X) -> (or C, X)
   if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
     return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
   // fold (select C, 0, 1) -> (xor C, 1)
+  // We can't do this reliably if integer based booleans have different contents
+  // to floating point based booleans.
   if (VT.isInteger() &&
-      (VT0 == MVT::i1 ||
-       (VT0.isInteger() &&
-        TLI.getBooleanContents(false) ==
+      (VT0 == MVT::i1 || (VT0.isInteger() &&
+                          TLI.getBooleanContents(false, false) ==
+                              TLI.getBooleanContents(false, true) &&
+                          TLI.getBooleanContents(false, false) ==
                               TargetLowering::ZeroOrOneBooleanContent)) &&
       N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
     SDValue XORNode;
     if (VT == VT0)
       return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
                          N0, DAG.getConstant(1, VT0));
     XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
                           N0, DAG.getConstant(1, VT0));
     AddToWorkList(XORNode.getNode());
if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
         ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
                         ISD::SIGN_EXTEND);
         return SDValue(N, 0);   // Return N so it doesn't get rechecked!
       }
     }
   }
 
   if (N0.getOpcode() == ISD::SETCC) {
+    EVT N0VT = N0.getOperand(0).getValueType();
     // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
     // Only do this before legalize for now.
     if (VT.isVector() && !LegalOperations &&
-        TLI.getBooleanContents(true) ==
+        TLI.getBooleanContents(N0VT) ==
             TargetLowering::ZeroOrNegativeOneBooleanContent) {
-      EVT N0VT = N0.getOperand(0).getValueType();
       // On some architectures (such as SSE/NEON/etc) the SETCC result type is
       // of the same size as the compared operands. Only optimize sext(setcc())
       // if this is the case.
       EVT SVT = getSetCCResultType(N0VT);
 
       // We know that the # elements of the results is the same as the
       // # elements of the compare (and the # elements of the compare result
       // for that matter).  Check to see that they are the same size.  If so,
if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
       SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
 
       return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
     }
   }
 
   // fold select C, 16, 0 -> shl C, 4
   if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
-    TLI.getBooleanContents(N0.getValueType().isVector()) ==
+      TLI.getBooleanContents(N0.getValueType()) ==
           TargetLowering::ZeroOrOneBooleanContent) {
 
     // If the caller doesn't want us to simplify this into a zext of a compare,
     // don't do it.
     if (NotExtCompare && N2C->getAPIntValue() == 1)
       return SDValue();
 
     // Get a SetCC of the condition
     // NOTE: Don't create a SETCC if it's not legal on this target.

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case ISD::SSUBO: {
     SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
                                       Node->getOpcode() == ISD::SADDO ?
                                       ISD::SETEQ : ISD::SETNE);
 
     SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
     SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
 
     SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
-    Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType));
+    Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
     break;
   }
   case ISD::UADDO:
   case ISD::USUBO: {
     SDValue LHS = Node->getOperand(0);
     SDValue RHS = Node->getOperand(1);
     SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
                               ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
                               LHS, RHS);
     Results.push_back(Sum);
 
     EVT ResultType = Node->getValueType(1);
     EVT SetCCType = getSetCCResultType(Node->getValueType(0));
     ISD::CondCode CC
       = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
     SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
 
-    Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType));
+    Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
     break;
   }
   case ISD::UMULO:
   case ISD::SMULO: {
     EVT VT = Node->getValueType(0);
     EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
     SDValue LHS = Node->getOperand(0);
     SDValue RHS = Node->getOperand(1);
if (Legalized) {
       Results.push_back(Tmp1);
       break;
     }
 
     // Otherwise, SETCC for the given comparison type must be completely
     // illegal; expand it into a SELECT_CC.
     EVT VT = Node->getValueType(0);
     int TrueValue;
-    switch (TLI.getBooleanContents(VT.isVector())) {
+    switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
     case TargetLowering::ZeroOrOneBooleanContent:
     case TargetLowering::UndefinedBooleanContent:
       TrueValue = 1;
       break;
     case TargetLowering::ZeroOrNegativeOneBooleanContent:
       TrueValue = -1;
       break;
     }

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

return DAG.getSelect(SDLoc(N),
                        LHS.getValueType(), N->getOperand(0), LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
   SDValue Mask = N->getOperand(0);
   EVT OpTy = N->getOperand(1).getValueType();
 
   // Promote all the way up to the canonical SetCC type.
-  Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy));
+  Mask = PromoteTargetBoolean(Mask, OpTy);
   SDValue LHS = GetPromotedInteger(N->getOperand(1));
   SDValue RHS = GetPromotedInteger(N->getOperand(2));
   return DAG.getNode(ISD::VSELECT, SDLoc(N),
                      LHS.getValueType(), Mask, LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
   SDValue LHS = GetPromotedInteger(N->getOperand(2));
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
                                 N->getOperand(1), LHS, RHS, N->getOperand(4)),
                  0);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
   assert(OpNo == 1 && "only know how to promote condition");
 
   // Promote all the way up to the canonical SetCC type.
-  EVT SVT = getSetCCResultType(MVT::Other);
-  SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
+  SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
 
   // The chain (Op#0) and basic block destination (Op#2) are always legal types.
   return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
                                         N->getOperand(2)), 0);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
   // Since the result type is legal, the operands must promote to it.

 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
   assert(OpNo == 0 && "Only know how to promote the condition!");
   SDValue Cond = N->getOperand(0);
   EVT OpTy = N->getOperand(1).getValueType();
 
   // Promote all the way up to the canonical SetCC type.
-  EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ?
-                                   OpTy.getScalarType() : OpTy);
-  Cond = PromoteTargetBoolean(Cond, SVT);
+  EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
+  Cond = PromoteTargetBoolean(Cond, OpVT);
 
   return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
                                         N->getOperand(2)), 0);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
   assert(OpNo == 0 && "Don't know how to promote this operand!");
 

lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index);
   SDValue JoinIntegers(SDValue Lo, SDValue Hi);
   SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
   
   std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
                                                  SDNode *Node, bool isSigned);
   std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
 
-  SDValue PromoteTargetBoolean(SDValue Bool, EVT VT);
+  SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT);
   void ReplaceValueWith(SDValue From, SDValue To);
   void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
   void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
                     SDValue &Lo, SDValue &Hi);
 
   //===--------------------------------------------------------------------===//
   // Integer Promotion Support: LegalizeIntegerTypes.cpp
   //===--------------------------------------------------------------------===//

lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

DAGTypeLegalizer::ExpandChainLibCall(RTLIB::Libcall LC,
   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
 
   return CallInfo;
 }
 
 /// PromoteTargetBoolean - Promote the given target boolean to a target boolean
 /// of the given type.  A target boolean is an integer value, not necessarily of
 /// type i1, the bits of which conform to getBooleanContents.
-SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) {
+///
+/// ValVT is the type of values that produced the boolean.
+SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT ValVT) {
   SDLoc dl(Bool);
+  EVT BoolVT = getSetCCResultType(ValVT);
   ISD::NodeType ExtendCode =
-    TargetLowering::getExtendForContent(TLI.getBooleanContents(VT.isVector()));
-  return DAG.getNode(ExtendCode, dl, VT, Bool);
+      TargetLowering::getExtendForContent(TLI.getBooleanContents(ValVT));
+  return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
 }
 
 /// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
 /// bits in Hi.
 void DAGTypeLegalizer::SplitInteger(SDValue Op,
                                     EVT LoVT, EVT HiVT,
                                     SDValue &Lo, SDValue &Hi) {
   SDLoc dl(Op);

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
   // AND,OR,XOR, we will have to scalarize the op.
   // Notice that the operation may be 'promoted' which means that it is
   // 'bitcasted' to another type which is handled.
   // This operation also isn't safe with AND, OR, XOR when the boolean
   // type is 0/1 as we need an all ones vector constant to mask with.
   // FIXME: Sign extend 1 to all ones if thats legal on the target.
   if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
       TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
-      TLI.getOperationAction(ISD::OR,  VT) == TargetLowering::Expand ||
-      TLI.getBooleanContents(true) !=
+      TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
+      TLI.getBooleanContents(Op1.getValueType()) !=
           TargetLowering::ZeroOrNegativeOneBooleanContent)
     return DAG.UnrollVectorOp(Op.getNode());
 
   // If the mask and the type are different sizes, unroll the vector op. This
   // can occur when getSetCCResultType returns something that is different in
   // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
   if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
     return DAG.UnrollVectorOp(Op.getNode());
 

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
   if (InOp.getValueType() != EltVT)
     return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
   return InOp;
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
   SDValue Cond = GetScalarizedVector(N->getOperand(0));
   SDValue LHS = GetScalarizedVector(N->getOperand(1));
-  TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false);
-  TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true);
+  TargetLowering::BooleanContent ScalarBool =
+      TLI.getBooleanContents(false, false);
+  TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
+
+  // If integer and float booleans have different contents then we can't
+  // reliably optimize in all cases.
+  if (TLI.getBooleanContents(false, false) !=
+      TLI.getBooleanContents(false, true)) {
+    // At least try the common case where the boolean is generated by a
+    // comparison.
+    if (Cond->getOpcode() == ISD::SETCC) {
+      EVT OpVT = Cond->getOperand(0)->getValueType(0);
+      ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
+      VecBool = TLI.getBooleanContents(OpVT);
+    } else
+      ScalarBool = TargetLowering::UndefinedBooleanContent;
+  }
+
   if (ScalarBool != VecBool) {
     EVT CondVT = Cond.getValueType();
     switch (ScalarBool) {
       case TargetLowering::UndefinedBooleanContent:
         break;
       case TargetLowering::ZeroOrOneBooleanContent:
         assert(VecBool == TargetLowering::UndefinedBooleanContent ||
                VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
   }
 
   // Turn it into a scalar SETCC.
   SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
                             N->getOperand(2));
   // Vectors may have a different boolean contents to scalars.  Promote the
   // value appropriately.
   ISD::NodeType ExtendCode =
-    TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
+      TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
   return DAG.getNode(ExtendCode, DL, NVT, Res);
 }
 
 
 //===----------------------------------------------------------------------===//
 //  Operand Vector Scalarization <1 x ty> -> ty.
 //===----------------------------------------------------------------------===//
 

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 }
 
 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) {
   return VT.bitsGT(Op.getValueType()) ?
     getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
     getNode(ISD::TRUNCATE, DL, VT, Op);
 }
 
-SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT) {
+SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT,
+                                        EVT OpVT) {
   if (VT.bitsLE(Op.getValueType()))
     return getNode(ISD::TRUNCATE, SL, VT, Op);
 
-  TargetLowering::BooleanContent BType = TLI->getBooleanContents(VT.isVector());
+  TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT);
   return getNode(TLI->getExtendForContent(BType), SL, VT, Op);
 }
 
 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) {
   assert(!VT.isVector() &&
          "getZeroExtendInReg should use the vector element type instead of "
          "the vector type!");
   if (Op.getValueType() == VT) return Op;
SDValue SelectionDAG::getNOT(SDLoc DL, SDValue Val, EVT VT) {
   SDValue NegOne =
     getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
   return getNode(ISD::XOR, DL, VT, Val, NegOne);
 }
 
 SDValue SelectionDAG::getLogicalNOT(SDLoc DL, SDValue Val, EVT VT) {
   EVT EltVT = VT.getScalarType();
   SDValue TrueValue;
-  switch (TLI->getBooleanContents(VT.isVector())) {
+  switch (TLI->getBooleanContents(VT)) {
     case TargetLowering::ZeroOrOneBooleanContent:
     case TargetLowering::UndefinedBooleanContent:
       TrueValue = getConstant(1, VT);
       break;
     case TargetLowering::ZeroOrNegativeOneBooleanContent:
       TrueValue = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()),
                               VT);
       break;
SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
   // These setcc operations always fold.
   switch (Cond) {
   default: break;
   case ISD::SETFALSE:
   case ISD::SETFALSE2: return getConstant(0, VT);
   case ISD::SETTRUE:
   case ISD::SETTRUE2: {
     const TargetLowering *TLI = TM.getTargetLowering();
-    TargetLowering::BooleanContent Cnt = TLI->getBooleanContents(VT.isVector());
+    TargetLowering::BooleanContent Cnt =
+        TLI->getBooleanContents(N1->getValueType(0));
     return getConstant(
         Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
   }
 
   case ISD::SETOEQ:
   case ISD::SETOGT:
   case ISD::SETOGE:
   case ISD::SETOLT:
void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
   case ISD::SADDO:
   case ISD::UADDO:
   case ISD::SSUBO:
   case ISD::USUBO:
   case ISD::SMULO:
   case ISD::UMULO:
     if (Op.getResNo() != 1)
       break;
-    // The boolean result conforms to getBooleanContents.  Fall through.
+    // The boolean result conforms to getBooleanContents.
+    // If we know the result of a setcc has the top bits zero, use this info.
+    // We know that we have an integer-based boolean since these operations
+    // are only available for integer.
+    if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
+            TargetLowering::ZeroOrOneBooleanContent &&
+        BitWidth > 1)
+      KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
+    break;
   case ISD::SETCC:
     // If we know the result of a setcc has the top bits zero, use this info.
-    if (TLI->getBooleanContents(Op.getValueType().isVector()) ==
-        TargetLowering::ZeroOrOneBooleanContent && BitWidth > 1)
+    if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
+            TargetLowering::ZeroOrOneBooleanContent &&
+        BitWidth > 1)
       KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     break;
   case ISD::SHL:
     // (shl X, C1) & C2 == 0   iff   (X & C2 >>u C1) == 0
     if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = SA->getZExtValue();
 
       // If the shift count is an invalid immediate, don't do anything.
unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
   case ISD::UADDO:
   case ISD::SSUBO:
   case ISD::USUBO:
   case ISD::SMULO:
   case ISD::UMULO:
     if (Op.getResNo() != 1)
       break;
     // The boolean result conforms to getBooleanContents.  Fall through.
+    // If setcc returns 0/-1, all bits are sign bits.
+    // We know that we have an integer-based boolean since these operations
+    // are only available for integer.
+    if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
+        TargetLowering::ZeroOrNegativeOneBooleanContent)
+      return VTBits;
+    break;
   case ISD::SETCC:
     // If setcc returns 0/-1, all bits are sign bits.
-    if (TLI->getBooleanContents(Op.getValueType().isVector()) ==
+    if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
         TargetLowering::ZeroOrNegativeOneBooleanContent)
       return VTBits;
     break;
   case ISD::ROTL:
   case ISD::ROTR:
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       unsigned RotAmt = C->getZExtValue() & (VTBits-1);
 

lib/CodeGen/SelectionDAG/TargetLowering.cpp

static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
   return (KnownZero.countPopulation() == BitWidth - 1) &&
          (KnownOne.countPopulation() == 1);
 }
 
 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
   if (!N)
     return false;
 
-  bool IsVec = false;
   const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
   if (!CN) {
     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
     if (!BV)
       return false;
 
-    IsVec = true;
     CN = BV->getConstantSplatValue();
   }
 
-  switch (getBooleanContents(IsVec)) {
+  switch (getBooleanContents(N->getValueType(0))) {
   case UndefinedBooleanContent:
     return CN->getAPIntValue()[0];
   case ZeroOrOneBooleanContent:
     return CN->isOne();
   case ZeroOrNegativeOneBooleanContent:
     return CN->isAllOnesValue();
   }
 
   llvm_unreachable("Invalid boolean contents");
 }
 
 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
   if (!N)
     return false;
 
-  bool IsVec = false;
   const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
   if (!CN) {
     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
     if (!BV)
       return false;
 
-    IsVec = true;
     CN = BV->getConstantSplatValue();
   }
 
-  if (getBooleanContents(IsVec) == UndefinedBooleanContent)
+  if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
     return !CN->getAPIntValue()[0];
 
   return CN->isNullValue();
 }
 
 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
 /// and cc. If it is unable to simplify it, return a null SDValue.
 SDValue
 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
                               ISD::CondCode Cond, bool foldBooleans,
                               DAGCombinerInfo &DCI, SDLoc dl) const {
   SelectionDAG &DAG = DCI.DAG;
 
   // These setcc operations always fold.
   switch (Cond) {
   default: break;
   case ISD::SETFALSE:
   case ISD::SETFALSE2: return DAG.getConstant(0, VT);
   case ISD::SETTRUE:
   case ISD::SETTRUE2: {
-    TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector());
+    TargetLowering::BooleanContent Cnt =
+        getBooleanContents(N0->getValueType(0));
     return DAG.getConstant(
         Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
   }
   }
 
   // Ensure that the constant occurs on the RHS, and fold constant
   // comparisons.
   ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
         if (DCI.isBeforeLegalizeOps() ||
             (isOperationLegal(ISD::SETCC, newVT) &&
              getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
           EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
           SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
 
           SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
                                           NewConst, Cond);
-          return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT);
+          return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
         }
         break;
       }
       default:
         break;   // todo, be more careful with signed comparisons
       }
     } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
                               N0.getOperand(1));
           }
 
           return DAG.getSetCC(dl, VT, Val, N1,
                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
         }
       } else if (N1C->getAPIntValue() == 1 &&
                  (VT == MVT::i1 ||
-                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
+                  getBooleanContents(N0->getValueType(0)) ==
+                      ZeroOrOneBooleanContent)) {
         SDValue Op0 = N0;
         if (Op0.getOpcode() == ISD::TRUNCATE)
           Op0 = Op0.getOperand(0);
 
         if ((Op0.getOpcode() == ISD::XOR) &&
             Op0.getOperand(0).getOpcode() == ISD::SETCC &&
             Op0.getOperand(1).getOpcode() == ISD::SETCC) {
           // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
       }
     }
   }
 
   if (N0 == N1) {
     // The sext(setcc()) => setcc() optimization relies on the appropriate
     // constant being emitted.
     uint64_t EqVal = 0;
-    switch (getBooleanContents(N0.getValueType().isVector())) {
+    switch (getBooleanContents(N0.getValueType())) {
     case UndefinedBooleanContent:
     case ZeroOrOneBooleanContent:
       EqVal = ISD::isTrueWhenEqual(Cond);
       break;
     case ZeroOrNegativeOneBooleanContent:
       EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
       break;
     }

lib/CodeGen/TargetLoweringBase.cpp

TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
   Pow2DivIsCheap = false;
   JumpIsExpensive = false;
   PredictableSelectIsExpensive = false;
   MaskAndBranchFoldingIsLegal = false;
   StackPointerRegisterToSaveRestore = 0;
   ExceptionPointerRegister = 0;
   ExceptionSelectorRegister = 0;
   BooleanContents = UndefinedBooleanContent;
+  BooleanFloatContents = UndefinedBooleanContent;
   BooleanVectorContents = UndefinedBooleanContent;
   SchedPreferenceInfo = Sched::ILP;
   JumpBufSize = 0;
   JumpBufAlignment = 0;
   MinFunctionAlignment = 0;
   PrefFunctionAlignment = 0;
   PrefLoopAlignment = 0;
   MinStackArgumentAlignment = 1;

lib/Target/AArch64/AArch64ISelLowering.cpp

 
 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
     : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
   Subtarget = &TM.getSubtarget<AArch64Subtarget>();
 
   // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
   // we have to make something up. Arbitrarily, choose ZeroOrOne.
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   // When comparing vectors the result sets the different elements in the
   // vector to all-one or all-zero.
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
   addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
 

lib/Target/MSP430/MSP430ISelLowering.cpp

MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
 
   // Provide all sorts of operation actions
 
   // Division is expensive
   setIntDivIsCheap(false);
 
   setStackPointerRegisterToSaveRestore(MSP430::SPW);
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // We have post-incremented loads / stores.
   setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
   setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
 
   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);

lib/Target/Mips/MipsISelLowering.cpp

 }
 
 MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
     : TargetLowering(TM, new MipsTargetObjectFile()),
       Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
+  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
+  // does.
+  if (Subtarget->hasMips32r6())
+    setBooleanFloatContents(ZeroOrNegativeOneBooleanContent);
 
   // Load extented operations for i1 types must be promoted
   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
 
   // MIPS doesn't have extending float->double load/store
   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);

lib/Target/NVPTX/NVPTXISelLowering.cpp

NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
   // always lower memset, memcpy, and memmove intrinsics to load/store
   // instructions, rather
   // then generating calls to memset, mempcy or memmove.
   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
 
   setBooleanContents(ZeroOrNegativeOneBooleanContent);
+  setBooleanFloatContents(ZeroOrNegativeOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
   // condition branches.
   setJumpIsExpensive(true);
 
   // By default, use the Source scheduling
   if (sched4reg)

lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   }
 
   setOperationAction(ISD::ATOMIC_LOAD,  MVT::i32, Expand);
   setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
   setOperationAction(ISD::ATOMIC_LOAD,  MVT::i64, Expand);
   setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
 
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   // Altivec instructions set fields to all zeros or all ones.
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   if (isPPC64) {
     setStackPointerRegisterToSaveRestore(PPC::X1);
     setExceptionPointerRegister(PPC::X3);
     setExceptionSelectorRegister(PPC::X4);
   } else {

lib/Target/R600/R600ISelLowering.cpp

R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   for (MVT VT : ScalarIntVTs) {
     setOperationAction(ISD::ADDC, VT, Expand);
     setOperationAction(ISD::SUBC, VT, Expand);
     setOperationAction(ISD::ADDE, VT, Expand);
     setOperationAction(ISD::SUBE, VT, Expand);
   }
 
   setBooleanContents(ZeroOrNegativeOneBooleanContent);
+  setBooleanFloatContents(ZeroOrNegativeOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
   setSchedulingPreference(Sched::Source);
 }
 
 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
     MachineInstr * MI, MachineBasicBlock * BB) const {
   MachineFunction * MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/SystemZ/SystemZISelLowering.cpp

SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
 
   // TODO: It may be better to default to latency-oriented scheduling, however
   // LLVM's current latency-oriented scheduler can't handle physreg definitions
   // such as SystemZ has with CC, so set this to the register-pressure
   // scheduler, because it can.
   setSchedulingPreference(Sched::RegPressure);
 
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // Instructions are strings of 2-byte aligned 2-byte values.
   setMinFunctionAlignment(2);
 
   // Handle operations that are handled in a similar way for all types.
   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
        I <= MVT::LAST_FP_VALUETYPE;

lib/Target/X86/X86ISelLowering.cpp

void X86TargetLowering::resetOperationActions() {
 
   TO = TM.Options;
 
   // Set up the TargetLowering object.
   static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
 
   // X86 is weird, it always uses i8 for shift amounts and setcc results.
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   // For 64-bit since we have so many registers use the ILP scheduler, for
   // 32-bit code use the register pressure specific scheduling.
   // For Atom, always use ILP scheduling.
   if (Subtarget->isAtom())
     setSchedulingPreference(Sched::ILP);

lib/Target/XCore/XCoreISelLowering.cpp

XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM)
   setIntDivIsCheap(false);
 
   setStackPointerRegisterToSaveRestore(XCore::SP);
 
   setSchedulingPreference(Sched::Source);
 
   // Use i32 for setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanFloatContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // XCore does not have the NodeTypes below.
   setOperationAction(ISD::BR_CC,     MVT::i32,   Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i32,   Expand);
   setOperationAction(ISD::ADDC, MVT::i32, Expand);
   setOperationAction(ISD::ADDE, MVT::i32, Expand);
   setOperationAction(ISD::SUBC, MVT::i32, Expand);

test/CodeGen/Mips/fcmp.ll

 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ogt_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: oge_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: olt_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ole_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: one_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ord_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ueq_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ugt_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uge_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ult_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ule_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: une_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uno_f32:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @true_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: true_f32:

 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ogt_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: oge_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: olt_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ole_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: one_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ord_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ueq_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ugt_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uge_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ult_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ule_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: une_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
 ; 64-C-DAG:      movf $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG:    not $2, $[[T1]]
+; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    not $2, $[[T1]]
+; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uno_f64:
 
 ; 32-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 32-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 64-C-DAG:      addiu $[[T0:2]], $zero, 0
 ; 64-C-DAG:      addiu $[[T1:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
 ; 64-C-DAG:      movt $[[T0]], $1, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG:    mfc1 $2, $[[T0]]
+; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $2, $[[T0]]
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uno double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @true_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: true_f64:
 ; ALL:           addiu $2, $zero, 1
 
   %1 = fcmp true double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

test/CodeGen/Mips/select.ll

 ; 32R2:          c.eq.s $[[F2]], $[[F3]]
 ; 32R2:          movt $5, $4, $fcc0
 ; 32R2:          move $2, $5
 
 ; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
 ; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
 ; 32R6:          cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64:            c.eq.s $f14, $f15
 ; 64:            movt $5, $4, $fcc0
 ; 64:            move $2, $5
 
 ; 64R2:          c.eq.s $f14, $f15
 ; 64R2:          movt $5, $4, $fcc0
 ; 64R2:          move $2, $5
 
 ; 64R6:          cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
   %cmp = fcmp oeq float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
 }
 

 ; 32R2:          c.olt.s $[[F2]], $[[F3]]
 ; 32R2:          movt $5, $4, $fcc0
 ; 32R2:          move $2, $5
 
 ; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
 ; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
 ; 32R6:          cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64:            c.olt.s $f14, $f15
 ; 64:            movt $5, $4, $fcc0
 ; 64:            move $2, $5
 
 ; 64R2:          c.olt.s $f14, $f15
 ; 64R2:          movt $5, $4, $fcc0
 ; 64R2:          move $2, $5
 
 ; 64R6:          cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
   %cmp = fcmp olt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
 }
 
 define i32 @f32_fcmp_ogt_i32_val(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {

 ; 32R2:          c.ule.s $[[F2]], $[[F3]]
 ; 32R2:          movf $5, $4, $fcc0
 ; 32R2:          move $2, $5
 
 ; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
 ; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
 ; 32R6:          cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64:            c.ule.s $f14, $f15
 ; 64:            movf $5, $4, $fcc0
 ; 64:            move $2, $5
 
 ; 64R2:          c.ule.s $f14, $f15
 ; 64R2:          movf $5, $4, $fcc0
 ; 64R2:          move $2, $5
 
 ; 64R6:          cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
 }
 

 ; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
 ; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
 ; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
 ; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 32R6:          cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
 ; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)

 ; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
 ; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
 ; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 64R6:          cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
   %tmp = load double* @d2, align 8
   %tmp1 = load double* @d3, align 8
   %cmp = fcmp oeq double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond

 ; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
 ; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
 ; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
 ; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 32R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
 ; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)

 ; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
 ; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
 ; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 64R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
   %tmp = load double* @d2, align 8
   %tmp1 = load double* @d3, align 8
   %cmp = fcmp olt double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond

 ; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
 ; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
 ; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
 ; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 32R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
 ; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 32R6:          or $2, $[[NE]], $[[EQ]]
 
 ; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
 ; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)

 ; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
 ; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
 ; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
 ; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
 ; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
 ; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
 ; 64R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
 ; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
 ; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
 ; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
 ; 64R6:          or $2, $[[NE]], $[[EQ]]
 
   %tmp = load double* @d2, align 8
   %tmp1 = load double* @d3, align 8
   %cmp = fcmp ogt double %tmp, %tmp1
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
 }