[NewGVN] Update phi-of-ops def block when updating existing ValuePHI.

[fhahn]

Summary

In case we update a ValuePHI node created earlier, we could update it
based on a different OpPHI which could be in a different block.
We need to update the TempToBlock mapping reflecting the new block,
otherwise we would end up placing the new phi node in a wrong block.

This problem is exposed by the test case in
https://bugs.llvm.org/show_bug.cgi?id=36504.

This patch fixes a slightly simpler problem than in the bug report. In
the bug's re-producer, the additional problem is that we are re-using a
ValuePHI node with to few incoming values for the new OpPHI. If this
patch makes sense, I will follow it up with a patch that creates a new
PHI node if the existing PHI node has a different number of incoming
values.

[• dberlin]

This is definitely correct.
Note that this also means we are likely leaving around TempToBlock mappings for ops because we don't remove them in removePhiOfOps.
(But that would require reference counting ATM, i believe, because they may be reused).
This shouldn't hurt anything, i believe.

[• dberlin]

Can you just use update_test_checks to generate the CHECK lines? We are trying to use it for all the newgvn tests.

[fhahn]

Create check lines using update_test_checks.py

llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp

if (!ValuePHI) {
       addPhiOfOps(ValuePHI, PHIBlock, I);
       NewPHI = true;
       NumGVNPHIOfOpsCreated++;
     }
     if (NewPHI) {
       for (auto PHIOp : Ops)
         ValuePHI->addIncoming(PHIOp.first, PHIOp.second);
     } else {
+      TempToBlock[ValuePHI] = PHIBlock;
       unsigned int i = 0;
       for (auto PHIOp : Ops) {
         ValuePHI->setIncomingValue(i, PHIOp.first);
         ValuePHI->setIncomingBlock(i, PHIOp.second);
         ++i;
       }
     }
     RevisitOnReachabilityChange[PHIBlock].set(InstrToDFSNum(I));

llvm/trunk/test/Transforms/NewGVN/phi-of-ops-move-block.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -newgvn -S | FileCheck %s
+
+@g_20 = external global i32, align 4
+
+define void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD1:%.*]], [[CRITEDGE:%.*]] ]
+; CHECK-NEXT:    store i32 [[STOREMERGE]], i32* @g_20, align 4
+; CHECK-NEXT:    [[CMP0:%.*]] = icmp eq i32 [[STOREMERGE]], 0
+; CHECK-NEXT:    br i1 [[CMP0]], label [[LR_PH:%.*]], label [[CRITEDGE]]
+; CHECK:       lr.ph:
+; CHECK-NEXT:    [[LV:%.*]] = load i64, i64* inttoptr (i64 16 to i64*), align 16
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[LV]], 0
+; CHECK-NEXT:    br i1 [[CMP1]], label [[PREHEADER_SPLIT:%.*]], label [[CRITEDGE]]
+; CHECK:       preheader.split:
+; CHECK-NEXT:    br label [[PREHEADER_SPLIT]]
+; CHECK:       critedge:
+; CHECK-NEXT:    [[PHIOFOPS1:%.*]] = phi i1 [ false, [[BB1]] ], [ true, [[LR_PH]] ]
+; CHECK-NEXT:    [[PHIOFOPS:%.*]] = phi i1 [ [[CMP0]], [[BB1]] ], [ true, [[LR_PH]] ]
+; CHECK-NEXT:    [[DOT05_LCSSA:%.*]] = phi i32 [ 0, [[BB1]] ], [ -1, [[LR_PH]] ]
+; CHECK-NEXT:    [[ADD1]] = add nsw i32 [[STOREMERGE]], -1
+; CHECK-NEXT:    br i1 [[PHIOFOPS]], label [[BB1]], label [[END:%.*]]
+; CHECK:       end:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %bb1
+
+bb1:                                      ; preds = %critedge, %entry
+  %storemerge = phi i32 [ 0, %entry ], [ %add1, %critedge ]
+  store i32 %storemerge, i32* @g_20, align 4
+  %cmp0 = icmp eq i32 %storemerge, 0
+  br i1 %cmp0, label %lr.ph, label %critedge
+
+lr.ph:                                           ; preds = %bb1
+  %lv = load i64, i64* inttoptr (i64 16 to i64*), align 16
+  %cmp1 = icmp eq i64 %lv, 0
+  br i1 %cmp1, label %preheader.split, label %critedge
+
+preheader.split:                                 ; preds = %lr.ph, %preheader.split
+  br label %preheader.split
+
+critedge:                                        ; preds = %lr.ph, %bb1
+  %.05.lcssa = phi i32 [ 0, %bb1 ], [ -1, %lr.ph ]
+  %cmp2 = icmp ne i32 %.05.lcssa, 0
+  %brmerge = or i1 %cmp0, %cmp2
+  %add1 = add nsw i32 %storemerge, -1
+  br i1 %brmerge, label %bb1, label %end
+
+end:
+  ret void
+}