[GlobalIsel][X86] Support G_PTRTOINT instruction.

[aivchenk]

Summary

Add legalization/selection for x86/x86_64 and
corresponding tests.

[igorb]

Hi,
Could you please add test for Legalizar pass?
I also suggest to add ll test to test all the passes together.

[igorb]

lib/Target/X86/X86InstructionSelector.cpp

691 ↗

(On Diff #135409)

DEBUG(dbgs() <<TII.getName(I.getOpcode()) <<" input/output on different banks\n");

[aivchenk]

addressed comments. Added legalizer and general tests

[igorb]

LGTM,
Thanks.

llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp

private:
   bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
                          MachineFunction &MF) const;
   bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
                              MachineFunction &MF) const;
   bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
                          MachineFunction &MF) const;
   bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
                       MachineFunction &MF) const;
-  bool selectTrunc(MachineInstr &I, MachineRegisterInfo &MRI,
+  bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
                              MachineFunction &MF) const;
   bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
                   MachineFunction &MF) const;
   bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
                     MachineFunction &MF) const;
   bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
                  MachineFunction &MF) const;
   bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
                    MachineFunction &MF) const;
bool X86InstructionSelector::select(MachineInstr &I,
   case TargetOpcode::G_FRAME_INDEX:
     return selectFrameIndexOrGep(I, MRI, MF);
   case TargetOpcode::G_GLOBAL_VALUE:
     return selectGlobalValue(I, MRI, MF);
   case TargetOpcode::G_CONSTANT:
     return selectConstant(I, MRI, MF);
   case TargetOpcode::G_FCONSTANT:
     return materializeFP(I, MRI, MF);
+  case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC:
-    return selectTrunc(I, MRI, MF);
+    return selectTruncOrPtrToInt(I, MRI, MF);
   case TargetOpcode::G_ZEXT:
     return selectZext(I, MRI, MF);
   case TargetOpcode::G_ANYEXT:
     return selectAnyext(I, MRI, MF);
   case TargetOpcode::G_ICMP:
     return selectCmp(I, MRI, MF);
   case TargetOpcode::G_UADDE:
     return selectUadde(I, MRI, MF);
bool X86InstructionSelector::selectConstant(MachineInstr &I,
   default:
     llvm_unreachable("Can't select G_CONSTANT, unsupported type.");
   }
 
   I.setDesc(TII.get(NewOpc));
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }
 
-// Helper function for selectTrunc and selectAnyext.
+// Helper function for selectTruncOrPtrToInt and selectAnyext.
 // Returns true if DstRC lives on a floating register class and
 // SrcRC lives on a 128-bit vector class.
 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC,
                             const TargetRegisterClass *SrcRC) {
   return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass ||
           DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) &&
          (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
 }
 
 bool X86InstructionSelector::selectTurnIntoCOPY(
     MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
     const TargetRegisterClass *DstRC, const unsigned SrcReg,
     const TargetRegisterClass *SrcRC) const {
 
   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
     DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
                  << " operand\n");
     return false;
   }
   I.setDesc(TII.get(X86::COPY));
   return true;
 }
 
-bool X86InstructionSelector::selectTrunc(MachineInstr &I,
+bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I,
                                                    MachineRegisterInfo &MRI,
                                                    MachineFunction &MF) const {
-  assert((I.getOpcode() == TargetOpcode::G_TRUNC) && "unexpected instruction");
+  assert((I.getOpcode() == TargetOpcode::G_TRUNC ||
+          I.getOpcode() == TargetOpcode::G_PTRTOINT) &&
+         "unexpected instruction");
 
   const unsigned DstReg = I.getOperand(0).getReg();
   const unsigned SrcReg = I.getOperand(1).getReg();
 
   const LLT DstTy = MRI.getType(DstReg);
   const LLT SrcTy = MRI.getType(SrcReg);
 
   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
 
   if (DstRB.getID() != SrcRB.getID()) {
-    DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
+    DEBUG(dbgs() << TII.getName(I.getOpcode())
+                 << " input/output on different banks\n");
     return false;
   }
 
   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
 
   if (!DstRC || !SrcRC)
     return false;
bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I,
   } else {
     return false;
   }
 
   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
 
   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
-    DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
+    DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+                 << "\n");
     return false;
   }
 
   I.getOperand(1).setSubReg(SubIdx);
 
   I.setDesc(TII.get(X86::COPY));
   return true;
 }

llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp

void X86LegalizerInfo::setLegalizerInfo32bit() {
 
   // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 
   setAction({G_GEP, p0}, Legal);
   setAction({G_GEP, 1, s32}, Legal);
 
+  if (!Subtarget.is64Bit())
+    getActionDefinitionsBuilder(G_PTRTOINT)
+        .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
+        .maxScalar(0, s32)
+        .widenScalarToNextPow2(0, /*Min*/ 8);
+
   // Control-flow
   setAction({G_BRCOND, s1}, Legal);
 
   // Constants
   for (auto Ty : {s8, s16, s32, p0})
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
 
   // Extensions
void X86LegalizerInfo::setLegalizerInfo32bit() {
   }
 }
 
 void X86LegalizerInfo::setLegalizerInfo64bit() {
 
   if (!Subtarget.is64Bit())
     return;
 
+  const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
+  const LLT s1 = LLT::scalar(1);
+  const LLT s8 = LLT::scalar(8);
+  const LLT s16 = LLT::scalar(16);
+  const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
   const LLT s128 = LLT::scalar(128);
 
   setAction({G_IMPLICIT_DEF, s64}, Legal);
   // Need to have that, as tryFoldImplicitDef will create this pattern:
   // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
   setAction({G_IMPLICIT_DEF, s128}, Legal);
 
   setAction({G_PHI, s64}, Legal);
 
   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
     setAction({BinOp, s64}, Legal);
 
   for (unsigned MemOp : {G_LOAD, G_STORE})
     setAction({MemOp, s64}, Legal);
 
   // Pointer-handling
   setAction({G_GEP, 1, s64}, Legal);
+  getActionDefinitionsBuilder(G_PTRTOINT)
+      .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
+      .maxScalar(0, s64)
+      .widenScalarToNextPow2(0, /*Min*/ 8);
 
   // Constants
   setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
 
   // Extensions
   for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
     setAction({extOp, s64}, Legal);
   }

llvm/trunk/test/CodeGen/X86/GlobalISel/ptrtoint.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=CHECK
+
+define i1 @ptrtoint_s1_p0(i64* %p) {
+; CHECK-LABEL: ptrtoint_s1_p0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = ptrtoint i64* %p to i1
+  ret i1 %0
+}
+
+define i8 @ptrtoint_s8_p0(i64* %p) {
+; CHECK-LABEL: ptrtoint_s8_p0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = ptrtoint i64* %p to i8
+  ret i8 %0
+}
+
+define i16 @ptrtoint_s16_p0(i64* %p) {
+; CHECK-LABEL: ptrtoint_s16_p0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = ptrtoint i64* %p to i16
+  ret i16 %0
+}
+
+define i32 @ptrtoint_s32_p0(i64* %p) {
+; CHECK-LABEL: ptrtoint_s32_p0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = ptrtoint i64* %p to i32
+  ret i32 %0
+}
+
+define i64 @ptrtoint_s64_p0(i64* %p) {
+; CHECK-LABEL: ptrtoint_s64_p0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = ptrtoint i64* %p to i64
+  ret i64 %0
+}

llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i686-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i1 @ptrtoint_s1_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i1
+    ret i1 %0
+  }
+
+  define i8 @ptrtoint_s8_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i8
+    ret i8 %0
+  }
+
+  define i16 @ptrtoint_s16_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i16
+    ret i16 %0
+  }
+
+  define i32 @ptrtoint_s32_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i32
+    ret i32 %0
+  }
+
+...
+---
+name:            ptrtoint_s1_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s1) = G_PTRTOINT [[LOAD]](p0)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[PTRTOINT]](s1)
+    ; CHECK: $al = COPY [[ANYEXT]](s8)
+    ; CHECK: RET 0, implicit $al
+    %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:_(s1) = G_PTRTOINT %0(p0)
+    %3:_(s8) = G_ANYEXT %2(s1)
+    $al = COPY %3(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s8_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s8_p0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s8) = G_PTRTOINT [[LOAD]](p0)
+    ; CHECK: $al = COPY [[PTRTOINT]](s8)
+    ; CHECK: RET 0, implicit $al
+    %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:_(s8) = G_PTRTOINT %0(p0)
+    $al = COPY %2(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s16_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s16_p0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s16) = G_PTRTOINT [[LOAD]](p0)
+    ; CHECK: $ax = COPY [[PTRTOINT]](s16)
+    ; CHECK: RET 0, implicit $ax
+    %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:_(s16) = G_PTRTOINT %0(p0)
+    $ax = COPY %2(s16)
+    RET 0, implicit $ax
+
+...
+---
+name:            ptrtoint_s32_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s32_p0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[LOAD]](p0)
+    ; CHECK: $eax = COPY [[PTRTOINT]](s32)
+    ; CHECK: RET 0, implicit $eax
+    %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:_(s32) = G_PTRTOINT %0(p0)
+    $eax = COPY %2(s32)
+    RET 0, implicit $eax
+
+...

llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i1 @ptrtoint_s1_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i1
+    ret i1 %0
+  }
+
+  define i8 @ptrtoint_s8_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i8
+    ret i8 %0
+  }
+
+  define i16 @ptrtoint_s16_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i16
+    ret i16 %0
+  }
+
+  define i32 @ptrtoint_s32_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i32
+    ret i32 %0
+  }
+
+...
+---
+name:            ptrtoint_s1_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
+    ; CHECK: $al = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $al
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(s1) = G_PTRTOINT %0(p0)
+    %3:gpr(s8) = G_ANYEXT %2(s1)
+    $al = COPY %3(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s8_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s8_p0
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
+    ; CHECK: $al = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $al
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(s8) = G_PTRTOINT %0(p0)
+    $al = COPY %2(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s16_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s16_p0
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[MOV32rm]].sub_16bit
+    ; CHECK: $ax = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $ax
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(s16) = G_PTRTOINT %0(p0)
+    $ax = COPY %2(s16)
+    RET 0, implicit $ax
+
+...
+---
+name:            ptrtoint_s32_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: ptrtoint_s32_p0
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: $eax = COPY [[MOV32rm]]
+    ; CHECK: RET 0, implicit $eax
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(s32) = G_PTRTOINT %0(p0)
+    $eax = COPY %2(s32)
+    RET 0, implicit $eax
+
+...

llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i1 @ptrtoint_s1_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i1
+    ret i1 %0
+  }
+
+  define i8 @ptrtoint_s8_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i8
+    ret i8 %0
+  }
+
+  define i16 @ptrtoint_s16_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i16
+    ret i16 %0
+  }
+
+  define i32 @ptrtoint_s32_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i32
+    ret i32 %0
+  }
+
+  define i64 @ptrtoint_s64_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i64
+    ret i64 %0
+  }
+
+...
+---
+name:            ptrtoint_s1_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s1) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[PTRTOINT]](s1)
+    ; CHECK: $al = COPY [[ANYEXT]](s8)
+    ; CHECK: RET 0, implicit $al
+    %0:_(p0) = COPY $rdi
+    %1:_(s1) = G_PTRTOINT %0(p0)
+    %2:_(s8) = G_ANYEXT %1(s1)
+    $al = COPY %2(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s8_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s8_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s8) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: $al = COPY [[PTRTOINT]](s8)
+    ; CHECK: RET 0, implicit $al
+    %0:_(p0) = COPY $rdi
+    %1:_(s8) = G_PTRTOINT %0(p0)
+    $al = COPY %1(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s16_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s16_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s16) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: $ax = COPY [[PTRTOINT]](s16)
+    ; CHECK: RET 0, implicit $ax
+    %0:_(p0) = COPY $rdi
+    %1:_(s16) = G_PTRTOINT %0(p0)
+    $ax = COPY %1(s16)
+    RET 0, implicit $ax
+
+...
+---
+name:            ptrtoint_s32_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s32_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: $eax = COPY [[PTRTOINT]](s32)
+    ; CHECK: RET 0, implicit $eax
+    %0:_(p0) = COPY $rdi
+    %1:_(s32) = G_PTRTOINT %0(p0)
+    $eax = COPY %1(s32)
+    RET 0, implicit $eax
+
+...
+---
+name:            ptrtoint_s64_p0
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s64_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: $rax = COPY [[PTRTOINT]](s64)
+    ; CHECK: RET 0, implicit $rax
+    %0:_(p0) = COPY $rdi
+    %1:_(s64) = G_PTRTOINT %0(p0)
+    $rax = COPY %1(s64)
+    RET 0, implicit $rax
+
+...

llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i1 @ptrtoint_s1_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i1
+    ret i1 %0
+  }
+
+  define i8 @ptrtoint_s8_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i8
+    ret i8 %0
+  }
+
+  define i16 @ptrtoint_s16_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i16
+    ret i16 %0
+  }
+
+  define i32 @ptrtoint_s32_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i32
+    ret i32 %0
+  }
+
+  define i64 @ptrtoint_s64_p0(i64* %p) {
+  entry:
+    %0 = ptrtoint i64* %p to i64
+    ret i64 %0
+  }
+
+...
+---
+name:            ptrtoint_s1_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; CHECK: $al = COPY [[COPY1]]
+    ; CHECK: RET 0, implicit $al
+    %0:gpr(p0) = COPY $rdi
+    %1:gpr(s1) = G_PTRTOINT %0(p0)
+    %2:gpr(s8) = G_ANYEXT %1(s1)
+    $al = COPY %2(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s8_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s8_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; CHECK: $al = COPY [[COPY1]]
+    ; CHECK: RET 0, implicit $al
+    %0:gpr(p0) = COPY $rdi
+    %1:gpr(s8) = G_PTRTOINT %0(p0)
+    $al = COPY %1(s8)
+    RET 0, implicit $al
+
+...
+---
+name:            ptrtoint_s16_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s16_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; CHECK: $ax = COPY [[COPY1]]
+    ; CHECK: RET 0, implicit $ax
+    %0:gpr(p0) = COPY $rdi
+    %1:gpr(s16) = G_PTRTOINT %0(p0)
+    $ax = COPY %1(s16)
+    RET 0, implicit $ax
+
+...
+---
+name:            ptrtoint_s32_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s32_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+    ; CHECK: $eax = COPY [[COPY1]]
+    ; CHECK: RET 0, implicit $eax
+    %0:gpr(p0) = COPY $rdi
+    %1:gpr(s32) = G_PTRTOINT %0(p0)
+    $eax = COPY %1(s32)
+    RET 0, implicit $eax
+
+...
+---
+name:            ptrtoint_s64_p0
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: ptrtoint_s64_p0
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK: $rax = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $rax
+    %0:gpr(p0) = COPY $rdi
+    %1:gpr(s64) = G_PTRTOINT %0(p0)
+    $rax = COPY %1(s64)
+    RET 0, implicit $rax
+
+...