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[mips] Spectre variant two mitigation for MIPSR2

Authored by sdardis on Feb 19 2018, 2:52 PM.



This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.

This option is accepted when targeting MIPS revision two or later.

The migitation strategy suggested by MIPS for these processors is to use
two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS ISA
in future, e.g. retpoline style solutions.

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Event Timeline

sdardis created this revision.Feb 19 2018, 2:52 PM
sdardis edited the summary of this revision. (Show Details)Feb 19 2018, 2:55 PM
This revision is now accepted and ready to land.Feb 20 2018, 4:44 AM
sdardis edited the summary of this revision. (Show Details)Feb 20 2018, 4:53 AM
sdardis edited the summary of this revision. (Show Details)Feb 20 2018, 4:02 PM
This revision was automatically updated to reflect the committed changes.