[DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), (not y))

[craig.topper]

Summary

If the and has an additional use we shouldn't invert it. That creates an additional instruction.

While there add a one use check to the transform above that looked similar.

[RKSimon]

LGTM - I'm curious whether it's be useful for those combines to support vectors at some point, X86 combineANDXORWithAllOnesIntoANDNP might match more cases then.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
     SDLoc DL(N0);
     V = DAG.getNode(ISD::XOR, DL, V.getValueType(), V,
                     DAG.getConstant(1, DL, V.getValueType()));
     AddToWorklist(V.getNode());
     return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
   }
 
   // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
-  if (isOneConstant(N1) && VT == MVT::i1 &&
+  if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
     if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
       AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
       return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
     }
   }
   // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
-  if (isAllOnesConstant(N1) &&
+  if (isAllOnesConstant(N1) && N0.hasOneUse() &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
     if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
       AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
       return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);

llvm/trunk/test/CodeGen/X86/tbm_patterns.ll

 ; CHECK-NEXT:    bextrq $15872, (%rdi), %rax # imm = 0x3E00
 ; CHECK-NEXT:    retq
 entry:
   %x1 = load i64, i64* %x
   %and = and i64 %x1, 4611686018427387903
   ret i64 %and
 }
 
-; This should select blcic
-; TODO: the xor is being combined with the mask and creating an or that's breaking this. Looks like a missing one use check.
+; Make sure the mask doesn't break our matching of blcic
 define  i64 @masked_blcic(i64) {
 ; CHECK-LABEL: masked_blcic:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl %di, %eax
-; CHECK-NEXT:    # kill: def $edi killed $edi killed $rdi def $rdi
-; CHECK-NEXT:    notl %edi
-; CHECK-NEXT:    orq $-65536, %rdi # imm = 0xFFFF0000
-; CHECK-NEXT:    incq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    blcicl %eax, %eax
 ; CHECK-NEXT:    retq
   %2 = and i64 %0, 65535
   %3 = xor i64 %2, -1
   %4 = add nuw nsw i64 %2, 1
   %5 = and i64 %4, %3
   ret i64 %5
 }