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Differential D42738

[mips] Define certain instructions in microMIPS32r3
ClosedPublic

Authored by smaksimovic on Jan 31 2018, 7:49 AM.

Details

Reviewers
zoran.jovanovic
sdardis
Commits
rGb3e7ed3b941b: [mips] Define certain instructions in microMIPS32r3
rL324584: [mips] Define certain instructions in microMIPS32r3
Summary

Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d

These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.

Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.

Diff Detail

Repository
rL LLVM

Event Timeline

smaksimovic created this revision.Jan 31 2018, 7:49 AM
Herald added a subscriber: arichardson. · View Herald TranscriptJan 31 2018, 7:49 AM
sdardis accepted this revision.Feb 7 2018, 4:01 AM

LGTM with two inline nits addressed.

test/CodeGen/Mips/llvm-ir/arith.ll
1 ↗(On Diff #132173)

This file should be called 'fp-arith.ll' or something similar. 'arith.ll' suggests integer arithmetic to me, which we have test files already for.

test/CodeGen/Mips/llvm-ir/cp1move.ll
1 ↗(On Diff #132173)

You can use the debug option "-mno-ldc1-sdc1" to disable the generation of ldc1 and sdc1. That along with simple bitcasts will generate mthc1 and mfhc1 instructions. Then this file can be called bitcast.ll

This is better than replying on inline asm as we want to test code generation from llvm ir.

This revision is now accepted and ready to land.Feb 7 2018, 4:01 AM
smaksimovic updated this revision to Diff 133206.Feb 7 2018, 6:03 AM

Addressed review comments.
Slightly modified expandBuildPairF64/expandExtractElementF64 to check when in micromips mode.

smaksimovic updated this revision to Diff 133208.Feb 7 2018, 6:10 AM

Indentation

Closed by commit rL324584: [mips] Define certain instructions in microMIPS32r3 (authored by smaksimovic). · Explain WhyFeb 8 2018, 1:27 AM
This revision was automatically updated to reflect the committed changes.
smaksimovic added a comment.Feb 8 2018, 1:35 AM

Had some changes from another patch sneak in this commit.
Reverted in r324585.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
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test/
CodeGen/
Mips/
llvm-ir/
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MC/
Disassembler/
Mips/
micromips32r3/
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mips32/
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mips32r2/
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mips32r3/
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mips32r5/
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Mips/
micromips/
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micromips32r6/
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mips1/
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mips2/
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mips32/
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mips32r2/
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mips32r3/
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mips32r5/
40 lines
36 lines

Diff 133381

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

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class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>; class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>; class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>; class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>; class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>; class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>; class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>; class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>; class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>;
class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>; class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>; class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>; class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>; class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>; class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>; class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>; class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>; class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>; class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>; class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>; class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>;
class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>; class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>; class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>; class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>; class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>; class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>; class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>; class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>; class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>; class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
/// Floating Point Instructions /// Floating Point Instructions
class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Descriptions // Instruction Descriptions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd, class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
II_MTC0>; II_MTC0>;
class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd, class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, HARDFLOAT; II_MTC1, bitconvert>, HARDFLOAT;
class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd, class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
II_MTC2>; II_MTC2>;
class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd, class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
II_MTHC0>; II_MTHC0>;
class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
GPR32Opnd, II_MTC1>,
HARDFLOAT, FGR_32;
class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd,
GPR32Opnd, II_MTC1>,
HARDFLOAT, FGR_64;
class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd, class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
II_MTC2>; II_MTC2>;
class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
RegisterOperand SrcRC, InstrItinClass Itin> { RegisterOperand SrcRC, InstrItinClass Itin> {
dag InOperandList = (ins SrcRC:$rs, uimm3:$sel); dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
dag OutOperandList = (outs DstRC:$rt); dag OutOperandList = (outs DstRC:$rt);
string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
Show All 27 Lines
class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd, class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
II_MFC0>; II_MFC0>;
class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd, class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, HARDFLOAT; II_MFC1, bitconvert>, HARDFLOAT;
class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd, class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
II_MFC2>; II_MFC2>;
class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd, class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
II_MFHC0>; II_MFHC0>;
class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
II_MFHC1>, HARDFLOAT, FGR_32;
class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
II_MFHC1>, HARDFLOAT, FGR_64;
class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd, class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
II_MFC2>; II_MFC2>;
class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
dag InOperandList = (ins mem_mm_16:$addr); dag InOperandList = (ins mem_mm_16:$addr);
dag OutOperandList = (outs FGR64Opnd:$ft); dag OutOperandList = (outs FGR64Opnd:$ft);
string AsmString = !strconcat("ldc1", "\t$ft, $addr"); string AsmString = !strconcat("ldc1", "\t$ft, $addr");
list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))]; list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesclass FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
dag InOperandList = (ins RC:$ft, RC:$fs); dag InOperandList = (ins RC:$ft, RC:$fs);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]; list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
bit isCommutable = isComm; bit isCommutable = isComm;
} }
class FADD_S_MMR6_DESC class FADD_S_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>; : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
class FADD_D_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
class FSUB_S_MMR6_DESC class FSUB_S_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>; : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
class FSUB_D_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
class FMUL_S_MMR6_DESC class FMUL_S_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>; : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
class FMUL_D_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
class FDIV_S_MMR6_DESC class FDIV_S_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>; : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
class FDIV_D_MMR6_DESC
: FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
II_MADDF_S>, HARDFLOAT; II_MADDF_S>, HARDFLOAT;
class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
II_MADDF_D>, HARDFLOAT; II_MADDF_D>, HARDFLOAT;
class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
II_MSUBF_S>, HARDFLOAT; II_MSUBF_S>, HARDFLOAT;
class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
II_MSUBF_D>, HARDFLOAT; II_MSUBF_D>, HARDFLOAT;
class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC, class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
RegisterOperand SrcRC, InstrItinClass Itin, RegisterOperand SrcRC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> SDPatternOperator OpNode = null_frag>
: HARDFLOAT, NeverHasSideEffects { : HARDFLOAT, NeverHasSideEffects {
dag OutOperandList = (outs DstRC:$ft); dag OutOperandList = (outs DstRC:$ft);
dag InOperandList = (ins SrcRC:$fs); dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
Format Form = FrmFR; Format Form = FrmFR;
} }
class FMOV_S_MMR6_DESC class FMOV_S_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>; : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
class FMOV_D_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
class FNEG_S_MMR6_DESC class FNEG_S_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>; : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
class FNEG_D_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>, class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
HARDFLOAT; HARDFLOAT;
class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>, class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
HARDFLOAT; HARDFLOAT;
class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>, class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
HARDFLOAT; HARDFLOAT;
class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>, class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
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} }
class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd, class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
II_CVT>; II_CVT>;
class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd, class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
II_CVT>; II_CVT>;
class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd, class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
II_CVT>; II_CVT>;
class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
II_CVT>;
class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
II_CVT>;
class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
II_CVT>;
class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd, class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
II_CVT>, FGR_64; II_CVT>, FGR_64;
class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
II_CVT>;
class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd, class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
II_CVT>; II_CVT>;
class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd, class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
II_CVT>, FGR_64; II_CVT>, FGR_64;
multiclass CMP_CC_MMR6<bits<6> format, string Typestr, multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
RegisterOperand FGROpnd, InstrItinClass Itin> { RegisterOperand FGROpnd, InstrItinClass Itin> {
def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM< def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
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def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6; def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6; def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6; def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6; def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6; def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6; def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6; def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6; def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderNamespace = "MicroMipsFP64" in {
def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
}
def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6; def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6; def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6; def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6; def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6; def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
let DecoderNamespace = "MicroMipsFP64" in {
def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
}
def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6; def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6; def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6; def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6; def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6; def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6; def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6; def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6; def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
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def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6; def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
} }
/// Floating Point Instructions /// Floating Point Instructions
def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC, def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC, def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC, def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC, def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC, def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC, def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC, def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC, def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC, def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC, def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6; def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6; def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC, def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC, def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC, def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC, def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC, def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC, def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC, def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
ISA_MICROMIPS32R6;
def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC, def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC, def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC, def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>; defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>; defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC, def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
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llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// //==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file describes the microMIPS FPU instruction set. // This file describes the microMIPS FPU instruction set.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCodeGenOnly = 1 in { multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode = null_frag> {
def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
FGR_32 {
string DecoderNamespace = "MicroMips";
}
// FIXME: This needs to be part of the instruction mapping tables.
def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
string DecoderNamespace = "MicroMipsFP64";
}
}
def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS;
def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS; ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS;
def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS; ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS;
def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS;
def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS;
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS;
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,
ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS;
def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS;
let isCodeGenOnly = 1 in {
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;
// FIXME: These instruction definitions are incorrect. They should be 64-bit // FIXME: These instruction definitions are incorrect. They should be 64-bit
// FPU only. // FPU only.
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
Show All 30 Lines
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd,
II_ROUND>, ROUND_W_FM_MM<0, 0xec>, II_ROUND>, ROUND_W_FM_MM<0, 0xec>,
ISA_MICROMIPS; ISA_MICROMIPS;
def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32;
def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;
def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd,
II_ROUND>, ROUND_W_FM_MM<1, 0xec>, II_ROUND>, ROUND_W_FM_MM<1, 0xec>,
ISA_MICROMIPS, FGR_32; ISA_MICROMIPS, FGR_32;
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
} }
let DecoderNamespace = "MicroMips" in {
def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMipsFP64" in {
def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64;
}
multiclass ABSS_MMM<string opstr, InstrItinClass Itin, multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> { SDPatternOperator OpNode = null_frag> {
def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_32 { ISA_MICROMIPS, FGR_32 {
string DecoderNamespace = "MicroMips"; string DecoderNamespace = "MicroMips";
} }
// FIXME: This needs to be part of the instruction mapping tables. // FIXME: This needs to be part of the instruction mapping tables.
def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_64 { ISA_MICROMIPS, FGR_64 {
string DecoderNamespace = "MicroMipsFP64"; string DecoderNamespace = "MicroMipsFP64";
} }
} }
defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>; defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
} }
let isCodeGenOnly = 1 in {
def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
let DecoderNamespace = "MicroMips" in {
def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32;
def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMipsFP64" in {
def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64;
def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64;
def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64;
}
let DecoderNamespace = "MicroMips" in {
def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;
}
def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32;
let isCodeGenOnly = 1 in {
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesdef TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>, FGR32Opnd, II_TRUNC>,
ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS { fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS {
string DecoderNamespace = "MicroMips"; string DecoderNamespace = "MicroMips";
} }
def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
let DecoderNamespace = "MicroMips" in {
def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMipsFP64" in {
def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64;
def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64;
}
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
MFC1_FM_MM<0x40>, ISA_MICROMIPS; MFC1_FM_MM<0x40>, ISA_MICROMIPS;
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
MFC1_FM_MM<0x60>, ISA_MICROMIPS; MFC1_FM_MM<0x60>, ISA_MICROMIPS;
def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>, II_RECIP_S>,
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
// Patterns for loads/stores with a reg+imm operand. // Patterns for loads/stores with a reg+imm operand.
let AddedComplexity = 40 in { let AddedComplexity = 40 in {
def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32; def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32;
def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32; def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32;
def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS;
def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS;
} }
def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
(CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64;
def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
(CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64;
def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
(CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32;
def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
(CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32;

llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 724 Lines • ▼ Show 20 Linesclass ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
let Inst{31-26} = 0x15; let Inst{31-26} = 0x15;
let Inst{25-21} = ft; let Inst{25-21} = ft;
let Inst{20-16} = fs; let Inst{20-16} = fs;
let Inst{15-11} = fd; let Inst{15-11} = fd;
let Inst{10} = 0; let Inst{10} = 0;
let Inst{9-8} = fmt; let Inst{9-8} = fmt;
let Inst{7-0} = funct; let Inst{7-0} = funct;
list<dag> Pattern = [];
} }
class LWXC1_FM_MM<bits<9> funct> : MMArch { class LWXC1_FM_MM<bits<9> funct> : MMArch {
bits<5> fd; bits<5> fd;
bits<5> base; bits<5> base;
bits<5> index; bits<5> index;
bits<32> Inst; bits<32> Inst;
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsISelLowering.h

Show First 20 Lines • Show All 364 Lines • ▼ Show 20 Lines bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// the first 256 for software use (e.g. OpenCL) and treat casts // the first 256 for software use (e.g. OpenCL) and treat casts
// between them as noops. // between them as noops.
return SrcAS < 256 && DestAS < 256; return SrcAS < 256 && DestAS < 256;
} }
bool isJumpTableRelative() const override { bool isJumpTableRelative() const override {
return getTargetMachine().isPositionIndependent(); return getTargetMachine().isPositionIndependent();
} }
void finalizeLowering(MachineFunction &MF) const override;
protected: protected:
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
// This method creates the following nodes, which are necessary for // This method creates the following nodes, which are necessary for
// computing a local symbol's address: // computing a local symbol's address:
// //
// (add (load (wrapper $gp, %got(sym)), %lo(sym)) // (add (load (wrapper $gp, %got(sym)), %lo(sym))
template <class NodeTy> template <class NodeTy>
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llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Linesstatic bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
if (!isShiftedMask_64(I)) if (!isShiftedMask_64(I))
return false; return false;
Size = countPopulation(I); Size = countPopulation(I);
Pos = countTrailingZeros(I); Pos = countTrailingZeros(I);
return true; return true;
} }
void MipsTargetLowering::finalizeLowering(MachineFunction &MF) const {
MF.getFrameInfo().computeMaxCallFrameSize(MF);
TargetLoweringBase::finalizeLowering(MF);
}
// The MIPS MSA ABI passes vector arguments in the integer register set. // The MIPS MSA ABI passes vector arguments in the integer register set.
// The number of integer registers used is dependant on the ABI used. // The number of integer registers used is dependant on the ABI used.
MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
if (VT.isVector() && Subtarget.hasMSA()) if (VT.isVector() && Subtarget.hasMSA())
return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
return MipsTargetLowering::getRegisterType(VT); return MipsTargetLowering::getRegisterType(VT);
} }
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llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xf, 16>, ISA_MIPS2; ABSS_FM<0xf, 16>, ISA_MIPS2;
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x24, 16>; ABSS_FM<0x24, 16>;
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in {
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
}
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
let BaseOpcode = "RECIP_D32"; let BaseOpcode = "RECIP_D32";
} }
Show All 37 Linesdef CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x20, 20>; ABSS_FM<0x20, 20>;
let AdditionalPredicates = [NotInMicroMips] in{ let AdditionalPredicates = [NotInMicroMips] in{
def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
} }
let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_32; ABSS_FM<0x20, 17>, FGR_32;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_32;
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, FGR_32; ABSS_FM<0x21, 16>, FGR_32;
}
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_32;
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_64;
let AdditionalPredicates = [NotInMicroMips] in{ let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 21>, FGR_64; ABSS_FM<0x20, 21>, FGR_64;
} def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_64;
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_64; ABSS_FM<0x21, 20>, FGR_64;
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, FGR_64; ABSS_FM<0x21, 16>, FGR_64;
}
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x21, 21>, FGR_64; ABSS_FM<0x21, 21>, FGR_64;
} }
let isPseudo = 1, isCodeGenOnly = 1 in { let isPseudo = 1, isCodeGenOnly = 1 in {
def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
ABSS_FM<0x5, 16>; ABSS_FM<0x5, 16>;
defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
} }
def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
ABSS_FM<0x7, 16>; ABSS_FM<0x7, 16>;
let AdditionalPredicates = [NotInMicroMips] in {
defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
}
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
} }
// The odd-numbered registers are only referenced when doing loads, // The odd-numbered registers are only referenced when doing loads,
Show All 35 Lines def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
bitconvert>, MFC1_FM<5>, ISA_MIPS3; bitconvert>, MFC1_FM<5>, ISA_MIPS3;
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
bitconvert>, MFC1_FM<1>, ISA_MIPS3; bitconvert>, MFC1_FM<1>, ISA_MIPS3;
}
def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABSS_FM<0x6, 16>; ABSS_FM<0x6, 16>;
def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
ABSS_FM<0x6, 17>, FGR_32; ABSS_FM<0x6, 17>, FGR_32;
def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
ABSS_FM<0x6, 17>, FGR_64 { ABSS_FM<0x6, 17>, FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
}
/// Floating Point Memory Instructions /// Floating Point Memory Instructions
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
LW_FM<0x31>; LW_FM<0x31>;
def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
LW_FM<0x39>; LW_FM<0x39>;
} }
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let DecoderNamespace="MipsFP64" in { let DecoderNamespace="MipsFP64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
} }
/// Floating-point Aritmetic /// Floating-point Aritmetic
let AdditionalPredicates = [NotInMicroMips] in {
def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
ADDS_FM<0x00, 16>; ADDS_FM<0x00, 16>;
defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
ADDS_FM<0x03, 16>; ADDS_FM<0x03, 16>;
defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
ADDS_FM<0x02, 16>; ADDS_FM<0x02, 16>;
defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM<0x01, 16>; ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
}
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
(MTC1_D64 GPR32Opnd:$src)>, FGR_64; (MTC1_D64 GPR32Opnd:$src)>, FGR_64;
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
(PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
(TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
(CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
(CVT_D32_S FGR32Opnd:$src)>, FGR_32; (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
}
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
(PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
(EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
(PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
(TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
(TRUNC_L_S FGR32Opnd:$src)>, FGR_64; (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
(TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(f32 (fpround FGR64Opnd:$src)), def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
(CVT_S_D64 FGR64Opnd:$src)>, FGR_64; (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
(CVT_D64_S FGR32Opnd:$src)>, FGR_64; (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
}
// To generate NMADD and NMSUB instructions when fneg node is present // To generate NMADD and NMSUB instructions when fneg node is present
multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> {
def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
(Nmadd RC:$fr, RC:$fs, RC:$ft)>; (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
(Nmsub RC:$fr, RC:$fs, RC:$ft)>; (Nmsub RC:$fr, RC:$fs, RC:$ft)>;
} }
Show All 20 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 LinesMipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const { MachineFunction &MF) const {
switch (RC->getID()) { switch (RC->getID()) {
default: default:
return 0; return 0;
case Mips::GPR32RegClassID: case Mips::GPR32RegClassID:
case Mips::GPR64RegClassID: case Mips::GPR64RegClassID:
case Mips::DSPRRegClassID: { case Mips::DSPRRegClassID: {
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
return 28 - TFI->hasFP(MF); bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
? TFI->hasFP(MF) : true;
return 28 - HasFP;
} }
case Mips::FGR32RegClassID: case Mips::FGR32RegClassID:
return 32; return 32;
case Mips::AFGR64RegClassID: case Mips::AFGR64RegClassID:
return 16; return 16;
case Mips::FGR64RegClassID: case Mips::FGR64RegClassID:
return 32; return 32;
} }
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Linesprivate:
/// CVT_D32_W D2, F4 /// CVT_D32_W D2, F4
/// ///
/// We do this expansion post-RA to avoid inserting a floating point copy /// We do this expansion post-RA to avoid inserting a floating point copy
/// instruction between MTC1 and CVT_D32_W. /// instruction between MTC1 and CVT_D32_W.
void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
void expandExtractElementF64(MachineBasicBlock &MBB, void expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, bool FP64) const; MachineBasicBlock::iterator I, bool isMicroMips,
bool FP64) const;
void expandBuildPairF64(MachineBasicBlock &MBB, void expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, bool FP64) const; MachineBasicBlock::iterator I, bool isMicroMips,
bool FP64) const;
void expandEhReturn(MachineBasicBlock &MBB, void expandEhReturn(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const;
}; };
} }
#endif #endif

llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp

Show First 20 Lines • Show All 373 Lines • ▼ Show 20 Lines case Mips::PseudoMTLOHI64:
break; break;
case Mips::PseudoMTLOHI_DSP: case Mips::PseudoMTLOHI_DSP:
expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
break; break;
case Mips::PseudoCVT_S_W: case Mips::PseudoCVT_S_W:
expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
break; break;
case Mips::PseudoCVT_D32_W: case Mips::PseudoCVT_D32_W:
expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
break; break;
case Mips::PseudoCVT_S_L: case Mips::PseudoCVT_S_L:
expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
break; break;
case Mips::PseudoCVT_D64_W: case Mips::PseudoCVT_D64_W:
expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
break; break;
case Mips::PseudoCVT_D64_L: case Mips::PseudoCVT_D64_L:
expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
break; break;
case Mips::BuildPairF64: case Mips::BuildPairF64:
expandBuildPairF64(MBB, MI, false); expandBuildPairF64(MBB, MI, isMicroMips, false);
break; break;
case Mips::BuildPairF64_64: case Mips::BuildPairF64_64:
expandBuildPairF64(MBB, MI, true); expandBuildPairF64(MBB, MI, isMicroMips, true);
break; break;
case Mips::ExtractElementF64: case Mips::ExtractElementF64:
expandExtractElementF64(MBB, MI, false); expandExtractElementF64(MBB, MI, isMicroMips, false);
break; break;
case Mips::ExtractElementF64_64: case Mips::ExtractElementF64_64:
expandExtractElementF64(MBB, MI, true); expandExtractElementF64(MBB, MI, isMicroMips, true);
break; break;
case Mips::MIPSeh_return32: case Mips::MIPSeh_return32:
case Mips::MIPSeh_return64: case Mips::MIPSeh_return64:
expandEhReturn(MBB, MI); expandEhReturn(MBB, MI);
break; break;
} }
MBB.erase(MI); MBB.erase(MI);
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines if (SrcIsLarger)
DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
} }
void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
bool isMicroMips,
bool FP64) const { bool FP64) const {
unsigned DstReg = I->getOperand(0).getReg(); unsigned DstReg = I->getOperand(0).getReg();
unsigned SrcReg = I->getOperand(1).getReg(); unsigned SrcReg = I->getOperand(1).getReg();
unsigned N = I->getOperand(2).getImm(); unsigned N = I->getOperand(2).getImm();
DebugLoc dl = I->getDebugLoc(); DebugLoc dl = I->getDebugLoc();
assert(N < 2 && "Invalid immediate"); assert(N < 2 && "Invalid immediate");
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
Show All 15 Lines if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
// requires a major overhaul of the FPU implementation which can't // requires a major overhaul of the FPU implementation which can't
// be done right now due to time constraints. // be done right now due to time constraints.
// MFHC1 is one of two instructions that are affected since they are // MFHC1 is one of two instructions that are affected since they are
// the only instructions that don't read the lower 32-bits. // the only instructions that don't read the lower 32-bits.
// We therefore pretend that it reads the bottom 32-bits to // We therefore pretend that it reads the bottom 32-bits to
// artificially create a dependency and prevent the scheduler // artificially create a dependency and prevent the scheduler
// changing the behaviour of the code. // changing the behaviour of the code.
BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) BuildMI(MBB, I, dl,
get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
: (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
DstReg)
.addReg(SrcReg); .addReg(SrcReg);
} else } else
BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
} }
void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
bool FP64) const { bool isMicroMips, bool FP64) const {
unsigned DstReg = I->getOperand(0).getReg(); unsigned DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc(); DebugLoc dl = I->getDebugLoc();
const TargetRegisterInfo &TRI = getRegisterInfo(); const TargetRegisterInfo &TRI = getRegisterInfo();
// When mthc1 is available, use: // When mthc1 is available, use:
// mtc1 Lo, $fp // mtc1 Lo, $fp
Show All 28 Lines if (Subtarget.hasMTHC1()) {
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
// requires a major overhaul of the FPU implementation which can't // requires a major overhaul of the FPU implementation which can't
// be done right now due to time constraints. // be done right now due to time constraints.
// MTHC1 is one of two instructions that are affected since they are // MTHC1 is one of two instructions that are affected since they are
// the only instructions that don't read the lower 32-bits. // the only instructions that don't read the lower 32-bits.
// We therefore pretend that it reads the bottom 32-bits to // We therefore pretend that it reads the bottom 32-bits to
// artificially create a dependency and prevent the scheduler // artificially create a dependency and prevent the scheduler
// changing the behaviour of the code. // changing the behaviour of the code.
BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) BuildMI(MBB, I, dl,
get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
: (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
DstReg)
.addReg(DstReg) .addReg(DstReg)
.addReg(HiReg); .addReg(HiReg);
} else if (Subtarget.isABI_FPXX()) } else if (Subtarget.isABI_FPXX())
llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
else else
BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
.addReg(HiReg); .addReg(HiReg);
} }
Show All 33 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/arith-fp.ll

; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define double @add_d(double %a, double %b) {
; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32
; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64
; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM
; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM
; MMR6: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM
%1 = fadd double %a, %b
ret double %1
}
define double @sub_d(double %a, double %b) {
; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32
; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64
; MM: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32_MM
; MMFP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM
; MMR6: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM
%1 = fsub double %a, %b
ret double %1
}
define double @mul_d(double %a, double %b) {
; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32
; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64
; MM: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32_MM
; MMFP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM
; MMR6: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM
%1 = fmul double %a, %b
ret double %1
}
define double @div_d(double %a, double %b) {
; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32
; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64
; MM: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32_MM
; MMFP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM
; MMR6: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM
%1 = fdiv double %a, %b
ret double %1
}
define double @fneg(double %a) {
; MIPS32: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32
; MIPS32FP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64
; MM: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32_MM
; MMFP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM
; MMR6: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM
%1 = fsub double -0.000000e+00, %a
ret double %1
}

llvm/trunk/test/CodeGen/Mips/llvm-ir/bitcast.ll

; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst \
; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32R2
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \
; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \
; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \
; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \
; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMR6
define double @mthc1(i64 %a) {
; MIPS32R2: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32
; MIPS32FP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64
; MM: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32_MM
; MMFP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM
; MMR6: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM
%1 = bitcast i64 %a to double
ret double %1
}
define i64 @mfhc1(double %a) {
; MIPS32R2: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32
; MIPS32FP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64
; MM: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32_MM
; MMFP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM
; MMR6: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM
%1 = bitcast double %a to i64
ret i64 %1
}

llvm/trunk/test/CodeGen/Mips/llvm-ir/cvt.ll

; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
; TODO: Test for cvt_w_d is missing, could not generate instruction
define double @cvt_d_s(float %a) {
; MIPS32: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S
; MIPS32FP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S
; MM: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S_MM
; MMFP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM
; MMR6: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM
%1 = fpext float %a to double
ret double %1
}
define double @cvt_d_w(i32 %a) {
; MIPS32: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W
; MIPS32FP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W
; MM: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W_MM
; MMFP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM
; MMR6: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM
%1 = sitofp i32 %a to double
ret double %1
}
define float @cvt_s_d(double %a) {
; MIPS32: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32
; MIPS32FP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64
; MM: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32_MM
; MMFP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM
; MMR6: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM
%1 = fptrunc double %a to float
ret float %1
}

llvm/trunk/test/CodeGen/Mips/maxcallframesize.ll

; RUN: llc < %s -mtriple=mips-unknown-linux -stop-before=prologepilog | FileCheck %s
; Test that maxCallFrameSize is being computed early on.
@glob = external global i32*
declare void @bar(i32*, [20000 x i8]* byval)
define void @foo([20000 x i8]* %addr) {
%tmp = alloca [4 x i32], align 32
%tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
call void @bar(i32* %tmp0, [20000 x i8]* byval %addr)
ret void
}
; CHECK: adjustsStack: true
; CHECK: maxCallFrameSize: 20008

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6 0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30 0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28 0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8 0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12 0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12
0x80 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f0
0x80 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f0
0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4
0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4
0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \ # RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s # RUN: | FileCheck %s
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12 0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12
0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12
0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12
0x80 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f0
0x80 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f0
0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4
0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4
0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \ # RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s # RUN: | FileCheck %s
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12 0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12
0x54 0x80 0x38 0x3b # CHECK: mthc1 $4, $f0
0x54 0x80 0x30 0x3b # CHECK: mfhc1 $4, $f0
0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4
0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4
0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2
0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Lines
0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6 0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30 0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28 0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8 0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12 0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12
0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12
0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12
0x54 0x80 0x38 0x3b # CHECK: mthc1 $4, $f0
0x54 0x80 0x30 0x3b # CHECK: mfhc1 $4, $f0
0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4
0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4
0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2
0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12
0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12
0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12
0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12
0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12
0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12
0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt

# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12
0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12
0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12
0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4
0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt

# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \ # RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12
0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Mips/micromips/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \ # RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \
# RUN: | FileCheck %s # RUN: | FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b] abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64_MM
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64_MM

llvm/trunk/test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesabs.s $f0, $f2 # CHECK: abs.s $f0, $f2 # encoding: [0x54,0x02,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b] abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32_MM
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b] sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM
add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10] add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10]
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D32_MM
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67] addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67]
addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67] addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67]
addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x50] addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x50]
sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90] sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90]
subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0] subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0]
sub $6, $zero, $7 # CHECK: neg $6, $7 # encoding: [0x00,0xe0,0x31,0x90] sub $6, $zero, $7 # CHECK: neg $6, $7 # encoding: [0x00,0xe0,0x31,0x90]
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D32_MM
subu $6, $zero, $7 # CHECK: subu $6, $zero, $7 # encoding: [0x00,0xe0,0x31,0xd0] subu $6, $zero, $7 # CHECK: subu $6, $zero, $7 # encoding: [0x00,0xe0,0x31,0xd0]
addu $7, $8, $zero # CHECK: addu $7, $8, $zero # encoding: [0x00,0x08,0x39,0x50] addu $7, $8, $zero # CHECK: addu $7, $8, $zero # encoding: [0x00,0x08,0x39,0x50]
slt $3, $3, $5 # CHECK: slt $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x50] slt $3, $3, $5 # CHECK: slt $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x50]
slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67] slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67] slti $3, $3, 103 # CHECK: slti $3, $3, 103 # encoding: [0x90,0x63,0x00,0x67]
sltiu $3, $3, 103 # CHECK: sltiu $3, $3, 103 # encoding: [0xb0,0x63,0x00,0x67] sltiu $3, $3, 103 # CHECK: sltiu $3, $3, 103 # encoding: [0xb0,0x63,0x00,0x67]
sltu $3, $3, $5 # CHECK: sltu $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x90] sltu $3, $3, $5 # CHECK: sltu $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x90]
lui $9, 17767 # CHECK: lui $9, 17767 # encoding: [0x41,0xa9,0x45,0x67] lui $9, 17767 # CHECK: lui $9, 17767 # encoding: [0x41,0xa9,0x45,0x67]
and $9, $6, $7 # CHECK: and $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x50] and $9, $6, $7 # CHECK: and $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x50]
andi $9, $6, 17767 # CHECK: andi $9, $6, 17767 # encoding: [0xd1,0x26,0x45,0x67] andi $9, $6, 17767 # CHECK: andi $9, $6, 17767 # encoding: [0xd1,0x26,0x45,0x67]
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
ori $9, $6, 17767 # CHECK: ori $9, $6, 17767 # encoding: [0x51,0x26,0x45,0x67] ori $9, $6, 17767 # CHECK: ori $9, $6, 17767 # encoding: [0x51,0x26,0x45,0x67]
xor $3, $3, $5 # CHECK: xor $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x10] xor $3, $3, $5 # CHECK: xor $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x10]
xori $9, $6, 17767 # CHECK: xori $9, $6, 17767 # encoding: [0x71,0x26,0x45,0x67] xori $9, $6, 17767 # CHECK: xori $9, $6, 17767 # encoding: [0x71,0x26,0x45,0x67]
nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0xd0] nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0xd0]
not $7, $8 # CHECK: not $7, $8 # encoding: [0x00,0x08,0x3a,0xd0] not $7, $8 # CHECK: not $7, $8 # encoding: [0x00,0x08,0x3a,0xd0]
not $7 # CHECK: not $7, $7 # encoding: [0x00,0x07,0x3a,0xd0] not $7 # CHECK: not $7, $7 # encoding: [0x00,0x07,0x3a,0xd0]
mul $9, $6, $7 # CHECK: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10] mul $9, $6, $7 # CHECK: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10]
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D32_MM
mult $9, $7 # CHECK: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c] mult $9, $7 # CHECK: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c]
multu $9, $7 # CHECK: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c] multu $9, $7 # CHECK: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c]
div $zero, $9, $7 # CHECK: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c] div $zero, $9, $7 # CHECK: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c]
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32_MM
divu $zero, $9, $7 # CHECK: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c] divu $zero, $9, $7 # CHECK: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00] sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80] sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40] srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
lb $5, 8($4) # CHECK: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08] lb $5, 8($4) # CHECK: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08]
lbu $6, 8($4) # CHECK: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08] lbu $6, 8($4) # CHECK: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lw $6, 4($5) # CHECK: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04] lw $6, 4($5) # CHECK: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04]
lw $6, 123($sp) # CHECK: lw $6, 123($sp) # encoding: [0xfc,0xdd,0x00,0x7b] lw $6, 123($sp) # CHECK: lw $6, 123($sp) # encoding: [0xfc,0xdd,0x00,0x7b]
sb $5, 8($4) # CHECK: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08] sb $5, 8($4) # CHECK: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08]
sh $2, 8($4) # CHECK: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08] sh $2, 8($4) # CHECK: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
sw $5, 123($sp) # CHECK: sw $5, 123($sp) # encoding: [0xf8,0xbd,0x00,0x7b] sw $5, 123($sp) # CHECK: sw $5, 123($sp) # encoding: [0xf8,0xbd,0x00,0x7b]
lwu $2, 8($4) # CHECK: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08] lwu $2, 8($4) # CHECK: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
lwl $4, 16($5) # CHECK: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10] lwl $4, 16($5) # CHECK: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
lwr $4, 16($5) # CHECK: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10] lwr $4, 16($5) # CHECK: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10]
swl $4, 16($5) # CHECK: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10] swl $4, 16($5) # CHECK: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10]
swr $4, 16($5) # CHECK: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10] swr $4, 16($5) # CHECK: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10]
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D32_MM
movz $9, $6, $7 # CHECK: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58] movz $9, $6, $7 # CHECK: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58]
movn $9, $6, $7 # CHECK: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18] movn $9, $6, $7 # CHECK: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
movt $9, $6, $fcc0 # CHECK: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b] movt $9, $6, $fcc0 # CHECK: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
movf $9, $6, $fcc0 # CHECK: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b] movf $9, $6, $fcc0 # CHECK: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
# FIXME: MTHI should also have its 16 bit implementation selected in micromips # FIXME: MTHI should also have its 16 bit implementation selected in micromips
mthi $6 # CHECK: mthi $6 # encoding: [0x00,0x06,0x2d,0x7c] mthi $6 # CHECK: mthi $6 # encoding: [0x00,0x06,0x2d,0x7c]
mfhi $6 # CHECK: mfhi $6 # encoding: [0x46,0x06] mfhi $6 # CHECK: mfhi $6 # encoding: [0x46,0x06]
# FIXME: MTLO should also have its 16 bit implementation selected in micromips # FIXME: MTLO should also have its 16 bit implementation selected in micromips
mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c] mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c]
mflo $6 # CHECK: mflo $6 # encoding: [0x46,0x46] mflo $6 # CHECK: mflo $6 # encoding: [0x46,0x46]
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c] madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c] maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c]
msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c] msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c] msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c]
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c] clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c] clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c] seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c] seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c] seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c] seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c] wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c]
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec] ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x57,0x0c,0x84,0xfc] c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x57,0x0c,0x84,0xfc]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x57,0xc3,0xc0,0xfc] c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x57,0xc3,0xc0,0xfc]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x56,0x58,0xe5,0xfc] c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x56,0x58,0xe5,0xfc]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x57,0xd5,0xe1,0xfc] c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x57,0xd5,0xe1,0xfc]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x56,0x06,0xc5,0x7c] c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x56,0x06,0xc5,0x7c]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x55,0x58,0xe1,0x7c] c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x55,0x58,0xe1,0x7c]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x54,0x9e,0x20,0x7c] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x54,0x9e,0x20,0x7c]
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D32_MM
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04] bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08] bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa4,0x00,0x02] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa4,0x00,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6] bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c] sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c] sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c] sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c]
synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x00,0x00,0x40] synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x00,0x00,0x40]

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70] sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70] sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64_MM
mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0] mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0] mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64_MM
div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0] div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0] div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM
maddf.s $f3, $f4, $f5 # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8] maddf.s $f3, $f4, $f5 # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8]
maddf.d $f3, $f4, $f5 # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8] maddf.d $f3, $f4, $f5 # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8]
msubf.s $f3, $f4, $f5 # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8] msubf.s $f3, $f4, $f5 # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8]
msubf.d $f3, $f4, $f5 # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8] msubf.d $f3, $f4, $f5 # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8]
mov.s $f6, $f7 # CHECK: mov.s $f6, $f7 # encoding: [0x54,0xc7,0x00,0x7b] mov.s $f6, $f7 # CHECK: mov.s $f6, $f7 # encoding: [0x54,0xc7,0x00,0x7b]
mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b] mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM
neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b] neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b]
neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b] neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64_MM
max.s $f5, $f4, $f3 # CHECK: max.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x0b] max.s $f5, $f4, $f3 # CHECK: max.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x0b]
max.d $f5, $f4, $f3 # CHECK: max.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x0b] max.d $f5, $f4, $f3 # CHECK: max.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x0b]
maxa.s $f5, $f4, $f3 # CHECK: maxa.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x2b] maxa.s $f5, $f4, $f3 # CHECK: maxa.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x2b]
maxa.d $f5, $f4, $f3 # CHECK: maxa.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x2b] maxa.d $f5, $f4, $f3 # CHECK: maxa.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x2b]
min.s $f5, $f4, $f3 # CHECK: min.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x03] min.s $f5, $f4, $f3 # CHECK: min.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x03]
min.d $f5, $f4, $f3 # CHECK: min.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x03] min.d $f5, $f4, $f3 # CHECK: min.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x03]
mina.s $f5, $f4, $f3 # CHECK: mina.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x23] mina.s $f5, $f4, $f3 # CHECK: mina.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x23]
mina.d $f5, $f4, $f3 # CHECK: mina.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x23] mina.d $f5, $f4, $f3 # CHECK: mina.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x23]
Show All 28 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
cmp.sle.s $f2, $f3, $f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x85] cmp.sle.s $f2, $f3, $f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x85]
cmp.sle.d $f2, $f3, $f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x95] cmp.sle.d $f2, $f3, $f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x95]
cmp.sule.s $f2, $f3, $f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xc5] cmp.sule.s $f2, $f3, $f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xc5]
cmp.sule.d $f2, $f3, $f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xd5] cmp.sule.d $f2, $f3, $f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xd5]
cvt.l.s $f3, $f4 # CHECK: cvt.l.s $f3, $f4 # encoding: [0x54,0x64,0x01,0x3b] cvt.l.s $f3, $f4 # CHECK: cvt.l.s $f3, $f4 # encoding: [0x54,0x64,0x01,0x3b]
cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b] cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b]
cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b] cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b]
cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b] cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM
cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b] cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM
cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b] cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM
cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b] cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b]
cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b] cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM
cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b] cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b] cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b] abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM
floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b] floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b]
floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b] floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b]
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM
mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc] mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc]
mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc] mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc]
mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b] mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b]
mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c] mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c]
mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4] mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4]
mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4]
mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM
mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c]
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips1/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips1 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips1 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
c.ngl.d $f29,$f29 c.ngl.d $f29,$f29
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.s.d $f26,$f8 cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
Show All 9 Linesa:
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
sb $s6,-19857($14) sb $s6,-19857($14)
Show All 21 Linesa:
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips2/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips2 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
Show All 19 Linesa:
c.ngl.d $f29,$f29 c.ngl.d $f29,$f29
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.s.d $f26,$f8 cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
Show All 17 Linesa:
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
round.w.d $f6,$f4 round.w.d $f6,$f4
Show All 33 Linesa:
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesa:
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.s.d $f26,$f8 cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
deret deret
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
Show All 21 Linesa:
madd $zero,$9 madd $zero,$9
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
movf $gp,$8,$fcc7 movf $gp,$8,$fcc7
movf.d $f6,$f11,$fcc5 movf.d $f6,$f11,$fcc5
movf.s $f23,$f5,$fcc6 movf.s $f23,$f5,$fcc6
movn $v1,$s1,$s0 movn $v1,$s1,$s0
movn.d $f27,$f21,$k0 movn.d $f27,$f21,$k0
movn.s $f12,$f0,$s7 movn.s $f12,$f0,$s7
movt $zero,$s4,$fcc5 movt $zero,$s4,$fcc5
movt.d $f0,$f2,$fcc0 movt.d $f0,$f2,$fcc0
movt.s $f30,$f2,$fcc1 movt.s $f30,$f2,$fcc1
movz $a1,$s6,$9 movz $a1,$s6,$9
movz.d $f12,$f29,$9 movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1 movz.s $f25,$f7,$v1
msub $s7,$k1 msub $s7,$k1
msubu $15,$a1 msubu $15,$a1
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul $s0,$s4,$at mul $s0,$s4,$at
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
Show All 35 Linesa:
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r2/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64

llvm/trunk/test/MC/Mips/mips32r2/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
deret deret
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
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madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
madd.d $f18,$f19,$f26,$f20 madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhc1 $s8,$f24 mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #1559 MFHC1_D32
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
movf $gp,$8,$fcc7 movf $gp,$8,$fcc7
movf.d $f6,$f11,$fcc5 movf.d $f6,$f11,$fcc5
movf.s $f23,$f5,$fcc6 movf.s $f23,$f5,$fcc6
movn $v1,$s1,$s0 movn $v1,$s1,$s0
movn.d $f27,$f21,$k0 movn.d $f27,$f21,$k0
movn.s $f12,$f0,$s7 movn.s $f12,$f0,$s7
movt $zero,$s4,$fcc5 movt $zero,$s4,$fcc5
movt.d $f0,$f2,$fcc0 movt.d $f0,$f2,$fcc0
movt.s $f30,$f2,$fcc1 movt.s $f30,$f2,$fcc1
movz $a1,$s6,$9 movz $a1,$s6,$9
movz.d $f12,$f29,$9 movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1 movz.s $f25,$f7,$v1
msub $s7,$k1 msub $s7,$k1
msub.d $f10,$f1,$f31,$f18 msub.d $f10,$f1,$f31,$f18
msub.s $f12,$f19,$f10,$f16 msub.s $f12,$f19,$f10,$f16
msubu $15,$a1 msubu $15,$a1
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthc1 $zero,$f16 mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #1712 MTHC1_D32
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul $s0,$s4,$at mul $s0,$s4,$at
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nmadd.d $f18,$f9,$f14,$f19 nmadd.d $f18,$f9,$f14,$f19
nmadd.s $f0,$f5,$f25,$f12 nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30 nmsub.d $f30,$f8,$f16,$f30
nmsub.s $f1,$f24,$f19,$f4 nmsub.s $f1,$f24,$f19,$f4
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
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srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r3/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64

llvm/trunk/test/MC/Mips/mips32r3/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r3 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r3 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
deret deret
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
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madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
madd.d $f18,$f19,$f26,$f20 madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhc1 $s8,$f24 mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #1559 MFHC1_D32
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
movf $gp,$8,$fcc7 movf $gp,$8,$fcc7
movf.d $f6,$f11,$fcc5 movf.d $f6,$f11,$fcc5
movf.s $f23,$f5,$fcc6 movf.s $f23,$f5,$fcc6
movn $v1,$s1,$s0 movn $v1,$s1,$s0
movn.d $f27,$f21,$k0 movn.d $f27,$f21,$k0
movn.s $f12,$f0,$s7 movn.s $f12,$f0,$s7
movt $zero,$s4,$fcc5 movt $zero,$s4,$fcc5
movt.d $f0,$f2,$fcc0 movt.d $f0,$f2,$fcc0
movt.s $f30,$f2,$fcc1 movt.s $f30,$f2,$fcc1
movz $a1,$s6,$9 movz $a1,$s6,$9
movz.d $f12,$f29,$9 movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1 movz.s $f25,$f7,$v1
msub $s7,$k1 msub $s7,$k1
msub.d $f10,$f1,$f31,$f18 msub.d $f10,$f1,$f31,$f18
msub.s $f12,$f19,$f10,$f16 msub.s $f12,$f19,$f10,$f16
msubu $15,$a1 msubu $15,$a1
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthc1 $zero,$f16 mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #1712 MTHC1_D32
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul $s0,$s4,$at mul $s0,$s4,$at
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nmadd.d $f18,$f9,$f14,$f19 nmadd.d $f18,$f9,$f14,$f19
nmadd.s $f0,$f5,$f25,$f12 nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30 nmsub.d $f30,$f8,$f16,$f30
nmsub.s $f1,$f24,$f19,$f4 nmsub.s $f1,$f24,$f19,$f4
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
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srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r5/valid-fp64.s

# RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s # RUN: FileCheck %s
abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64
sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64

llvm/trunk/test/MC/Mips/mips32r5/valid.s

# Instructions that are valid # Instructions that are valid
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r5 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r5 | FileCheck %s
a: a:
.set noat .set noat
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
add $s7,$s2,$a1 add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
# CHECK-NEXT: # <MCInst #1067 FADD_D32
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $13,$9,26322 addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
addu $9,$a0,$a2 addu $9,$a0,$a2
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
and $s7,$v0,$12 and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
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c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
cvt.d.w $f26,$f11 # CHECK-NEXT: # <MCInst #732 CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #734 CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #748 CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
# CHECK-NEXT: # <MCInst #757 CVT_W_D32
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
deret deret
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
# CHECK-NEXT: # <MCInst #1105 FDIV_D32
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58] eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.w.d $f14,$f11 floor.w.d $f14,$f11
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madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
madd.d $f18,$f19,$f26,$f20 madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhc1 $s8,$f24 mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
# CHECK-NEXT: # <MCInst #1559 MFHC1_D32
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
# CHECK-NEXT: # <MCInst #1160 FMOV_D32
mov.s $f2,$f27 mov.s $f2,$f27
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
movf $gp,$8,$fcc7 movf $gp,$8,$fcc7
movf.d $f6,$f11,$fcc5 movf.d $f6,$f11,$fcc5
movf.s $f23,$f5,$fcc6 movf.s $f23,$f5,$fcc6
movn $v1,$s1,$s0 movn $v1,$s1,$s0
movn.d $f27,$f21,$k0 movn.d $f27,$f21,$k0
movn.s $f12,$f0,$s7 movn.s $f12,$f0,$s7
movt $zero,$s4,$fcc5 movt $zero,$s4,$fcc5
movt.d $f0,$f2,$fcc0 movt.d $f0,$f2,$fcc0
movt.s $f30,$f2,$fcc1 movt.s $f30,$f2,$fcc1
movz $a1,$s6,$9 movz $a1,$s6,$9
movz.d $f12,$f29,$9 movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1 movz.s $f25,$f7,$v1
msub $s7,$k1 msub $s7,$k1
msub.d $f10,$f1,$f31,$f18 msub.d $f10,$f1,$f31,$f18
msub.s $f12,$f19,$f10,$f16 msub.s $f12,$f19,$f10,$f16
msubu $15,$a1 msubu $15,$a1
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
mtc1 $s8,$f9 mtc1 $s8,$f9
mthc1 $zero,$f16 mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00]
# CHECK-NEXT: # <MCInst #1712 MTHC1_D32
mthi $s1 mthi $s1
mtlo $sp mtlo $sp
mtlo $25 mtlo $25
mul $s0,$s4,$at mul $s0,$s4,$at
mul.d $f20,$f20,$f16 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
# CHECK-NEXT: # <MCInst #1170 FMUL_D32
mul.s $f30,$f10,$f2 mul.s $f30,$f10,$f2
mult $sp,$s4 mult $sp,$s4
mult $sp,$v0 mult $sp,$v0
multu $gp,$k0 multu $gp,$k0
multu $9,$s2 multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18 neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
# CHECK-NEXT: # <MCInst #1178 FNEG_D32
neg.s $f1,$f15 neg.s $f1,$f15
nmadd.d $f18,$f9,$f14,$f19 nmadd.d $f18,$f9,$f14,$f19
nmadd.s $f0,$f5,$f25,$f12 nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30 nmsub.d $f30,$f8,$f16,$f30
nmsub.s $f1,$f24,$f19,$f4 nmsub.s $f1,$f24,$f19,$f4
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
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srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
# CHECK-NEXT: # <MCInst #1213 FSUB_D32
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
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