[DAGCombiner] Bail out if vector size is not a multiple

[svenvh]

Summary

For the included test case, visitCONCAT_VECTORS would attempt to
create a v2i32 vector for a v9i8 concat_vector. Bail out to avoid
creating a bitcast with mismatching sizes later on.

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

15191 ↗

(On Diff #130902)

"Bail out if the output vector size is not a multiple of the input vector size."

Shouldn't this be pulled out to near the top of the method?

FoldCONCAT_VECTORS actually treats this as an assert - is there anyway that you can cause it to fire there?

[svenvh]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

15191 ↗

(On Diff #130902)

Not sure if "input vector size" is correct here; we want the output vector size to be a multiple of the scalar size that we input to scalar_to_vector. We only know the scalar size around this point in the code (after deciding whether to look through the trunc).

The concat_vector in itself is fine; which assert in FoldCONCAT_VECTORS do you expect to fire?

[RKSimon]

Sorry, but I misread your change - I've gone through it properly now and LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (In->getOpcode() == ISD::BITCAST &&
           TLI.isTypeLegal(Scalar->getOperand(0).getValueType()))
         Scalar = Scalar->getOperand(0);
 
       EVT SclTy = Scalar->getValueType(0);
 
       if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
         return SDValue();
 
+      // Bail out if the vector size is not a multiple of the scalar size.
+      if (VT.getSizeInBits() % SclTy.getSizeInBits())
+        return SDValue();
+
       unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits();
       if (VNTNumElms < 2)
         return SDValue();
 
       EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, VNTNumElms);
       if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
         return SDValue();
 

llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll

 define amdgpu_kernel void @concat_vector_crash(<8 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
 bb:
   %tmp = load <2 x float>, <2 x float> addrspace(1)* %in, align 4
   %tmp1 = shufflevector <2 x float> %tmp, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %tmp2 = shufflevector <8 x float> undef, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
   store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
   ret void
 }
+
+; FUNC-LABEL: {{^}}concat_vector_crash2:
+; SI: s_endpgm
+define amdgpu_kernel void @concat_vector_crash2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) {
+  %tmp = load i32, i32 addrspace(1)* %in, align 1
+  %tmp1 = trunc i32 %tmp to i24
+  %tmp2 = bitcast i24 %tmp1 to <3 x i8>
+  %tmp3 = shufflevector <3 x i8> %tmp2, <3 x i8> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef>
+  %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 7, i8 8>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
+  store <8 x i8> %tmp4, <8 x i8> addrspace(1)* %out, align 8
+  ret void
+}