[mips] Reordering callseq* nodes to be linear

[abeserminji]

Summary

When calling a function and passing large argument by value, and when argument size is above certain threshold, memcpy is used to copy argument on stack instead of sequence of loads and stores. In that case callseq* nodes for memcpy are nested inside callseq* nodes for the called function. This patch corrects this behavior by moving callseq_start of the called function after arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear.

This is a second try to fix this problem. Previously reverted here rL316215.

[sdardis]

This patch isn't correct, as you're not passing the pointer to the callee or filling the rest of the argument registers with the object being passed. This results in the callee and caller differing in their interpretation of the arguments. The following test case shows this behaviour:

struct S1 {
  char t[32000];
};

extern void f2(char);

void f(int b, struct S1 a) {
  f2(a.t[1] + (char)b) ;
}

void g(void) {
  struct S1 a;
  f(1, a);
}

This compiled with r310704 reverted has the correct IR in that the caller and callee agree that the second argument to f is a pointer to a byval structure argument, but g doesn't set $5 to the result of the memcpy:

addiu $4, $1, 16
addiu $1, $fp, 32016
addiu $5, $1, 12
addiu $6, $zero, 32000
jal memcpy
nop
addiu $4, $zero, 1
sw  $2, 32012($fp)          # 4-byte Folded Spill
jal f
nop

while f believes that the second argument is spread across $5-$7:

addiu $sp, $sp, -32
sw  $ra, 28($sp)            # 4-byte Folded Spill
sw  $fp, 24($sp)            # 4-byte Folded Spill
move  $fp, $sp
sw  $7, 44($fp)
sw  $6, 40($fp)
sw  $5, 36($fp)
sw  $4, 20($fp)
lbu $4, 37($fp)
lw  $5, 20($fp)
addu  $4, $4, $5
seb $4, $4
jal f2

Can you take a look at this?

[abeserminji]

Fixed here: https://reviews.llvm.org/rL327388

lib/Target/Mips/MipsISelLowering.h

private:
     void passByValArg(SDValue Chain, const SDLoc &DL,
                       std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
                       SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
                       MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
                       unsigned FirstReg, unsigned LastReg,
                       const ISD::ArgFlagsTy &Flags, bool isLittle,
                       const CCValAssign &VA) const;
 
+    bool passArgUsingMemcpy(SDValue &Chain, const SDLoc &DL, SDValue StackPtr,
+                            SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
+                            unsigned LastReg, const ISD::ArgFlagsTy &Flags,
+                            const CCValAssign &VA) const;
+
     /// writeVarArgRegs - Write variable function arguments passed in registers
     /// to the stack. Also create a stack frame object for the first variable
     /// argument.
     void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
                          const SDLoc &DL, SelectionDAG &DAG,
                          CCState &State) const;
 
     SDValue

lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   }
   if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
     report_fatal_error("failed to perform tail call elimination on a call "
                        "site marked musttail");
 
   if (IsTailCall)
     ++NumTailCalls;
 
+  // Before initiation of function call, prepare args that need memcpy
+  CCInfo.rewindByValRegsInfo();
+  SDValue StackPtr;
+
+  // This pre-pass is to try to copy an argument to stack using memcpy.
+  // We use copyArgUsingMemcpy to keep track of which args are copied by memcpy.
+  SmallVector<bool, 0> copyArgUsingMemcpy;
+  copyArgUsingMemcpy.resize(ArgLocs.size());
+  unsigned byValCounter = 0;
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+    ISD::ArgFlagsTy Flags = Outs[i].Flags;
+    SDValue Arg = OutVals[i];
+    CCValAssign &VA = ArgLocs[i];
+    if(Flags.isByVal()){
+      StackPtr =
+          DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
+                             getPointerTy(DAG.getDataLayout()));
+      unsigned FirstByValReg, LastByValReg;
+      unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
+      CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
+      // Here we call passArgUsingMemcpy which will try to
+      // copy an argument using memcpy, and if memcpy is used
+      // it retuns true.
+      bool useMemcpy = passArgUsingMemcpy(Chain, DL, StackPtr, DAG, Arg,
+                                          FirstByValReg, LastByValReg, Flags,
+                                          VA);
+      copyArgUsingMemcpy[byValCounter++] = useMemcpy;
+
+      CCInfo.nextInRegsParam();
+    }
+  }
+
   // Chain is the output chain of the last Load/Store or CopyToReg node.
   // ByValChain is the output chain of the last Memcpy node created for copying
   // byval arguments to the stack.
   unsigned StackAlignment = TFL->getStackAlignment();
   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
 
   if (!IsTailCall)
     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
 
-  SDValue StackPtr =
+  StackPtr =
       DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
                          getPointerTy(DAG.getDataLayout()));
 
   std::deque<std::pair<unsigned, SDValue>> RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
 
   CCInfo.rewindByValRegsInfo();
+  byValCounter = 0;
 
   // Walk the register/memloc assignments, inserting copies/loads.
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     SDValue Arg = OutVals[i];
     CCValAssign &VA = ArgLocs[i];
     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
     ISD::ArgFlagsTy Flags = Outs[i].Flags;
     bool UseUpperBits = false;
 
     // ByVal Arg.
     if (Flags.isByVal()) {
+      // Check if argument is already copied using memcpy.
+      if (copyArgUsingMemcpy[byValCounter++]) {
+        CCInfo.nextInRegsParam();
+        continue;
+      }
       unsigned FirstByValReg, LastByValReg;
       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
 
       assert(Flags.getByValSize() &&
              "ByVal args of size 0 should have been ignored by front-end.");
       assert(ByValIdx < CCInfo.getInRegsParamsCount());
       assert(!IsTailCall &&
for (unsigned I = 0; I < NumRegs; ++I) {
     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
                                    DAG.getConstant(Offset, DL, PtrTy));
     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
                                  StorePtr, MachinePointerInfo(FuncArg, Offset));
     OutChains.push_back(Store);
   }
 }
 
+// Try to copy byVal arg using memcpy
+bool MipsTargetLowering::passArgUsingMemcpy(
+    SDValue &Chain, const SDLoc &DL, SDValue StackPtr,
+    SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
+    unsigned LastReg, const ISD::ArgFlagsTy &Flags,
+    const CCValAssign &VA) const {
+  unsigned ByValSizeInBytes = Flags.getByValSize();
+  unsigned OffsetInBytes = 0; // From beginning of struct
+  unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
+  unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
+  EVT PtrTy = getPointerTy(DAG.getDataLayout());
+  unsigned NumRegs = LastReg - FirstReg;
+  bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
+  unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
+  OffsetInBytes = (NumRegs - LeftoverBytes) * RegSizeInBytes;
+
+  if (NumRegs) {
+    if (LeftoverBytes || OffsetInBytes == ByValSizeInBytes) {
+      return false;
+    }
+  }
+
+  SDValue MemCpyCall;
+  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
+                            DAG.getConstant(OffsetInBytes, DL, PtrTy));
+  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
+                            DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
+  MemCpyCall = DAG.getMemcpy(Chain, DL, Dst, Src,
+                            DAG.getConstant(MemCpySize, DL, PtrTy),
+                            Alignment, /*isVolatile=*/false,
+                            /*AlwaysInline=*/false,
+                            /*isTailCall=*/false,
+                            MachinePointerInfo(), MachinePointerInfo());
+  // If the first node in returned MemCpyCall is CopyFromReg,
+  // it means that memcpy is used to copy an argument.
+  if (MemCpyCall.getNode()->getOpcode() == ISD::CopyFromReg) {
+    Chain = MemCpyCall;
+    return true;
+  }
+
+  return false;
+}
+
 // Copy byVal arg to registers and stack.
 void MipsTargetLowering::passByValArg(
     SDValue Chain, const SDLoc &DL,
     std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
     SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
     MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
     unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
     const CCValAssign &VA) const {
if (LeftoverBytes) {
       }
 
       unsigned ArgReg = ArgRegs[FirstReg + I];
       RegsToPass.push_back(std::make_pair(ArgReg, Val));
       return;
     }
   }
 
-  // Copy remainder of byval arg to it with memcpy.
+  // Copy remainder of byval arg to it with memcpy lowered to loads and stores.
   unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
                             DAG.getConstant(OffsetInBytes, DL, PtrTy));
   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
                             DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
   Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
                         DAG.getConstant(MemCpySize, DL, PtrTy),
                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,