[mips] Add assembler support for '.set mipsX'.

[tomatabacu]

Summary

This patch also fixes an issue with the way the Mips assembler enables/disables architecture
features. Before this patch, the assembler never disabled feature bits. For example,
.set mips64
.set mips32r2

would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right.
Unfortunately this isn't trivial to fix because there's not an easy way to clear
feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits
that imply the feature being cleared and not the implied bits by the feature (there's a
better explanation to the code I added).

[dsanders]

The patch looks good to me but as you say, it needs to be reviewed on-list because of the change to MCSubtargetInfo

test/MC/Mips/set-mips-directives-bad.s

4–6

I misread this the first time since ll is both an instruction and a filetype. Could you add write 'the ll instruction' or similar?

[vmedic]

Looks good to me with a nit(comment). I agree it should be sent to commit list for a review.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

243

I think this comment is not correct, shouldn't it be "clear (FeatureMips3 | FeatureMips2 | FeatureMipsGP64 | FeatureMips1)" ?

[matheusalmeida]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

243

Please see function ClearImpliedBits in SubtargetFeature.cpp. It only clears the features that imply the bit being cleared and not the other way around. It might be clearer for you if you compare the two functions (SetImpliedBits and ClearImpliedBits).

[matheusalmeida]

CC'ing the list because there's a small modification to MCSubtargetInfo.h.

This patch adds support to many of the .set mipsX assembler directives that allow an ISA to be selected/deselected in the same translation unit. Example:

.text
.set mips32
// Mips32 ISA available
.set mips64
// Mips64 ISA available

Mips ISAs are defined with respect to older ISAs. For example:

FeatureMips1 : None
FeatureMips2 : FeatureMips1
FeatureMips3 : FeatureMips2 | FeatureMipsGP64
and so on...

One of the issues of disabling a feature is that the function ClearImpliedBits in SubtargetFeature only clears the features that imply the feature being cleared. As an example, clearing the FeatureMips3 will not clear (FeatureMips2 | FeatureMipsGP64 | FeatureMips1).

The idea behind this patch is that every time we select a new ISA, we clear all the bits related to ISAs (updating MCSubtargetInfo) and select the new one as 'setImpliedBits' does the right thing.

Does this make sense ?

Regards,
Matheus

[tomatabacu]

Commandeered to finish off the patch and make it ready for commit.

[tomatabacu]

For MipsAsmParser.cpp:
Corrected grammar in comment (double "by") in line 54.

For MipsTargetStreamer.cpp:
Added dummy implementations of the functions introduced by the patch to the MipsTargetStreamer class.
Added "setCanHaveModuleDir(false);" to the definitions of the functions introduced by the patch in both MipsTargetAsmStreamer and MipsTargetELFStreamer classes.

For MipsTargetStreamer.h:
Changed virtual member functions of MipsTargetStreamer introduced by the patch to not be pure virtual functions.

For set-mips-directives-bad.s:
Addressed a concern about the comment.

Rebased to trunk.

[tomatabacu]

Ran clang-format and rebased.

[dsanders]

LGTM. There is a cleanup that I'd like to be done afterwards though.

At the moment, MipsTargetELFStreamer::emitDirectiveSetMips*() and MipsTargetAsmStreamer::emitDirectiveSetMips*() both call setCanHaveModuleDir(). We should move this call to the base class (MipsTargetStreamer), delete MipsTargetELFStreamer::emitDirectiveSetMips*() since they no longer do anything and have MipsTargetAsmStreamer::emitDirectiveSetMips*() call the base class implementation after emitting the directive.

include/llvm/MC/MCSubtargetInfo.h

public:
   }
 
   /// getFeatureBits - Return the feature bits.
   ///
   uint64_t getFeatureBits() const {
     return FeatureBits;
   }
 
+  /// setFeatureBits - Set the feature bits.
+  ///
+  void setFeatureBits(uint64_t _FeatureBits) {
+    FeatureBits = _FeatureBits;
+  }
+
   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
   /// feature string). Recompute feature bits and scheduling model.
   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
 
   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
   void InitCPUSchedModel(StringRef CPU);
 
   /// ToggleFeature - Toggle a feature and returns the re-computed feature

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

public:
   bool isReorder() { return reorder; }
   void setReorder() { reorder = true; }
   void setNoreorder() { reorder = false; }
 
   bool isMacro() { return macro; }
   void setMacro() { macro = true; }
   void setNomacro() { macro = false; }
 
+  // Set of features that are either architecture features or referenced by
+  // by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6).
+  // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
+  // The reason we need this mask is explained in the selectArch function.
+  // FIXME: Ideally we would like TableGen to generate this information.
+  static const uint64_t AllArchRelatedMask =
+      Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 |
+      Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
+      Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
+      Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
+      Mips::FeatureMips32r6 | Mips::FeatureMips64 | Mips::FeatureMips64r2 |
+      Mips::FeatureMips64r6 | Mips::FeatureCnMips | Mips::FeatureFP64Bit |
+      Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
 private:
   unsigned aTReg;
   bool reorder;
   bool macro;
 };
 }
 
 namespace {
#include "MipsGenAsmMatcher.inc"
   bool processInstruction(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
   // Helper function that checks if the value of a vector index is within the
   // boundaries of accepted values for each RegisterKind
   // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
   bool validateMSAIndex(int Val, int RegKind);
 
+  // Selects a new architecture by updating the FeatureBits with the necessary
+  // info including implied dependencies.
+  // Internally, it clears all the feature bits related to *any* architecture
+  // and selects the new one using the ToggleFeature functionality of the
+  // MCSubtargetInfo object that handles implied dependencies. The reason we
+  // clear all the arch related bits manually is because ToggleFeature only
+  // clears the features that imply the feature being cleared and not the
+  // features implied by the feature being cleared. This is easier to see
+  // with an example:
+  //  --------------------------------------------------
+  // | Feature         | Implies                        |
+  // | -------------------------------------------------|
+  // | FeatureMips1    | None                           |
+  // | FeatureMips2    | FeatureMips1                   |
+  // | FeatureMips3    | FeatureMips2 | FeatureMipsGP64 |
+  // | FeatureMips4    | FeatureMips3                   |
+  // | ...             |                                |
+  //  --------------------------------------------------
+  //
+  // Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 |
+  // FeatureMipsGP64 | FeatureMips1)
+  // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
+  void selectArch(StringRef ArchFeature) {
+    uint64_t FeatureBits = STI.getFeatureBits();
+    FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
+    STI.setFeatureBits(FeatureBits);
+    setAvailableFeatures(
+        ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
+  }
+
   void setFeatureBits(unsigned Feature, StringRef FeatureString) {
     if (!(STI.getFeatureBits() & Feature)) {
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
     }
   }
 
   void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
case Mips::FeatureDSP:
     getTargetStreamer().emitDirectiveSetDsp();
     break;
   case Mips::FeatureMicroMips:
     getTargetStreamer().emitDirectiveSetMicroMips();
     break;
   case Mips::FeatureMips16:
     getTargetStreamer().emitDirectiveSetMips16();
     break;
+  case Mips::FeatureMips1:
+    selectArch("mips1");
+    getTargetStreamer().emitDirectiveSetMips1();
+    break;
+  case Mips::FeatureMips2:
+    selectArch("mips2");
+    getTargetStreamer().emitDirectiveSetMips2();
+    break;
+  case Mips::FeatureMips3:
+    selectArch("mips3");
+    getTargetStreamer().emitDirectiveSetMips3();
+    break;
+  case Mips::FeatureMips4:
+    selectArch("mips4");
+    getTargetStreamer().emitDirectiveSetMips4();
+    break;
+  case Mips::FeatureMips5:
+    selectArch("mips5");
+    getTargetStreamer().emitDirectiveSetMips5();
+    break;
+  case Mips::FeatureMips32:
+    selectArch("mips32");
+    getTargetStreamer().emitDirectiveSetMips32();
+    break;
   case Mips::FeatureMips32r2:
-    setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
+    selectArch("mips32r2");
     getTargetStreamer().emitDirectiveSetMips32R2();
     break;
+  case Mips::FeatureMips32r6:
+    selectArch("mips32r6");
+    getTargetStreamer().emitDirectiveSetMips32R6();
+    break;
   case Mips::FeatureMips64:
-    setFeatureBits(Mips::FeatureMips64, "mips64");
+    selectArch("mips64");
     getTargetStreamer().emitDirectiveSetMips64();
     break;
   case Mips::FeatureMips64r2:
-    setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
+    selectArch("mips64r2");
     getTargetStreamer().emitDirectiveSetMips64R2();
     break;
+  case Mips::FeatureMips64r6:
+    selectArch("mips64r6");
+    getTargetStreamer().emitDirectiveSetMips64R6();
+    break;
   }
   return false;
 }
 
 bool MipsAsmParser::parseRegister(unsigned &RegNum) {
   if (!getLexer().is(AsmToken::Dollar))
     return false;
 
bool MipsAsmParser::parseDirectiveSet() {
   } else if (Tok.getString() == "nomips16") {
     return parseSetNoMips16Directive();
   } else if (Tok.getString() == "nomicromips") {
     getTargetStreamer().emitDirectiveSetNoMicroMips();
     Parser.eatToEndOfStatement();
     return false;
   } else if (Tok.getString() == "micromips") {
     return parseSetFeature(Mips::FeatureMicroMips);
+  } else if (Tok.getString() == "mips1") {
+    return parseSetFeature(Mips::FeatureMips1);
+  } else if (Tok.getString() == "mips2") {
+    return parseSetFeature(Mips::FeatureMips2);
+  } else if (Tok.getString() == "mips3") {
+    return parseSetFeature(Mips::FeatureMips3);
+  } else if (Tok.getString() == "mips4") {
+    return parseSetFeature(Mips::FeatureMips4);
+  } else if (Tok.getString() == "mips5") {
+    return parseSetFeature(Mips::FeatureMips5);
+  } else if (Tok.getString() == "mips32") {
+    return parseSetFeature(Mips::FeatureMips32);
   } else if (Tok.getString() == "mips32r2") {
     return parseSetFeature(Mips::FeatureMips32r2);
+  } else if (Tok.getString() == "mips32r6") {
+    return parseSetFeature(Mips::FeatureMips32r6);
   } else if (Tok.getString() == "mips64") {
     return parseSetFeature(Mips::FeatureMips64);
   } else if (Tok.getString() == "mips64r2") {
     return parseSetFeature(Mips::FeatureMips64r2);
+  } else if (Tok.getString() == "mips64r6") {
+    return parseSetFeature(Mips::FeatureMips64r6);
   } else if (Tok.getString() == "dsp") {
     return parseSetFeature(Mips::FeatureDSP);
   } else {
     // It is just an identifier, look for an assignment.
     parseSetAssignment();
     return false;
   }
 

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
                                       unsigned ReturnReg) {
   OS << "\t.frame\t$"
      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
      << StackSize << ",$"
      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
+  OS << "\t.set\tmips1\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
+  OS << "\t.set\tmips2\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
+  OS << "\t.set\tmips3\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
+  OS << "\t.set\tmips4\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
+  OS << "\t.set\tmips5\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
+  OS << "\t.set\tmips32\n";
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
   OS << "\t.set\tmips32r2\n";
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
+  OS << "\t.set\tmips32r6\n";
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
   OS << "\t.set\tmips64\n";
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
   OS << "\t.set\tmips64r2\n";
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
+  OS << "\t.set\tmips64r6\n";
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
   OS << "\t.set\tdsp\n";
 }
 // Print a 32 bit hex number with all numbers.
 static void printHex32(unsigned Value, raw_ostream &OS) {
   OS << "0x";
   for (int i = 7; i >= 0; i--)
     OS.write_hex((Value & (0xF << (i*4))) >> (i*4));
void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
   // FIXME: implement.
 }
 
 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
                                       int FPUTopSavedRegOff) {
   // FIXME: implement.
 }
 
+void MipsTargetELFStreamer::emitDirectiveSetMips1() {
+  // No action required for ELF output.
+}
+
+void MipsTargetELFStreamer::emitDirectiveSetMips2() {
+  // No action required for ELF output.
+}
+
+void MipsTargetELFStreamer::emitDirectiveSetMips3() {
+  // No action required for ELF output.
+}
+
+void MipsTargetELFStreamer::emitDirectiveSetMips4() {
+  // No action required for ELF output.
+}
+
+void MipsTargetELFStreamer::emitDirectiveSetMips5() {
+  // No action required for ELF output.
+}
+
+void MipsTargetELFStreamer::emitDirectiveSetMips32() {
+  // No action required for ELF output.
+}
+
 void MipsTargetELFStreamer::emitDirectiveSetMips32R2() {
   // No action required for ELF output.
 }
 
+void MipsTargetELFStreamer::emitDirectiveSetMips32R6() {
+  // No action required for ELF output.
+}
+
 void MipsTargetELFStreamer::emitDirectiveSetMips64() {
   // No action required for ELF output.
 }
 
 void MipsTargetELFStreamer::emitDirectiveSetMips64R2() {
   // No action required for ELF output.
 }
 
+void MipsTargetELFStreamer::emitDirectiveSetMips64R6() {
+  // No action required for ELF output.
+}
+
 void MipsTargetELFStreamer::emitDirectiveSetDsp() {
   // No action required for ELF output.
 }
 
 void MipsTargetELFStreamer::emitDirectiveCpload(unsigned RegNo) {
   // .cpload $reg
   // This directive expands to:
   // lui   $gp, %hi(_gp_disp)

lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveNaNLegacy() = 0;
   virtual void emitDirectiveOptionPic0() = 0;
   virtual void emitDirectiveOptionPic2() = 0;
   virtual void emitFrame(unsigned StackReg, unsigned StackSize,
                          unsigned ReturnReg) = 0;
   virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) = 0;
   virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) = 0;
 
+  virtual void emitDirectiveSetMips1() = 0;
+  virtual void emitDirectiveSetMips2() = 0;
+  virtual void emitDirectiveSetMips3() = 0;
+  virtual void emitDirectiveSetMips4() = 0;
+  virtual void emitDirectiveSetMips5() = 0;
+  virtual void emitDirectiveSetMips32() = 0;
   virtual void emitDirectiveSetMips32R2() = 0;
+  virtual void emitDirectiveSetMips32R6() = 0;
   virtual void emitDirectiveSetMips64() = 0;
   virtual void emitDirectiveSetMips64R2() = 0;
+  virtual void emitDirectiveSetMips64R6() = 0;
   virtual void emitDirectiveSetDsp() = 0;
 
   // PIC support
   virtual void emitDirectiveCpload(unsigned RegNo) = 0;
   virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                     const MCSymbol &Sym, bool IsReg) = 0;
 };
 
public:
   void emitDirectiveNaNLegacy() override;
   void emitDirectiveOptionPic0() override;
   void emitDirectiveOptionPic2() override;
   void emitFrame(unsigned StackReg, unsigned StackSize,
                  unsigned ReturnReg) override;
   void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
+  void emitDirectiveSetMips1() override;
+  void emitDirectiveSetMips2() override;
+  void emitDirectiveSetMips3() override;
+  void emitDirectiveSetMips4() override;
+  void emitDirectiveSetMips5() override;
+  void emitDirectiveSetMips32() override;
   void emitDirectiveSetMips32R2() override;
+  void emitDirectiveSetMips32R6() override;
   void emitDirectiveSetMips64() override;
   void emitDirectiveSetMips64R2() override;
+  void emitDirectiveSetMips64R6() override;
   void emitDirectiveSetDsp() override;
 
   // PIC support
   virtual void emitDirectiveCpload(unsigned RegNo);
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 };
 
public:
   void emitDirectiveNaNLegacy() override;
   void emitDirectiveOptionPic0() override;
   void emitDirectiveOptionPic2() override;
   void emitFrame(unsigned StackReg, unsigned StackSize,
                  unsigned ReturnReg) override;
   void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
+  void emitDirectiveSetMips1() override;
+  void emitDirectiveSetMips2() override;
+  void emitDirectiveSetMips3() override;
+  void emitDirectiveSetMips4() override;
+  void emitDirectiveSetMips5() override;
+  void emitDirectiveSetMips32() override;
   void emitDirectiveSetMips32R2() override;
+  void emitDirectiveSetMips32R6() override;
   void emitDirectiveSetMips64() override;
   void emitDirectiveSetMips64R2() override;
+  void emitDirectiveSetMips64R6() override;
   void emitDirectiveSetDsp() override;
 
   // PIC support
   virtual void emitDirectiveCpload(unsigned RegNo);
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 
 protected:
   bool isO32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
   bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
   bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
 };
 }
 #endif

test/MC/Mips/set-mips-directives-bad.s

+# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 2>%t1
+# RUN: FileCheck %s < %t1
+
+# FIXME: At the moment we emit the wrong error message if we try to assemble
+# ll using an unsupported architecture so we just check for "error" and ignore
+# the rest of the message.
+
+        .text
+        .set noreorder
+        .set mips1
+        ll  $2,-2($2) # CHECK: error:
+        .set mips2
+        dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips3
+        ldxc1 $f8,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips4
+        luxc1 $f19,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips5
+        clo  $2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips32
+        rotr    $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips32r2
+        mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
+        .set mips32r6
+        daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64
+        drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r2
+        mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
+

test/MC/Mips/set-mips-directives.s

+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 | \
+# RUN:   FileCheck %s
+
+        .text
+        .set noreorder
+        .set mips1
+        add $2, $2, $2
+        .set mips2
+        ll  $2,-2($2)
+        .set mips3
+        dadd $2,$2,$2
+        .set mips4
+        ldxc1 $f8,$2($4)
+        .set mips5
+        luxc1 $f19,$2($4)
+        .set mips32
+        clo  $2,$2
+        .set mips32r2
+        rotr    $2,15
+        .set mips32r6
+        mod $2, $4, $6
+        .set mips64
+        daddi $2, $2, 10
+        .set mips64r2
+        drotr32 $1,$14,15
+        .set mips64r6
+        mod $2, $4, $6
+
+# CHECK: .set noreorder
+# CHECK: .set mips1
+# CHECK: add $2, $2, $2
+# CHECK: .set mips2
+# CHECK: ll  $2, -2($2)
+# CHECK: .set mips3
+# CHECK: dadd $2, $2, $2
+# CHECK: .set mips4
+# CHECK: ldxc1 $f8, $2($4)
+# CHECK: .set mips5
+# CHECK: luxc1 $f19, $2($4)
+# CHECK: .set mips32
+# CHECK: clo $2, $2
+# CHECK: .set mips32r2
+# CHECK: rotr $2, $2, 15
+# CHECK: .set mips32r6
+# CHECK: mod $2, $4, $6
+# CHECK: .set mips64
+# CHECK: daddi $2, $2, 10
+# CHECK: .set mips64r2
+# CHECK:  drotr32 $1, $14, 15
+# CHECK: .set mips64r6
+# CHECK: mod $2, $4, $6