Remove Unsupported flag from T99 Scheduler

[steleman]

Summary

This patch removes the Unsupported = 1 flag for the WriteAtomic WriteRes.

In practice, this patch has no effect on scheduling.

There is no test case as there already exists a comprehensive test case for LSE Atomics.

[steleman]

Ping!

[fhahn]

Sorry I missed this one! LGTM, assuming you are happy with effect on ThunderX2!

[steleman]

In D40694#970346, @fhahn wrote:

Sorry I missed this one! LGTM, assuming you are happy with effect on ThunderX2!

Thank you. Yes I am happy - because at least right now the effect is zero. :-)

[fhahn]

Could you please prefix the title of the commit message with [AArch64]?

[steleman]

In D40694#970457, @fhahn wrote:

Could you please prefix the title of the commit message with [AArch64]?

Sure - I'll ask Joel to do that since I don't have commit privileges and it's usually Joel who does my commits for me.

[joelkevinjones]

Okay, I'll be sure to add "[AArch64]" when I do the commit.

lib/Target/AArch64/AArch64SchedThunderX2T99.td

   let NumMicroOps = 2;
 }
 
 // Branch, register
 // Branch and link, register != LR
 // Branch and link, register = LR
 def : WriteRes<WriteBrReg,   [THX2T99I2]> {
   let Latency = 1;
   let NumMicroOps = 2;
 }
 
 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 
 def : WriteRes<WriteAtomic,  []> {
-  let Unsupported = 1;
+  let Latency = 4;
   let NumMicroOps = 2;
 }
 
 //---
 // Branch
 //---
 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>;
 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>;
 def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B..$")>;
 def : InstRW<[THX2T99Write_1Cyc_I2],
             (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>;
 
 //---
 // 3.2 Arithmetic and Logical Instructions
 // 3.3 Move and Shift Instructions
 //---