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Differential D40419

[CodeGen] Separate MachineOperand implementation from MachineInstr
ClosedPublic

Authored by thegameg on Nov 24 2017, 3:33 AM.

Details

Reviewers
MatzeB
qcolombet
Commits
rGaa739695a4ae: [CodeGen] Separate MachineOperand implementation from MachineInstr
rL319194: [CodeGen] Separate MachineOperand implementation from MachineInstr
Summary

Move the implementation to its own file.

Diff Detail

Event Timeline

thegameg created this revision.Nov 24 2017, 3:33 AM
Herald added a subscriber: mgorny. · View Herald TranscriptNov 24 2017, 3:33 AM
thegameg updated this revision to Diff 124200.Nov 24 2017, 6:30 AM

Fix file header.

MatzeB accepted this revision.Nov 27 2017, 11:31 AM

LGTM, thanks. I'd commit the MachineOperand.h changes in a separate commit.

Feel free to do the doxygen comment cleanups in a separate future commit if you like.

lib/CodeGen/MachineOperand.cpp
10

Use /// \file ... so doxygen can pick it up.

32–34

This is unnecessary now as the whole file is about MachineOperand.

80

As we are on it: Would be good to move the doxygen comments from the implementation to the header where possible.

113–115

In cases where we have a doxygen comment in the implementation and the declaration we should just remove it from the implementation.

This revision is now accepted and ready to land.Nov 27 2017, 11:31 AM
Closed by commit rL319194: [CodeGen] Separate MachineOperand implementation from MachineInstr (authored by thegameg). · Explain WhyNov 28 2017, 9:59 AM
This revision was automatically updated to reflect the committed changes.
thegameg marked 4 inline comments as done.
MatzeB added inline comments.Nov 28 2017, 11:04 AM
llvm/trunk/lib/CodeGen/MachineOperand.cpp
10–11 ↗(On Diff #124598)

This should be:

/// \file Methods common to all machine operands.

(just look around some other files for examples).

thegameg marked an inline comment as done.Nov 28 2017, 11:17 AM
thegameg added inline comments.
llvm/trunk/lib/CodeGen/MachineOperand.cpp
10–11 ↗(On Diff #124598)

Ok, fixed in r319206 (I actually did look around, but it looks like the version with a newline is more popular)

Revision Contents

PathSize
include/
llvm/
CodeGen/
33 lines
lib/
CodeGen/
1 line
721 lines
754 lines

Diff 124200

include/llvm/CodeGen/MachineOperand.h

Show First 20 Lines • Show All 635 Lines • ▼ Show 20 Lines static MachineOperand CreateFPImm(const ConstantFP *CFP) {
Op.Contents.CFP = CFP; Op.Contents.CFP = CFP;
return Op; return Op;
} }
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
bool isKill = false, bool isDead = false, bool isKill = false, bool isDead = false,
bool isUndef = false, bool isUndef = false,
bool isEarlyClobber = false, bool isEarlyClobber = false,
unsigned SubReg = 0, unsigned SubReg = 0, bool isDebug = false,
bool isDebug = false,
bool isInternalRead = false) { bool isInternalRead = false) {
assert(!(isDead && !isDef) && "Dead flag on non-def"); assert(!(isDead && !isDef) && "Dead flag on non-def");
assert(!(isKill && isDef) && "Kill flag on def"); assert(!(isKill && isDef) && "Kill flag on def");
MachineOperand Op(MachineOperand::MO_Register); MachineOperand Op(MachineOperand::MO_Register);
Op.IsDef = isDef; Op.IsDef = isDef;
Op.IsImp = isImp; Op.IsImp = isImp;
Op.IsKill = isKill; Op.IsKill = isKill;
Op.IsDead = isDead; Op.IsDead = isDead;
Show All 31 Linespublic:
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_TargetIndex); MachineOperand Op(MachineOperand::MO_TargetIndex);
Op.setIndex(Idx); Op.setIndex(Idx);
Op.setOffset(Offset); Op.setOffset(Offset);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
static MachineOperand CreateJTI(unsigned Idx, static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_JumpTableIndex); MachineOperand Op(MachineOperand::MO_JumpTableIndex);
Op.setIndex(Idx); Op.setIndex(Idx);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_GlobalAddress); MachineOperand Op(MachineOperand::MO_GlobalAddress);
Show All 14 Lines static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_BlockAddress); MachineOperand Op(MachineOperand::MO_BlockAddress);
Op.Contents.OffsetedInfo.Val.BA = BA; Op.Contents.OffsetedInfo.Val.BA = BA;
Op.setOffset(Offset); Op.setOffset(Offset);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
/// CreateRegMask - Creates a register mask operand referencing Mask. The /// CreateRegMask - Creates a register mask operand referencing Mask. The
/// operand does not take ownership of the memory referenced by Mask, it must /// operand does not take ownership of the memory referenced by Mask, it
/// remain valid for the lifetime of the operand. /// must remain valid for the lifetime of the operand.
/// ///
/// A RegMask operand represents a set of non-clobbered physical registers on /// A RegMask operand represents a set of non-clobbered physical registers
/// an instruction that clobbers many registers, typically a call. The bit /// on an instruction that clobbers many registers, typically a call. The
/// mask has a bit set for each physreg that is preserved by this /// bit mask has a bit set for each physreg that is preserved by this
/// instruction, as described in the documentation for /// instruction, as described in the documentation for
/// TargetRegisterInfo::getCallPreservedMask(). /// TargetRegisterInfo::getCallPreservedMask().
/// ///
/// Any physreg with a 0 bit in the mask is clobbered by the instruction. /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
/// ///
static MachineOperand CreateRegMask(const uint32_t *Mask) { static MachineOperand CreateRegMask(const uint32_t *Mask) {
assert(Mask && "Missing register mask"); assert(Mask && "Missing register mask");
MachineOperand Op(MachineOperand::MO_RegisterMask); MachineOperand Op(MachineOperand::MO_RegisterMask);
Show All 36 Linespublic:
static MachineOperand CreatePredicate(unsigned Pred) { static MachineOperand CreatePredicate(unsigned Pred) {
MachineOperand Op(MachineOperand::MO_Predicate); MachineOperand Op(MachineOperand::MO_Predicate);
Op.Contents.Pred = Pred; Op.Contents.Pred = Pred;
return Op; return Op;
} }
friend class MachineInstr; friend class MachineInstr;
friend class MachineRegisterInfo; friend class MachineRegisterInfo;
private: private:
void removeRegFromUses(); void removeRegFromUses();
/// Artificial kinds for DenseMap usage. /// Artificial kinds for DenseMap usage.
enum : unsigned char { enum : unsigned char {
MO_Empty = MO_Last + 1, MO_Empty = MO_Last + 1,
MO_Tombstone, MO_Tombstone,
}; };
friend struct DenseMapInfo<MachineOperand>; friend struct DenseMapInfo<MachineOperand>;
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Methods for handling register use/def lists. // Methods for handling register use/def lists.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// isOnRegUseList - Return true if this operand is on a register use/def list /// isOnRegUseList - Return true if this operand is on a register use/def
/// or false if not. This can only be called for register operands that are /// list or false if not. This can only be called for register operands
/// part of a machine instruction. /// that are part of a machine instruction.
bool isOnRegUseList() const { bool isOnRegUseList() const {
assert(isReg() && "Can only add reg operand to use lists"); assert(isReg() && "Can only add reg operand to use lists");
return Contents.Reg.Prev != nullptr; return Contents.Reg.Prev != nullptr;
} }
}; };
template <> struct DenseMapInfo<MachineOperand> { template <> struct DenseMapInfo<MachineOperand> {
static MachineOperand getEmptyKey() { static MachineOperand getEmptyKey() {
Show All 12 Lines if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
MachineOperand::MO_Empty) || MachineOperand::MO_Empty) ||
LHS.getType() == static_cast<MachineOperand::MachineOperandType>( LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
MachineOperand::MO_Tombstone)) MachineOperand::MO_Tombstone))
return LHS.getType() == RHS.getType(); return LHS.getType() == RHS.getType();
return LHS.isIdenticalTo(RHS); return LHS.isIdenticalTo(RHS);
} }
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
MO.print(OS, nullptr); MO.print(OS, nullptr);
return OS; return OS;
} }
// See friend declaration above. This additional declaration is required in // See friend declaration above. This additional declaration is required in
// order to compile LLVM with IBM xlC compiler. // order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const MachineOperand &MO); hash_code hash_value(const MachineOperand &MO);
} // End llvm namespace } // namespace llvm
#endif #endif

lib/CodeGen/CMakeLists.txt

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesadd_llvm_library(LLVMCodeGen
MachineFunctionPass.cpp MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp MachineFunctionPrinterPass.cpp
MachineInstrBundle.cpp MachineInstrBundle.cpp
MachineInstr.cpp MachineInstr.cpp
MachineLICM.cpp MachineLICM.cpp
MachineLoopInfo.cpp MachineLoopInfo.cpp
MachineModuleInfo.cpp MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp MachineModuleInfoImpls.cpp
MachineOperand.cpp
MachineOptimizationRemarkEmitter.cpp MachineOptimizationRemarkEmitter.cpp
MachineOutliner.cpp MachineOutliner.cpp
MachinePassRegistry.cpp MachinePassRegistry.cpp
MachinePipeliner.cpp MachinePipeliner.cpp
MachinePostDominators.cpp MachinePostDominators.cpp
MachineRegionInfo.cpp MachineRegionInfo.cpp
MachineRegisterInfo.cpp MachineRegisterInfo.cpp
MachineScheduler.cpp MachineScheduler.cpp
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

lib/CodeGen/MachineInstr.cpp

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
#include <cstddef> #include <cstddef>
#include <cstdint> #include <cstdint>
#include <cstring> #include <cstring>
#include <iterator> #include <iterator>
#include <utility> #include <utility>
using namespace llvm; using namespace llvm;
static cl::opt<int> PrintRegMaskNumRegs(
"print-regmask-num-regs",
cl::desc("Number of registers to limit to when "
"printing regmask operands in IR dumps. "
"unlimited = -1"),
cl::init(32), cl::Hidden);
//===----------------------------------------------------------------------===//
// MachineOperand Implementation
//===----------------------------------------------------------------------===//
void MachineOperand::setReg(unsigned Reg) {
if (getReg() == Reg) return; // No change.
// Otherwise, we have to change the register. If this operand is embedded
// into a machine function, we need to update the old and new register's
// use/def lists.
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent()) {
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.removeRegOperandFromUseList(this);
SmallContents.RegNo = Reg;
MRI.addRegOperandToUseList(this);
return;
}
// Otherwise, just change the register, no problem. :)
SmallContents.RegNo = Reg;
}
void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
const TargetRegisterInfo &TRI) {
assert(TargetRegisterInfo::isVirtualRegister(Reg));
if (SubIdx && getSubReg())
SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
setReg(Reg);
if (SubIdx)
setSubReg(SubIdx);
}
void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
if (getSubReg()) {
Reg = TRI.getSubReg(Reg, getSubReg());
// Note that getSubReg() may return 0 if the sub-register doesn't exist.
// That won't happen in legal code.
setSubReg(0);
if (isDef())
setIsUndef(false);
}
setReg(Reg);
}
/// Change a def to a use, or a use to a def.
void MachineOperand::setIsDef(bool Val) {
assert(isReg() && "Wrong MachineOperand accessor");
assert((!Val || !isDebug()) && "Marking a debug operation as def");
if (IsDef == Val)
return;
// MRI may keep uses and defs in different list positions.
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent()) {
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.removeRegOperandFromUseList(this);
IsDef = Val;
MRI.addRegOperandToUseList(this);
return;
}
IsDef = Val;
}
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
void MachineOperand::removeRegFromUses() {
if (!isReg() || !isOnRegUseList())
return;
if (MachineInstr *MI = getParent()) {
if (MachineBasicBlock *MBB = MI->getParent()) {
if (MachineFunction *MF = MBB->getParent())
MF->getRegInfo().removeRegOperandFromUseList(this);
}
}
}
/// ChangeToImmediate - Replace this operand with a new immediate operand of
/// the specified value. If an operand is known to be an immediate already,
/// the setImm method should be used.
void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
removeRegFromUses();
OpKind = MO_Immediate;
Contents.ImmVal = ImmVal;
}
void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
removeRegFromUses();
OpKind = MO_FPImmediate;
Contents.CFP = FPImm;
}
void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into an external symbol");
removeRegFromUses();
OpKind = MO_ExternalSymbol;
Contents.OffsetedInfo.Val.SymbolName = SymName;
setOffset(0); // Offset is always 0.
setTargetFlags(TargetFlags);
}
void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into an MCSymbol");
removeRegFromUses();
OpKind = MO_MCSymbol;
Contents.Sym = Sym;
}
void MachineOperand::ChangeToFrameIndex(int Idx) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into a FrameIndex");
removeRegFromUses();
OpKind = MO_FrameIndex;
setIndex(Idx);
}
void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
unsigned char TargetFlags) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into a FrameIndex");
removeRegFromUses();
OpKind = MO_TargetIndex;
setIndex(Idx);
setOffset(Offset);
setTargetFlags(TargetFlags);
}
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
bool isKill, bool isDead, bool isUndef,
bool isDebug) {
MachineRegisterInfo *RegInfo = nullptr;
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent())
RegInfo = &MF->getRegInfo();
// If this operand is already a register operand, remove it from the
// register's use/def lists.
bool WasReg = isReg();
if (RegInfo && WasReg)
RegInfo->removeRegOperandFromUseList(this);
// Change this to a register and set the reg#.
OpKind = MO_Register;
SmallContents.RegNo = Reg;
SubReg_TargetFlags = 0;
IsDef = isDef;
IsImp = isImp;
IsKill = isKill;
IsDead = isDead;
IsUndef = isUndef;
IsInternalRead = false;
IsEarlyClobber = false;
IsDebug = isDebug;
// Ensure isOnRegUseList() returns false.
Contents.Reg.Prev = nullptr;
// Preserve the tie when the operand was already a register.
if (!WasReg)
TiedTo = 0;
// If this operand is embedded in a function, add the operand to the
// register's use/def list.
if (RegInfo)
RegInfo->addRegOperandToUseList(this);
}
/// isIdenticalTo - Return true if this operand is identical to the specified
/// operand. Note that this should stay in sync with the hash_value overload
/// below.
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
if (getType() != Other.getType() ||
getTargetFlags() != Other.getTargetFlags())
return false;
switch (getType()) {
case MachineOperand::MO_Register:
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
case MachineOperand::MO_CImmediate:
return getCImm() == Other.getCImm();
case MachineOperand::MO_FPImmediate:
return getFPImm() == Other.getFPImm();
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
return getIndex() == Other.getIndex();
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
case MachineOperand::MO_JumpTableIndex:
return getIndex() == Other.getIndex();
case MachineOperand::MO_GlobalAddress:
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
case MachineOperand::MO_ExternalSymbol:
return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
getOffset() == Other.getOffset();
case MachineOperand::MO_BlockAddress:
return getBlockAddress() == Other.getBlockAddress() &&
getOffset() == Other.getOffset();
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut: {
// Shallow compare of the two RegMasks
const uint32_t *RegMask = getRegMask();
const uint32_t *OtherRegMask = Other.getRegMask();
if (RegMask == OtherRegMask)
return true;
// Calculate the size of the RegMask
const MachineFunction *MF = getParent()->getMF();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
// Deep compare of the two RegMasks
return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
}
case MachineOperand::MO_MCSymbol:
return getMCSymbol() == Other.getMCSymbol();
case MachineOperand::MO_CFIIndex:
return getCFIIndex() == Other.getCFIIndex();
case MachineOperand::MO_Metadata:
return getMetadata() == Other.getMetadata();
case MachineOperand::MO_IntrinsicID:
return getIntrinsicID() == Other.getIntrinsicID();
case MachineOperand::MO_Predicate:
return getPredicate() == Other.getPredicate();
}
llvm_unreachable("Invalid machine operand type");
}
// Note: this must stay exactly in sync with isIdenticalTo above.
hash_code llvm::hash_value(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
// Register operands don't have target flags.
return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
case MachineOperand::MO_Immediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
case MachineOperand::MO_CImmediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
case MachineOperand::MO_FPImmediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
case MachineOperand::MO_MachineBasicBlock:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
case MachineOperand::MO_FrameIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
MO.getOffset());
case MachineOperand::MO_JumpTableIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
case MachineOperand::MO_ExternalSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
MO.getSymbolName());
case MachineOperand::MO_GlobalAddress:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
MO.getOffset());
case MachineOperand::MO_BlockAddress:
return hash_combine(MO.getType(), MO.getTargetFlags(),
MO.getBlockAddress(), MO.getOffset());
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
case MachineOperand::MO_Metadata:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
case MachineOperand::MO_MCSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
case MachineOperand::MO_CFIIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
case MachineOperand::MO_IntrinsicID:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
case MachineOperand::MO_Predicate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
}
llvm_unreachable("Invalid machine operand type");
}
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
ModuleSlotTracker DummyMST(nullptr);
print(OS, DummyMST, TRI, IntrinsicInfo);
}
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
switch (getType()) {
case MachineOperand::MO_Register:
OS << printReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isInternalRead() || isEarlyClobber() || isTied()) {
OS << '<';
bool NeedComma = false;
if (isDef()) {
if (NeedComma) OS << ',';
if (isEarlyClobber())
OS << "earlyclobber,";
if (isImplicit())
OS << "imp-";
OS << "def";
NeedComma = true;
// <def,read-undef> only makes sense when getSubReg() is set.
// Don't clutter the output otherwise.
if (isUndef() && getSubReg())
OS << ",read-undef";
} else if (isImplicit()) {
OS << "imp-use";
NeedComma = true;
}
if (isKill()) {
if (NeedComma) OS << ',';
OS << "kill";
NeedComma = true;
}
if (isDead()) {
if (NeedComma) OS << ',';
OS << "dead";
NeedComma = true;
}
if (isUndef() && isUse()) {
if (NeedComma) OS << ',';
OS << "undef";
NeedComma = true;
}
if (isInternalRead()) {
if (NeedComma) OS << ',';
OS << "internal";
NeedComma = true;
}
if (isTied()) {
if (NeedComma) OS << ',';
OS << "tied";
if (TiedTo != 15)
OS << unsigned(TiedTo - 1);
}
OS << '>';
}
break;
case MachineOperand::MO_Immediate:
OS << getImm();
break;
case MachineOperand::MO_CImmediate:
getCImm()->getValue().print(OS, false);
break;
case MachineOperand::MO_FPImmediate:
if (getFPImm()->getType()->isFloatTy()) {
OS << getFPImm()->getValueAPF().convertToFloat();
} else if (getFPImm()->getType()->isHalfTy()) {
APFloat APF = getFPImm()->getValueAPF();
bool Unused;
APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
OS << "half " << APF.convertToFloat();
} else if (getFPImm()->getType()->isFP128Ty()) {
APFloat APF = getFPImm()->getValueAPF();
SmallString<16> Str;
getFPImm()->getValueAPF().toString(Str);
OS << "quad " << Str;
} else if (getFPImm()->getType()->isX86_FP80Ty()) {
APFloat APF = getFPImm()->getValueAPF();
OS << "x86_fp80 0xK";
APInt API = APF.bitcastToAPInt();
OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
/*Upper=*/true);
OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
/*Upper=*/true);
} else {
OS << getFPImm()->getValueAPF().convertToDouble();
}
break;
case MachineOperand::MO_MachineBasicBlock:
OS << "<BB#" << getMBB()->getNumber() << ">";
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << getIndex() << '>';
break;
case MachineOperand::MO_ConstantPoolIndex:
OS << "<cp#" << getIndex();
if (getOffset()) OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_TargetIndex:
OS << "<ti#" << getIndex();
if (getOffset()) OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_JumpTableIndex:
OS << "<jt#" << getIndex() << '>';
break;
case MachineOperand::MO_GlobalAddress:
OS << "<ga:";
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
if (getOffset()) OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_ExternalSymbol:
OS << "<es:" << getSymbolName();
if (getOffset()) OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_BlockAddress:
OS << '<';
getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
if (getOffset()) OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_RegisterMask: {
unsigned NumRegsInMask = 0;
unsigned NumRegsEmitted = 0;
OS << "<regmask";
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
unsigned MaskWord = i / 32;
unsigned MaskBit = i % 32;
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintRegMaskNumRegs < 0 ||
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
OS << " " << printReg(i, TRI);
NumRegsEmitted++;
}
NumRegsInMask++;
}
}
if (NumRegsEmitted != NumRegsInMask)
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
OS << ">";
break;
}
case MachineOperand::MO_RegisterLiveOut:
OS << "<regliveout>";
break;
case MachineOperand::MO_Metadata:
OS << '<';
getMetadata()->printAsOperand(OS, MST);
OS << '>';
break;
case MachineOperand::MO_MCSymbol:
OS << "<MCSym=" << *getMCSymbol() << '>';
break;
case MachineOperand::MO_CFIIndex:
OS << "<call frame instruction>";
break;
case MachineOperand::MO_IntrinsicID: {
Intrinsic::ID ID = getIntrinsicID();
if (ID < Intrinsic::num_intrinsics)
OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
else if (IntrinsicInfo)
OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
else
OS << "<intrinsic:" << ID << '>';
break;
}
case MachineOperand::MO_Predicate: {
auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
<< CmpInst::getPredicateName(Pred) << '>';
break;
}
}
if (unsigned TF = getTargetFlags())
OS << "[TF=" << TF << ']';
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void MachineOperand::dump() const {
dbgs() << *this << '\n';
}
#endif
//===----------------------------------------------------------------------===//
// MachineMemOperand Implementation
//===----------------------------------------------------------------------===//
/// getAddrSpace - Return the LLVM IR address space number that this pointer
/// points into.
unsigned MachinePointerInfo::getAddrSpace() const {
if (V.isNull()) return 0;
if (V.is<const PseudoSourceValue*>())
return V.get<const PseudoSourceValue*>()->getAddressSpace();
return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
}
/// isDereferenceable - Return true if V is always dereferenceable for
/// Offset + Size byte.
bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
const DataLayout &DL) const {
if (!V.is<const Value*>())
return false;
const Value *BasePtr = V.get<const Value*>();
if (BasePtr == nullptr)
return false;
return isDereferenceableAndAlignedPointer(
BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
}
/// getConstantPool - Return a MachinePointerInfo record that refers to the
/// constant pool.
MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getConstantPool());
}
/// getFixedStack - Return a MachinePointerInfo record that refers to the
/// the specified FrameIndex.
MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
int FI, int64_t Offset) {
return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
}
MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getJumpTable());
}
MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getGOT());
}
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
int64_t Offset,
uint8_t ID) {
return MachinePointerInfo(MF.getPSVManager().getStack(), Offset,ID);
}
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
uint64_t s, unsigned int a,
const AAMDNodes &AAInfo,
const MDNode *Ranges,
SyncScope::ID SSID,
AtomicOrdering Ordering,
AtomicOrdering FailureOrdering)
: PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
AAInfo(AAInfo), Ranges(Ranges) {
assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
"invalid pointer value");
assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
assert((isLoad() || isStore()) && "Not a load/store!");
AtomicInfo.SSID = static_cast<unsigned>(SSID);
assert(getSyncScopeID() == SSID && "Value truncated");
AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
assert(getOrdering() == Ordering && "Value truncated");
AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
assert(getFailureOrdering() == FailureOrdering && "Value truncated");
}
/// Profile - Gather unique data for the object.
///
void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
ID.AddInteger(getOffset());
ID.AddInteger(Size);
ID.AddPointer(getOpaqueValue());
ID.AddInteger(getFlags());
ID.AddInteger(getBaseAlignment());
}
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
// The Value and Offset may differ due to CSE. But the flags and size
// should be the same.
assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
assert(MMO->getSize() == getSize() && "Size mismatch!");
if (MMO->getBaseAlignment() >= getBaseAlignment()) {
// Update the alignment value.
BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
// Also update the base and offset, because the new alignment may
// not be applicable with the old ones.
PtrInfo = MMO->PtrInfo;
}
}
/// getAlignment - Return the minimum known alignment in bytes of the
/// actual memory reference.
uint64_t MachineMemOperand::getAlignment() const {
return MinAlign(getBaseAlignment(), getOffset());
}
void MachineMemOperand::print(raw_ostream &OS) const {
ModuleSlotTracker DummyMST(nullptr);
print(OS, DummyMST);
}
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
assert((isLoad() || isStore()) &&
"SV has to be a load, store or both.");
if (isVolatile())
OS << "Volatile ";
if (isLoad())
OS << "LD";
if (isStore())
OS << "ST";
OS << getSize();
// Print the address information.
OS << "[";
if (const Value *V = getValue())
V->printAsOperand(OS, /*PrintType=*/false, MST);
else if (const PseudoSourceValue *PSV = getPseudoValue())
PSV->printCustom(OS);
else
OS << "<unknown>";
unsigned AS = getAddrSpace();
if (AS != 0)
OS << "(addrspace=" << AS << ')';
// If the alignment of the memory reference itself differs from the alignment
// of the base pointer, print the base alignment explicitly, next to the base
// pointer.
if (getBaseAlignment() != getAlignment())
OS << "(align=" << getBaseAlignment() << ")";
if (getOffset() != 0)
OS << "+" << getOffset();
OS << "]";
// Print the alignment of the reference.
if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
OS << "(align=" << getAlignment() << ")";
// Print TBAA info.
if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
OS << "(tbaa=";
if (TBAAInfo->getNumOperands() > 0)
TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
else
OS << "<unknown>";
OS << ")";
}
// Print AA scope info.
if (const MDNode *ScopeInfo = getAAInfo().Scope) {
OS << "(alias.scope=";
if (ScopeInfo->getNumOperands() > 0)
for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
if (i != ie-1)
OS << ",";
}
else
OS << "<unknown>";
OS << ")";
}
// Print AA noalias scope info.
if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
OS << "(noalias=";
if (NoAliasInfo->getNumOperands() > 0)
for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
if (i != ie-1)
OS << ",";
}
else
OS << "<unknown>";
OS << ")";
}
if (const MDNode *Ranges = getRanges()) {
unsigned NumRanges = Ranges->getNumOperands();
if (NumRanges != 0) {
OS << "(ranges=";
for (unsigned I = 0; I != NumRanges; ++I) {
Ranges->getOperand(I)->printAsOperand(OS, MST);
if (I != NumRanges - 1)
OS << ',';
}
OS << ')';
}
}
if (isNonTemporal())
OS << "(nontemporal)";
if (isDereferenceable())
OS << "(dereferenceable)";
if (isInvariant())
OS << "(invariant)";
if (getFlags() & MOTargetFlag1)
OS << "(flag1)";
if (getFlags() & MOTargetFlag2)
OS << "(flag2)";
if (getFlags() & MOTargetFlag3)
OS << "(flag3)";
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MachineInstr Implementation // MachineInstr Implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
if (MCID->ImplicitDefs) if (MCID->ImplicitDefs)
for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
++ImpDefs) ++ImpDefs)
▲ Show 20 Lines • Show All 1,658 Lines • Show Last 20 Lines

lib/CodeGen/MachineOperand.cpp

  • This file was added.
//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Methods common to all machine operands.
MatzeBUnsubmitted
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Use /// \file ... so doxygen can pick it up.

MatzeB: Use `/// \file ...` so doxygen can pick it up.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/Analysis/Loads.h"
#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/ModuleSlotTracker.h"
using namespace llvm;
static cl::opt<int>
PrintRegMaskNumRegs("print-regmask-num-regs",
cl::desc("Number of registers to limit to when "
"printing regmask operands in IR dumps. "
"unlimited = -1"),
cl::init(32), cl::Hidden);
//===----------------------------------------------------------------------===//
// MachineOperand Implementation
//===----------------------------------------------------------------------===//
MatzeBUnsubmitted
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This is unnecessary now as the whole file is about MachineOperand.

MatzeB: This is unnecessary now as the whole file is about MachineOperand.
void MachineOperand::setReg(unsigned Reg) {
if (getReg() == Reg)
return; // No change.
// Otherwise, we have to change the register. If this operand is embedded
// into a machine function, we need to update the old and new register's
// use/def lists.
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent()) {
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.removeRegOperandFromUseList(this);
SmallContents.RegNo = Reg;
MRI.addRegOperandToUseList(this);
return;
}
// Otherwise, just change the register, no problem. :)
SmallContents.RegNo = Reg;
}
void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
const TargetRegisterInfo &TRI) {
assert(TargetRegisterInfo::isVirtualRegister(Reg));
if (SubIdx && getSubReg())
SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
setReg(Reg);
if (SubIdx)
setSubReg(SubIdx);
}
void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
if (getSubReg()) {
Reg = TRI.getSubReg(Reg, getSubReg());
// Note that getSubReg() may return 0 if the sub-register doesn't exist.
// That won't happen in legal code.
setSubReg(0);
if (isDef())
setIsUndef(false);
}
setReg(Reg);
}
/// Change a def to a use, or a use to a def.
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Done
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As we are on it: Would be good to move the doxygen comments from the implementation to the header where possible.

MatzeB: As we are on it: Would be good to move the doxygen comments from the implementation to the…
void MachineOperand::setIsDef(bool Val) {
assert(isReg() && "Wrong MachineOperand accessor");
assert((!Val || !isDebug()) && "Marking a debug operation as def");
if (IsDef == Val)
return;
// MRI may keep uses and defs in different list positions.
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent()) {
MachineRegisterInfo &MRI = MF->getRegInfo();
MRI.removeRegOperandFromUseList(this);
IsDef = Val;
MRI.addRegOperandToUseList(this);
return;
}
IsDef = Val;
}
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
void MachineOperand::removeRegFromUses() {
if (!isReg() || !isOnRegUseList())
return;
if (MachineInstr *MI = getParent()) {
if (MachineBasicBlock *MBB = MI->getParent()) {
if (MachineFunction *MF = MBB->getParent())
MF->getRegInfo().removeRegOperandFromUseList(this);
}
}
}
/// ChangeToImmediate - Replace this operand with a new immediate operand of
/// the specified value. If an operand is known to be an immediate already,
/// the setImm method should be used.
MatzeBUnsubmitted
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In cases where we have a doxygen comment in the implementation and the declaration we should just remove it from the implementation.

MatzeB: In cases where we have a doxygen comment in the implementation and the declaration we should…
void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
removeRegFromUses();
OpKind = MO_Immediate;
Contents.ImmVal = ImmVal;
}
void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
removeRegFromUses();
OpKind = MO_FPImmediate;
Contents.CFP = FPImm;
}
void MachineOperand::ChangeToES(const char *SymName,
unsigned char TargetFlags) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into an external symbol");
removeRegFromUses();
OpKind = MO_ExternalSymbol;
Contents.OffsetedInfo.Val.SymbolName = SymName;
setOffset(0); // Offset is always 0.
setTargetFlags(TargetFlags);
}
void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into an MCSymbol");
removeRegFromUses();
OpKind = MO_MCSymbol;
Contents.Sym = Sym;
}
void MachineOperand::ChangeToFrameIndex(int Idx) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into a FrameIndex");
removeRegFromUses();
OpKind = MO_FrameIndex;
setIndex(Idx);
}
void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
unsigned char TargetFlags) {
assert((!isReg() || !isTied()) &&
"Cannot change a tied operand into a FrameIndex");
removeRegFromUses();
OpKind = MO_TargetIndex;
setIndex(Idx);
setOffset(Offset);
setTargetFlags(TargetFlags);
}
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
bool isKill, bool isDead, bool isUndef,
bool isDebug) {
MachineRegisterInfo *RegInfo = nullptr;
if (MachineInstr *MI = getParent())
if (MachineBasicBlock *MBB = MI->getParent())
if (MachineFunction *MF = MBB->getParent())
RegInfo = &MF->getRegInfo();
// If this operand is already a register operand, remove it from the
// register's use/def lists.
bool WasReg = isReg();
if (RegInfo && WasReg)
RegInfo->removeRegOperandFromUseList(this);
// Change this to a register and set the reg#.
OpKind = MO_Register;
SmallContents.RegNo = Reg;
SubReg_TargetFlags = 0;
IsDef = isDef;
IsImp = isImp;
IsKill = isKill;
IsDead = isDead;
IsUndef = isUndef;
IsInternalRead = false;
IsEarlyClobber = false;
IsDebug = isDebug;
// Ensure isOnRegUseList() returns false.
Contents.Reg.Prev = nullptr;
// Preserve the tie when the operand was already a register.
if (!WasReg)
TiedTo = 0;
// If this operand is embedded in a function, add the operand to the
// register's use/def list.
if (RegInfo)
RegInfo->addRegOperandToUseList(this);
}
/// isIdenticalTo - Return true if this operand is identical to the specified
/// operand. Note that this should stay in sync with the hash_value overload
/// below.
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
if (getType() != Other.getType() ||
getTargetFlags() != Other.getTargetFlags())
return false;
switch (getType()) {
case MachineOperand::MO_Register:
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
case MachineOperand::MO_CImmediate:
return getCImm() == Other.getCImm();
case MachineOperand::MO_FPImmediate:
return getFPImm() == Other.getFPImm();
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
return getIndex() == Other.getIndex();
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
case MachineOperand::MO_JumpTableIndex:
return getIndex() == Other.getIndex();
case MachineOperand::MO_GlobalAddress:
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
case MachineOperand::MO_ExternalSymbol:
return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
getOffset() == Other.getOffset();
case MachineOperand::MO_BlockAddress:
return getBlockAddress() == Other.getBlockAddress() &&
getOffset() == Other.getOffset();
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut: {
// Shallow compare of the two RegMasks
const uint32_t *RegMask = getRegMask();
const uint32_t *OtherRegMask = Other.getRegMask();
if (RegMask == OtherRegMask)
return true;
// Calculate the size of the RegMask
const MachineFunction *MF = getParent()->getMF();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
// Deep compare of the two RegMasks
return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
}
case MachineOperand::MO_MCSymbol:
return getMCSymbol() == Other.getMCSymbol();
case MachineOperand::MO_CFIIndex:
return getCFIIndex() == Other.getCFIIndex();
case MachineOperand::MO_Metadata:
return getMetadata() == Other.getMetadata();
case MachineOperand::MO_IntrinsicID:
return getIntrinsicID() == Other.getIntrinsicID();
case MachineOperand::MO_Predicate:
return getPredicate() == Other.getPredicate();
}
llvm_unreachable("Invalid machine operand type");
}
// Note: this must stay exactly in sync with isIdenticalTo above.
hash_code llvm::hash_value(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
// Register operands don't have target flags.
return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
case MachineOperand::MO_Immediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
case MachineOperand::MO_CImmediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
case MachineOperand::MO_FPImmediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
case MachineOperand::MO_MachineBasicBlock:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
case MachineOperand::MO_FrameIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
MO.getOffset());
case MachineOperand::MO_JumpTableIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
case MachineOperand::MO_ExternalSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
MO.getSymbolName());
case MachineOperand::MO_GlobalAddress:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
MO.getOffset());
case MachineOperand::MO_BlockAddress:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
MO.getOffset());
case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
case MachineOperand::MO_Metadata:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
case MachineOperand::MO_MCSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
case MachineOperand::MO_CFIIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
case MachineOperand::MO_IntrinsicID:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
case MachineOperand::MO_Predicate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
}
llvm_unreachable("Invalid machine operand type");
}
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
ModuleSlotTracker DummyMST(nullptr);
print(OS, DummyMST, TRI, IntrinsicInfo);
}
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
switch (getType()) {
case MachineOperand::MO_Register:
OS << printReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isInternalRead() || isEarlyClobber() || isTied()) {
OS << '<';
bool NeedComma = false;
if (isDef()) {
if (NeedComma)
OS << ',';
if (isEarlyClobber())
OS << "earlyclobber,";
if (isImplicit())
OS << "imp-";
OS << "def";
NeedComma = true;
// <def,read-undef> only makes sense when getSubReg() is set.
// Don't clutter the output otherwise.
if (isUndef() && getSubReg())
OS << ",read-undef";
} else if (isImplicit()) {
OS << "imp-use";
NeedComma = true;
}
if (isKill()) {
if (NeedComma)
OS << ',';
OS << "kill";
NeedComma = true;
}
if (isDead()) {
if (NeedComma)
OS << ',';
OS << "dead";
NeedComma = true;
}
if (isUndef() && isUse()) {
if (NeedComma)
OS << ',';
OS << "undef";
NeedComma = true;
}
if (isInternalRead()) {
if (NeedComma)
OS << ',';
OS << "internal";
NeedComma = true;
}
if (isTied()) {
if (NeedComma)
OS << ',';
OS << "tied";
if (TiedTo != 15)
OS << unsigned(TiedTo - 1);
}
OS << '>';
}
break;
case MachineOperand::MO_Immediate:
OS << getImm();
break;
case MachineOperand::MO_CImmediate:
getCImm()->getValue().print(OS, false);
break;
case MachineOperand::MO_FPImmediate:
if (getFPImm()->getType()->isFloatTy()) {
OS << getFPImm()->getValueAPF().convertToFloat();
} else if (getFPImm()->getType()->isHalfTy()) {
APFloat APF = getFPImm()->getValueAPF();
bool Unused;
APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
OS << "half " << APF.convertToFloat();
} else if (getFPImm()->getType()->isFP128Ty()) {
APFloat APF = getFPImm()->getValueAPF();
SmallString<16> Str;
getFPImm()->getValueAPF().toString(Str);
OS << "quad " << Str;
} else if (getFPImm()->getType()->isX86_FP80Ty()) {
APFloat APF = getFPImm()->getValueAPF();
OS << "x86_fp80 0xK";
APInt API = APF.bitcastToAPInt();
OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
/*Upper=*/true);
OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
/*Upper=*/true);
} else {
OS << getFPImm()->getValueAPF().convertToDouble();
}
break;
case MachineOperand::MO_MachineBasicBlock:
OS << "<BB#" << getMBB()->getNumber() << ">";
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << getIndex() << '>';
break;
case MachineOperand::MO_ConstantPoolIndex:
OS << "<cp#" << getIndex();
if (getOffset())
OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_TargetIndex:
OS << "<ti#" << getIndex();
if (getOffset())
OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_JumpTableIndex:
OS << "<jt#" << getIndex() << '>';
break;
case MachineOperand::MO_GlobalAddress:
OS << "<ga:";
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
if (getOffset())
OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_ExternalSymbol:
OS << "<es:" << getSymbolName();
if (getOffset())
OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_BlockAddress:
OS << '<';
getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
if (getOffset())
OS << "+" << getOffset();
OS << '>';
break;
case MachineOperand::MO_RegisterMask: {
unsigned NumRegsInMask = 0;
unsigned NumRegsEmitted = 0;
OS << "<regmask";
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
unsigned MaskWord = i / 32;
unsigned MaskBit = i % 32;
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintRegMaskNumRegs < 0 ||
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
OS << " " << printReg(i, TRI);
NumRegsEmitted++;
}
NumRegsInMask++;
}
}
if (NumRegsEmitted != NumRegsInMask)
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
OS << ">";
break;
}
case MachineOperand::MO_RegisterLiveOut:
OS << "<regliveout>";
break;
case MachineOperand::MO_Metadata:
OS << '<';
getMetadata()->printAsOperand(OS, MST);
OS << '>';
break;
case MachineOperand::MO_MCSymbol:
OS << "<MCSym=" << *getMCSymbol() << '>';
break;
case MachineOperand::MO_CFIIndex:
OS << "<call frame instruction>";
break;
case MachineOperand::MO_IntrinsicID: {
Intrinsic::ID ID = getIntrinsicID();
if (ID < Intrinsic::num_intrinsics)
OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
else if (IntrinsicInfo)
OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
else
OS << "<intrinsic:" << ID << '>';
break;
}
case MachineOperand::MO_Predicate: {
auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
<< CmpInst::getPredicateName(Pred) << '>';
break;
}
}
if (unsigned TF = getTargetFlags())
OS << "[TF=" << TF << ']';
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
#endif
//===----------------------------------------------------------------------===//
// MachineMemOperand Implementation
//===----------------------------------------------------------------------===//
/// getAddrSpace - Return the LLVM IR address space number that this pointer
/// points into.
unsigned MachinePointerInfo::getAddrSpace() const {
if (V.isNull())
return 0;
if (V.is<const PseudoSourceValue *>())
return V.get<const PseudoSourceValue *>()->getAddressSpace();
return cast<PointerType>(V.get<const Value *>()->getType())
->getAddressSpace();
}
/// isDereferenceable - Return true if V is always dereferenceable for
/// Offset + Size byte.
bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
const DataLayout &DL) const {
if (!V.is<const Value *>())
return false;
const Value *BasePtr = V.get<const Value *>();
if (BasePtr == nullptr)
return false;
return isDereferenceableAndAlignedPointer(
BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
}
/// getConstantPool - Return a MachinePointerInfo record that refers to the
/// constant pool.
MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getConstantPool());
}
/// getFixedStack - Return a MachinePointerInfo record that refers to the
/// the specified FrameIndex.
MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
int FI, int64_t Offset) {
return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
}
MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getJumpTable());
}
MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
return MachinePointerInfo(MF.getPSVManager().getGOT());
}
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
int64_t Offset, uint8_t ID) {
return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
}
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
uint64_t s, unsigned int a,
const AAMDNodes &AAInfo,
const MDNode *Ranges, SyncScope::ID SSID,
AtomicOrdering Ordering,
AtomicOrdering FailureOrdering)
: PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
AAInfo(AAInfo), Ranges(Ranges) {
assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
"invalid pointer value");
assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
assert((isLoad() || isStore()) && "Not a load/store!");
AtomicInfo.SSID = static_cast<unsigned>(SSID);
assert(getSyncScopeID() == SSID && "Value truncated");
AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
assert(getOrdering() == Ordering && "Value truncated");
AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
assert(getFailureOrdering() == FailureOrdering && "Value truncated");
}
/// Profile - Gather unique data for the object.
///
void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
ID.AddInteger(getOffset());
ID.AddInteger(Size);
ID.AddPointer(getOpaqueValue());
ID.AddInteger(getFlags());
ID.AddInteger(getBaseAlignment());
}
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
// The Value and Offset may differ due to CSE. But the flags and size
// should be the same.
assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
assert(MMO->getSize() == getSize() && "Size mismatch!");
if (MMO->getBaseAlignment() >= getBaseAlignment()) {
// Update the alignment value.
BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
// Also update the base and offset, because the new alignment may
// not be applicable with the old ones.
PtrInfo = MMO->PtrInfo;
}
}
/// getAlignment - Return the minimum known alignment in bytes of the
/// actual memory reference.
uint64_t MachineMemOperand::getAlignment() const {
return MinAlign(getBaseAlignment(), getOffset());
}
void MachineMemOperand::print(raw_ostream &OS) const {
ModuleSlotTracker DummyMST(nullptr);
print(OS, DummyMST);
}
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
assert((isLoad() || isStore()) && "SV has to be a load, store or both.");
if (isVolatile())
OS << "Volatile ";
if (isLoad())
OS << "LD";
if (isStore())
OS << "ST";
OS << getSize();
// Print the address information.
OS << "[";
if (const Value *V = getValue())
V->printAsOperand(OS, /*PrintType=*/false, MST);
else if (const PseudoSourceValue *PSV = getPseudoValue())
PSV->printCustom(OS);
else
OS << "<unknown>";
unsigned AS = getAddrSpace();
if (AS != 0)
OS << "(addrspace=" << AS << ')';
// If the alignment of the memory reference itself differs from the alignment
// of the base pointer, print the base alignment explicitly, next to the base
// pointer.
if (getBaseAlignment() != getAlignment())
OS << "(align=" << getBaseAlignment() << ")";
if (getOffset() != 0)
OS << "+" << getOffset();
OS << "]";
// Print the alignment of the reference.
if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
OS << "(align=" << getAlignment() << ")";
// Print TBAA info.
if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
OS << "(tbaa=";
if (TBAAInfo->getNumOperands() > 0)
TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
else
OS << "<unknown>";
OS << ")";
}
// Print AA scope info.
if (const MDNode *ScopeInfo = getAAInfo().Scope) {
OS << "(alias.scope=";
if (ScopeInfo->getNumOperands() > 0)
for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
if (i != ie - 1)
OS << ",";
}
else
OS << "<unknown>";
OS << ")";
}
// Print AA noalias scope info.
if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
OS << "(noalias=";
if (NoAliasInfo->getNumOperands() > 0)
for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
if (i != ie - 1)
OS << ",";
}
else
OS << "<unknown>";
OS << ")";
}
if (const MDNode *Ranges = getRanges()) {
unsigned NumRanges = Ranges->getNumOperands();
if (NumRanges != 0) {
OS << "(ranges=";
for (unsigned I = 0; I != NumRanges; ++I) {
Ranges->getOperand(I)->printAsOperand(OS, MST);
if (I != NumRanges - 1)
OS << ',';
}
OS << ')';
}
}
if (isNonTemporal())
OS << "(nontemporal)";
if (isDereferenceable())
OS << "(dereferenceable)";
if (isInvariant())
OS << "(invariant)";
if (getFlags() & MOTargetFlag1)
OS << "(flag1)";
if (getFlags() & MOTargetFlag2)
OS << "(flag2)";
if (getFlags() & MOTargetFlag3)
OS << "(flag3)";
}