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Differential D4007

Add floating point extension from float to double
AbandonedPublic

Authored by rkotler on Jun 3 2014, 1:37 PM.

Details

Reviewers
dsanders
Summary

This will allow extensiosn of 32 to 64 bit floating point.

Diff Detail

Event Timeline

rkotler updated this revision to Diff 10058.Jun 3 2014, 1:37 PM
rkotler retitled this revision from to Add floating point extension from float to double.
rkotler updated this object.
rkotler edited the test plan for this revision. (Show Details)
rkotler added a reviewer: dsanders.
rkotler added a comment.Jun 3 2014, 4:50 PM

fpext.c109 BDownload

rkotler added a parent revision: D3984: Add sign/zero extend.Jun 19 2014, 7:38 AM
rkotler updated this revision to Diff 10636.Jun 19 2014, 8:22 AM
  • Merge branch '1758_9a' into 1758_10a
  • add test case
Herald added a subscriber: mcrosier. · View Herald TranscriptJun 19 2014, 8:22 AM
mcrosier removed a subscriber: mcrosier.Jul 7 2014, 7:25 PM
rkotler abandoned this revision.Nov 12 2014, 4:22 PM

Revision Contents

PathSize
lib/
Target/
Mips/
129 lines
test/
CodeGen/
Mips/
Fast-ISel/
21 lines
166 lines

Diff 10636

lib/Target/Mips/MipsFastISel.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
private: private:
bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment = 0); unsigned Alignment = 0);
bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr, bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
unsigned Alignment = 0); unsigned Alignment = 0);
bool SelectLoad(const Instruction *I); bool SelectLoad(const Instruction *I);
bool SelectRet(const Instruction *I); bool SelectRet(const Instruction *I);
bool SelectStore(const Instruction *I); bool SelectStore(const Instruction *I);
bool SelectIntExt(const Instruction *I);
bool SelectTrunc(const Instruction *I);
bool SelectFPExt(const Instruction *I);
bool isTypeLegal(Type *Ty, MVT &VT); bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT); bool isLoadTypeLegal(Type *Ty, MVT &VT);
unsigned MaterializeFP(const ConstantFP *CFP, MVT VT); unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
unsigned MaterializeGV(const GlobalValue *GV, MVT VT); unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
unsigned MaterializeInt(const Constant *C, MVT VT); unsigned MaterializeInt(const Constant *C, MVT VT);
unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC); unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
// for some reason, this default is not generated by tablegen // for some reason, this default is not generated by tablegen
// so we explicitly generate it here. // so we explicitly generate it here.
// //
unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill, uint64_t imm1, unsigned Op0, bool Op0IsKill, uint64_t imm1,
uint64_t imm2, unsigned Op3, bool Op3IsKill) { uint64_t imm2, unsigned Op3, bool Op3IsKill) {
return 0; return 0;
} }
MachineInstrBuilder EmitInst(unsigned Opc) { MachineInstrBuilder EmitInst(unsigned Opc) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)); return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
} }
MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) { MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
DstReg); DstReg);
} }
MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg, MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
unsigned MemReg, int64_t MemOffset) { unsigned MemReg, int64_t MemOffset) {
return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
} }
MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg, MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
unsigned MemReg, int64_t MemOffset) { unsigned MemReg, int64_t MemOffset) {
return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
} }
#include "MipsGenFastISel.inc" #include "MipsGenFastISel.inc"
}; };
bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
EVT evt = TLI.getValueType(Ty, true); EVT evt = TLI.getValueType(Ty, true);
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines case MVT::f64:
break; break;
default: default:
return false; return false;
} }
EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset); EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
return true; return true;
} }
bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
return false;
switch (SrcVT.SimpleTy) {
default:
return false;
case MVT::i8:
EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
break;
case MVT::i16:
EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
break;
}
return true;
}
bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
switch (SrcVT.SimpleTy) {
default:
return false;
case MVT::i1:
EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
break;
case MVT::i8:
EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
break;
case MVT::i16:
EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
break;
}
return true;
}
bool MipsFastISel::SelectLoad(const Instruction *I) { bool MipsFastISel::SelectLoad(const Instruction *I) {
// Atomic loads need special handling. // Atomic loads need special handling.
if (cast<LoadInst>(I)->isAtomic()) if (cast<LoadInst>(I)->isAtomic())
return false; return false;
// Verify we have a legal type before going any further. // Verify we have a legal type before going any further.
MVT VT; MVT VT;
if (!isLoadTypeLegal(I->getType(), VT)) if (!isLoadTypeLegal(I->getType(), VT))
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines if (!FuncInfo.CanLowerReturn)
return false; return false;
if (Ret->getNumOperands() > 0) { if (Ret->getNumOperands() > 0) {
return false; return false;
} }
EmitInst(Mips::RetRA); EmitInst(Mips::RetRA);
return true; return true;
} }
// Attempt to fast-select a floating-point extend instruction.
bool MipsFastISel::SelectFPExt(const Instruction *I) {
Value *Src = I->getOperand(0);
EVT SrcVT = TLI.getValueType(Src->getType(), true);
EVT DestVT = TLI.getValueType(I->getType(), true);
if (SrcVT != MVT::f32 || DestVT != MVT::f64)
return false;
unsigned SrcReg =
getRegForValue(Src); // his must be a 32 bit floating point register class
// maybe we should handle this differently
if (!SrcReg)
return false;
unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
EmitInst(Mips::CVT_D_S_MM, DestReg).addReg(SrcReg);
UpdateValueMap(I, DestReg);
return true;
}
bool MipsFastISel::SelectIntExt(const Instruction *I) {
Type *DestTy = I->getType();
Value *Src = I->getOperand(0);
Type *SrcTy = Src->getType();
bool isZExt = isa<ZExtInst>(I);
unsigned SrcReg = getRegForValue(Src);
if (!SrcReg)
return false;
EVT SrcEVT, DestEVT;
SrcEVT = TLI.getValueType(SrcTy, true);
DestEVT = TLI.getValueType(DestTy, true);
if (!SrcEVT.isSimple())
return false;
if (!DestEVT.isSimple())
return false;
MVT SrcVT = SrcEVT.getSimpleVT();
MVT DestVT = DestEVT.getSimpleVT();
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
if (isZExt) {
if (!EmitIntZExt(SrcVT, SrcReg, DestVT, ResultReg))
return false;
} else {
if (!EmitIntSExt(SrcVT, SrcReg, DestVT, ResultReg))
return false;
}
UpdateValueMap(I, ResultReg);
return true;
}
bool MipsFastISel::SelectTrunc(const Instruction *I) {
// The high bits for a type smaller than the register size are assumed to be
// undefined.
Value *Op = I->getOperand(0);
EVT SrcVT, DestVT;
SrcVT = TLI.getValueType(Op->getType(), true);
DestVT = TLI.getValueType(I->getType(), true);
if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
return false;
if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
return false;
unsigned SrcReg = getRegForValue(Op);
if (!SrcReg)
return false;
// Because the high bits are undefined, a truncate doesn't generate
// any code.
UpdateValueMap(I, SrcReg);
return true;
}
bool MipsFastISel::TargetSelectInstruction(const Instruction *I) { bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
if (!TargetSupported) if (!TargetSupported)
return false; return false;
switch (I->getOpcode()) { switch (I->getOpcode()) {
default: default:
break; break;
case Instruction::Load: case Instruction::Load:
return SelectLoad(I); return SelectLoad(I);
case Instruction::Store: case Instruction::Store:
return SelectStore(I); return SelectStore(I);
case Instruction::Ret: case Instruction::Ret:
return SelectRet(I); return SelectRet(I);
case Instruction::Trunc:
return SelectTrunc(I);
case Instruction::ZExt:
case Instruction::SExt:
return SelectIntExt(I);
case Instruction::FPExt:
return SelectFPExt(I);
} }
return false; return false;
} }
} }
unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
if (VT == MVT::f32) { if (VT == MVT::f32) {
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

test/CodeGen/Mips/Fast-ISel/fpext.ll

  • This file was added.
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
@f = global float 0x40147E6B80000000, align 4
@d_f = common global double 0.000000e+00, align 8
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind
define void @dv() #0 {
entry:
%0 = load float* @f, align 4
%conv = fpext float %0 to double
; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
store double %conv, double* @d_f, align 8
ret void
}
attributes #1 = { nounwind }

test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

  • This file was added.
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
@b2 = global i8 0, align 1
@b1 = global i8 1, align 1
@uc1 = global i8 0, align 1
@uc2 = global i8 -1, align 1
@sc1 = global i8 -128, align 1
@sc2 = global i8 127, align 1
@ss1 = global i16 -32768, align 2
@ss2 = global i16 32767, align 2
@us1 = global i16 0, align 2
@us2 = global i16 -1, align 2
@ssi = global i16 0, align 2
@ssj = global i16 0, align 2
@i = global i32 0, align 4
@j = global i32 0, align 4
@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
; Function Attrs: nounwind
define void @_Z3b_iv() #0 {
entry:
; CHECK: .ent _Z3b_iv
%0 = load i8* @b1, align 1
%tobool = trunc i8 %0 to i1
%frombool = zext i1 %tobool to i8
store i8 %frombool, i8* @b2, align 1
%1 = load i8* @b2, align 1
%tobool1 = trunc i8 %1 to i1
%conv = zext i1 %tobool1 to i32
store i32 %conv, i32* @i, align 4
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 1
; CHECK: sb ${{[0-9]+}}, 0(${{[0-9]+}})
ret void
; CHECK: .end _Z3b_iv
}
; Function Attrs: nounwind
define void @_Z4uc_iv() #0 {
entry:
; CHECK: .ent _Z4uc_iv
%0 = load i8* @uc1, align 1
%conv = zext i8 %0 to i32
store i32 %conv, i32* @i, align 4
%1 = load i8* @uc2, align 1
%conv1 = zext i8 %1 to i32
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 255
store i32 %conv1, i32* @j, align 4
ret void
; CHECK: .end _Z4uc_iv
}
; Function Attrs: nounwind
define void @_Z4sc_iv() #0 {
entry:
; CHECK: .ent _Z4sc_iv
%0 = load i8* @sc1, align 1
%conv = sext i8 %0 to i32
store i32 %conv, i32* @i, align 4
%1 = load i8* @sc2, align 1
%conv1 = sext i8 %1 to i32
store i32 %conv1, i32* @j, align 4
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: seb ${{[0-9]+}}, ${{[0-9]+}}
ret void
; CHECK: .end _Z4sc_iv
}
; Function Attrs: nounwind
define void @_Z4us_iv() #0 {
entry:
; CHECK: .ent _Z4us_iv
%0 = load i16* @us1, align 2
%conv = zext i16 %0 to i32
store i32 %conv, i32* @i, align 4
%1 = load i16* @us2, align 2
%conv1 = zext i16 %1 to i32
store i32 %conv1, i32* @j, align 4
ret void
; CHECK: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 65535
; CHECK: .end _Z4us_iv
}
; Function Attrs: nounwind
define void @_Z4ss_iv() #0 {
entry:
; CHECK: .ent _Z4ss_iv
%0 = load i16* @ss1, align 2
%conv = sext i16 %0 to i32
store i32 %conv, i32* @i, align 4
%1 = load i16* @ss2, align 2
%conv1 = sext i16 %1 to i32
store i32 %conv1, i32* @j, align 4
; CHECK: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: seh ${{[0-9]+}}, ${{[0-9]+}}
ret void
; CHECK: .end _Z4ss_iv
}
; Function Attrs: nounwind
define void @_Z4b_ssv() #0 {
entry:
; CHECK: .ent _Z4b_ssv
%0 = load i8* @b2, align 1
%tobool = trunc i8 %0 to i1
%conv = zext i1 %tobool to i16
store i16 %conv, i16* @ssi, align 2
ret void
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 1
; CHECK: .end _Z4b_ssv
}
; Function Attrs: nounwind
define void @_Z5uc_ssv() #0 {
entry:
; CHECK: .ent _Z5uc_ssv
%0 = load i8* @uc1, align 1
%conv = zext i8 %0 to i16
store i16 %conv, i16* @ssi, align 2
%1 = load i8* @uc2, align 1
%conv1 = zext i8 %1 to i16
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 255
store i16 %conv1, i16* @ssj, align 2
ret void
; CHECK: .end _Z5uc_ssv
}
; Function Attrs: nounwind
define void @_Z5sc_ssv() #0 {
entry:
; CHECK: .ent _Z5sc_ssv
%0 = load i8* @sc1, align 1
%conv = sext i8 %0 to i16
store i16 %conv, i16* @ssi, align 2
%1 = load i8* @sc2, align 1
%conv1 = sext i8 %1 to i16
store i16 %conv1, i16* @ssj, align 2
; CHECK: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; CHECK: seb ${{[0-9]+}}, ${{[0-9]+}}
ret void
; CHECK: .end _Z5sc_ssv
}
declare i32 @printf(i8*, ...) #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }