[mips] Guard indirect and tailcall pseudo instructions correctly.

[sdardis]

Summary

Previously these pseudo instructions were not guarded by ISA, so their
select was dependant on the ordering of the entries in the DAG matcher.

[atanasyan]

LGTM

lib/Target/Mips/MicroMips32r6InstrInfo.td

def : MipsPat<(not GPR32:$in),
               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
 // Patterns for load with a reg+imm operand.
 let AddedComplexity = 41 in {
   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
 }
 
 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
+              (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
+              (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
+

lib/Target/Mips/MicroMipsInstrInfo.td

def : MipsPat<(store GPR32:$src, addr:$addr),
                 (SW_MM GPR32:$src, addr:$addr)>;
 
   def : MipsPat<(load addrimm4lsl2:$addr),
                 (LW16_MM addrimm4lsl2:$addr)>;
   def : MipsPat<(load addr:$addr),
                 (LW_MM addr:$addr)>;
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
                 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
+}
 
-  def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
-                (TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
-  def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
-                (TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
-}
+              (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
+              (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
 let AddedComplexity = 40 in {
   def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
                 (LH_MM addrRegImm:$a)>;
 }
 def : MipsPat<(atomic_load_16 addr:$a),
               (LH_MM addr:$a)>;
 def : MipsPat<(i32 (extloadi16 addr:$src)),

lib/Target/Mips/MipsInstrInfo.td

 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"!FeatureMips64r6">;
 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
+def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
+                      AssemblerPredicate<"!FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
 def NotCnMips    :    Predicate<"!Subtarget->hasCnMips()">,
                       AssemblerPredicate<"!FeatureCnMips">;
 def IsSym32     :     Predicate<"Subtarget->HasSym32()">,
                       AssemblerPredicate<"FeatureSym32">;
 def IsSym64     :     Predicate<"!Subtarget->HasSym32()">,
                       AssemblerPredicate<"!FeatureSym32">;

 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
     hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
   class TailCall<Instruction JumpInst, DAGOperand Opnd> :
     PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
     PseudoInstExpansion<(JumpInst Opnd:$target)>;
 
   class TailCallReg<RegisterOperand RO> :
-    MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
+    PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
 }
 
 class BAL_BR_Pseudo<Instruction RealInst> :
   PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
   PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
   let isBranch = 1;
   let isTerminator = 1;
   let isBarrier = 1;

 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
               BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
              ISA_MIPS1_NOT_32R6_64R6;
 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
               BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
 
-let Predicates = [NotInMicroMips] in { 
+let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
   def TAILCALL : TailCall<J, jmptarget>;
 }
 
 def TAILCALLREG : TailCallReg<GPR32Opnd>;
 
 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
 class PseudoIndirectBranchBase<RegisterOperand RO> :
     MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
                II_IndirectBranchPseudo> {
   let isTerminator=1;
   let isBarrier=1;
   let hasDelaySlot = 1;
   let isBranch = 1;
   let isIndirectBranch = 1;
   bit isCTI = 1;
+  let Predicates = [NotInMips16Mode];
 }
 
 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
 
 // Return instructions are matched as a RetRA instruction, then are expanded
 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
 // ISA.

 
 // Call
 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
               (JAL texternalsym:$dst)>;
 //def : MipsPat<(MipsJmpLink GPR32:$dst),
 //              (JALR GPR32:$dst)>;
 
 // Tail call
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
                 (TAILCALL tglobaladdr:$dst)>;
   def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
                 (TAILCALL texternalsym:$dst)>;
+}
 // hi/lo relocs
 multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
                           Register ZeroReg, RegisterOperand GPROpnd> {
   def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>;
   def : MipsPat<(MipsHi tblockaddress:$in), (Lui tblockaddress:$in)>;
   def : MipsPat<(MipsHi tjumptable:$in), (Lui tjumptable:$in)>;
   def : MipsPat<(MipsHi tconstpool:$in), (Lui tconstpool:$in)>;
   def : MipsPat<(MipsHi tglobaltlsaddr:$in), (Lui tglobaltlsaddr:$in)>;

test/CodeGen/Mips/brind-tailcall.ll

+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
+; RUN:   -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s
+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s
+; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
+; RUN:   -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s
+; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s
+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
+; RUN:   -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
+; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
+; RUN:   -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
+; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=pic    -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
+; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1  \
+; RUN:   -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
+
+; REQUIRES: asserts
+
+; Test that the correct pseudo instructions are generated for indirect
+; branches and tail calls. Previously, the order of the DAG matcher table
+; determined if the correct instruction was selected for mips16.
+
+declare protected void @a()
+
+define void @test1(i32 %a) {
+entry:
+  %0 = trunc i32 %a to i1
+  %1 = select i1 %0,
+              i8* blockaddress(@test1, %bb),
+              i8* blockaddress(@test1, %bb6)
+  indirectbr i8* %1, [label %bb, label %bb6]
+
+; STATIC:     PseudoIndirectBranch
+; STATIC-MM:  PseudoIndirectBranch
+; STATIC-NOT: PseudoIndirectBranch64
+; STATIC64:   PseudoIndirectBranch64
+; PIC:        PseudoIndirectBranch
+; PIC-NOT:    PseudoIndirectBranch64
+; PIC64:      PseudoIndirectBranch64
+; MIPS16:     JrcRx16
+bb:
+  ret void
+
+bb6:
+  tail call void @a()
+
+; STATIC:     TAILCALL
+; STATIC-NOT: TAILCALL_MM
+; STATIC-MM:  TAILCALL_MM
+; PIC:        TAILCALLREG
+; PIC-NOT:    TAILCALLREG64
+; PIC64:      TAILCALLREG64
+; MIPS16:     RetRA16
+  ret void
+}

test/CodeGen/Mips/tailcall/tailcall.ll

 ; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r2  \
 ; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64
 ; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6  \
 ; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
 
 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
 ; RUN:      -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
-; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
+; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
 ; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
 ; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
 ; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
 ; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
 @g2 = common global i32 0, align 4
 @g3 = common global i32 0, align 4
 @g4 = common global i32 0, align 4
 @g5 = common global i32 0, align 4
 @g6 = common global i32 0, align 4
 @g7 = common global i32 0, align 4
 @g8 = common global i32 0, align 4
 @g9 = common global i32 0, align 4
 
 define i32 @caller1(i32 %a0) nounwind {
 entry:
 ; ALL-LABEL: caller1:
 ; PIC32: jalr $25
 ; PIC32MM: jalr $25
 ; PIC32R6: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee1(i32 1, i32 1, i32 1, i32 %a0) nounwind
   ret i32 %call
 }
 
 declare i32 @callee1(i32, i32, i32, i32)
 
 define i32 @caller2(i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {
 entry:
 ; ALL-LABEL: caller2
 ; PIC32: jalr $25
 ; PIC32MM: jalr $25
 ; PIC32R6: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee2(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind
   ret i32 %call
 }
 
 declare i32 @callee2(i32, i32, i32, i32, i32)
 
 define i32 @caller3(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind {
 entry:
 ; ALL-LABEL: caller3:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee3(i32 1, i32 1, i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind
   ret i32 %call
 }
 
 declare i32 @callee3(i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller4(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind {
 entry:
 ; ALL-LABEL: caller4:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; SATATIC32MMR6: jal
 ; PIC64: jalr $25
 ; STATIC64: jal
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee4(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee4(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller5() nounwind readonly {
 entry:
 ; ALL-LABEL: caller5:
 ; PIC32: jr $25
 ; PIC32R6: jr $25
 ; PIC32MM: jr
 ; STATIC32: j
+; STATIC32MMR6: bc
 ; PIC64: jr $25
 ; STATIC64: j
 ; PIC16: jalrc
 
   %0 = load i32, i32* @g0, align 4
   %1 = load i32, i32* @g1, align 4
   %2 = load i32, i32* @g2, align 4
   %3 = load i32, i32* @g3, align 4

 
 define i32 @caller8_0() nounwind {
 entry:
 ; ALL-LABEL: caller8_0:
 ; PIC32: jr $25
 ; PIC32R6: jrc $25
 ; PIC32MM: jrc
 ; STATIC32: j
+; STATIC32MMR6: bc
 ; PIC64: jr $25
 ; PIC64R6: jrc $25
 ; PIC64R6MM: jr $25
 ; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call fastcc i32 @caller8_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller8_1() nounwind noinline {
 entry:
 ; ALL-LABEL: caller8_1:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; PIC64: jalr $25
 ; STATIC64: jal
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
   ret i32 %call
 }
 
 %struct.S = type { [2 x i32] }
 
 @gs1 = external global %struct.S
 
 declare i32 @callee9(%struct.S* byval)
 
 define i32 @caller9_0() nounwind {
 entry:
 ; ALL-LABEL: caller9_0:
 ; PIC32: jr $25
 ; PIC32R6: jrc $25
 ; PIC32MM: jrc
 ; STATIC32: j
+; STATIC32MMR6: bc
 ; PIC64: jr $25
 ; STATIC64: j
 ; PIC64R6: jrc $25
 ; PIC16: jalrc
   %call = tail call fastcc i32 @caller9_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller9_1() nounwind noinline {
 entry:
 ; ALL-LABEL: caller9_1:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee10(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller10(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) nounwind {
 entry:
 ; ALL-LABEL: caller10:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee11(%struct.S* byval)
 
 define i32 @caller11() nounwind noinline {
 entry:
 ; ALL-LABEL: caller11:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee12()
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
 define i32 @caller12(%struct.S* nocapture byval %a0) nounwind {
 entry:
 ; ALL-LABEL: caller12:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %0 = bitcast %struct.S* %a0 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast (%struct.S* @gs1 to i8*), i8* %0, i32 8, i32 4, i1 false)
   %call = tail call i32 @callee12() nounwind
   ret i32 %call
 }
 
 declare i32 @callee13(i32, ...)
 
 define i32 @caller13() nounwind {
 entry:
 ; ALL-LABEL: caller13:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
+; STATIC32MMR6: jal
 ; STATIC64: jal
 ; PIC64R6: jalr $25
 ; PIC64: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
   ret i32 %call
 }