This is an archive of the discontinued LLVM Phabricator instance.

Differential D39495

[mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
ClosedPublic

Authored by sdardis on Nov 1 2017, 9:33 AM.

Details

Reviewers
atanasyan
Commits
rG169df4e24b2d: [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
rL317475: [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
Summary

Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encoded for
microMIPS32r6, so this patch provides the correct encoding.

Secondly, correct the encoding of the 'rs' and 'rt' operands which have
an instruction specific encoding for the registers those operands accept.

Finally, correct the decoding of the 'dst_regs' operand which was extracting
the relevant field from the instruction, but was actually extracting the
field from the alreadly extracted field.

Diff Detail

Event Timeline

sdardis created this revision.Nov 1 2017, 9:33 AM
Herald added a subscriber: arichardson. · View Herald TranscriptNov 1 2017, 9:33 AM
atanasyan accepted this revision.Nov 4 2017, 2:10 AM

LGTM

This revision is now accepted and ready to land.Nov 4 2017, 2:10 AM
Closed by commit rL317475: [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version (authored by sdardis). · Explain WhyNov 6 2017, 5:00 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
6 lines
MCTargetDesc/
3 lines
23 lines
15 lines
4 lines
3 lines
1 line
1 line
test/
MC/
Disassembler/
Mips/
micromips32r3/
1 line
1 line
micromips32r6/
2 lines
micromips64r6/
2 lines
Mips/
micromips32r6/
2 lines
micromips64r6/
2 lines

Diff 121142

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 529 Lines • ▼ Show 20 Lines
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
namespace llvm { namespace llvm {
Target &getTheMipselTarget(); Target &getTheMipselTarget();
Target &getTheMipsTarget(); Target &getTheMipsTarget();
Target &getTheMips64Target(); Target &getTheMips64Target();
▲ Show 20 Lines • Show All 1,929 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
for (unsigned i = 0; i <= RegNum; i++) for (unsigned i = 0; i <= RegNum; i++)
Inst.addOperand(MCOperand::createReg(Regs[i])); Inst.addOperand(MCOperand::createReg(Regs[i]));
Inst.addOperand(MCOperand::createReg(Mips::RA)); Inst.addOperand(MCOperand::createReg(Mips::RA));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
switch (RegPair) { switch (RegPair) {
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
case 0: case 0:
Inst.addOperand(MCOperand::createReg(Mips::A1)); Inst.addOperand(MCOperand::createReg(Mips::A1));
Inst.addOperand(MCOperand::createReg(Mips::A2)); Inst.addOperand(MCOperand::createReg(Mips::A2));
break; break;
case 1: case 1:
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Linespublic:
unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
Show All 15 Lines

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Show First 20 Lines • Show All 1,109 Lines • ▼ Show 20 LinesMipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
else if (MI.getOperand(0).getReg() == Mips::A0 && else if (MI.getOperand(0).getReg() == Mips::A0 &&
MI.getOperand(1).getReg() == Mips::A3) MI.getOperand(1).getReg() == Mips::A3)
res = 7; res = 7;
return res; return res;
} }
unsigned unsigned
MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(((OpNo == 2) || (OpNo == 3)) &&
"Unexpected OpNo for movep operand encoding!");
MCOperand Op = MI.getOperand(OpNo);
assert(Op.isReg() && "Operand of movep is not a register!");
switch (Op.getReg()) {
default:
llvm_unreachable("Unknown register for movep!");
case Mips::ZERO: return 0;
case Mips::S1: return 1;
case Mips::V0: return 2;
case Mips::V1: return 3;
case Mips::S0: return 4;
case Mips::S2: return 5;
case Mips::S3: return 6;
case Mips::S4: return 7;
}
}
unsigned
MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate"); assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
// The immediate is encoded as 'immediate >> 2'. // The immediate is encoded as 'immediate >> 2'.
unsigned Res = static_cast<unsigned>(MO.getImm()); unsigned Res = static_cast<unsigned>(MO.getImm());
assert((Res & 3) == 0); assert((Res & 3) == 0);
return Res >> 2; return Res >> 2;
} }
#include "MipsGenMCCodeEmitter.inc" #include "MipsGenMCCodeEmitter.inc"

lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 823 Lines • ▼ Show 20 Linesclass POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
bits<16> Inst; bits<16> Inst;
let Inst{15-10} = 0x11; let Inst{15-10} = 0x11;
let Inst{9-7} = rt; let Inst{9-7} = rt;
let Inst{6-4} = rs; let Inst{6-4} = rs;
let Inst{3-0} = 0b0000; let Inst{3-0} = 0b0000;
} }
class POOL16C_MOVEP16_FM_MMR6 : MicroMipsR6Inst16 {
bits<3> dst_regs;
bits<3> rt;
bits<3> rs;
bits<16> Inst;
let Inst{15-10} = 0b010001;
let Inst{9-7} = dst_regs;
let Inst{6-4} = rt;
let Inst{3} = rs{2};
let Inst{2} = 0b1;
let Inst{1-0} = rs{1-0};
}
class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 { class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
bits<3> rt; bits<3> rt;
bits<3> rs; bits<3> rs;
bits<16> Inst; bits<16> Inst;
let Inst{15-10} = 0b010001; let Inst{15-10} = 0b010001;
let Inst{9-7} = rt; let Inst{9-7} = rt;
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 223 Lines • ▼ Show 20 Lines
class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16; class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6; class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>; class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16; class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16; class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16; class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
class MOVEP_MMR6_ENC : POOL16C_MOVEP16_FM_MMR6;
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>; class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>; class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>; class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
▲ Show 20 Lines • Show All 959 Lines • ▼ Show 20 Lines
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
MMR6Arch<"srl16">; MMR6Arch<"srl16">;
class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">, class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">,
MicroMipsR6Inst16; MicroMipsR6Inst16;
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove; MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">, class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
MicroMipsR6Inst16; MicroMipsR6Inst16;
class MOVEP_MMR6_DESC :MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">;
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">, class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
MicroMipsR6Inst16; MicroMipsR6Inst16;
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
MMR6Arch<"subu16">, MicroMipsR6Inst16 { MMR6Arch<"subu16">, MicroMipsR6Inst16 {
int AddedComplexity = 1; int AddedComplexity = 1;
} }
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
MMR6Arch<"xor16"> { MMR6Arch<"xor16"> {
▲ Show 20 Lines • Show All 459 Lines • ▼ Show 20 Lines
def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC, def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC, def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC, def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC, def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MOVEP_MMR6 : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
ISA_MICROMIPS32R6;
def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC, def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC, def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 192 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 625 Lines • ▼ Show 20 Linesdef SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
LOAD_STORE_SP_FM_MM16<0x32>; LOAD_STORE_SP_FM_MM16<0x32>;
def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16; def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>; def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16; def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
ISA_MICROMIPS_NOT_32R6_64R6;
def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16, def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
IsAsCheapAsAMove; IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>, def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>; def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>; def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>; def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>; def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
▲ Show 20 Lines • Show All 540 Lines • Show Last 20 Lines

lib/Target/Mips/MipsRegisterInfo.td

Show First 20 Lines • Show All 610 Lines • ▼ Show 20 Lines
} }
def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> { def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
let ParserMatchClass = GPRMM16AsmOperandZero; let ParserMatchClass = GPRMM16AsmOperandZero;
} }
def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> { def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
let ParserMatchClass = GPRMM16AsmOperandMoveP; let ParserMatchClass = GPRMM16AsmOperandMoveP;
let EncoderMethod = "getMovePRegSingleOpValue";
} }
def GPR64Opnd : RegisterOperand<GPR64> { def GPR64Opnd : RegisterOperand<GPR64> {
let ParserMatchClass = GPR64AsmOperand; let ParserMatchClass = GPR64AsmOperand;
} }
def DSPROpnd : RegisterOperand<DSPR> { def DSPROpnd : RegisterOperand<DSPR> {
let ParserMatchClass = GPR32AsmOperand; let ParserMatchClass = GPR32AsmOperand;
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

lib/Target/Mips/MipsScheduleGeneric.td

Show First 20 Lines • Show All 730 Lines • ▼ Show 20 Lines
def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>;
def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>;
def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>; def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>;
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show All 21 Lines
0x12 0x6a # CHECK: lw16 $4, 8($17) 0x12 0x6a # CHECK: lw16 $4, 8($17)
0x84 0x89 # CHECK: sb16 $3, 4($16) 0x84 0x89 # CHECK: sb16 $3, 4($16)
0x14 0xaa # CHECK: sh16 $4, 8($17) 0x14 0xaa # CHECK: sh16 $4, 8($17)
0x11 0xea # CHECK: sw16 $4, 4($17) 0x11 0xea # CHECK: sw16 $4, 4($17)
0x11 0xe8 # CHECK: sw16 $zero, 4($17) 0x11 0xe8 # CHECK: sw16 $zero, 4($17)
0x09 0x46 # CHECK: mfhi $9 0x09 0x46 # CHECK: mfhi $9
0x49 0x46 # CHECK: mflo $9 0x49 0x46 # CHECK: mflo $9
0x21 0x0f # CHECK: move $25, $1 0x21 0x0f # CHECK: move $25, $1
0x9a 0x85 # CHECK: movep $4, $21, $18, $17
0xa9 0x45 # CHECK: jrc $9 0xa9 0x45 # CHECK: jrc $9
0xc9 0x45 # CHECK: jalr $9 0xc9 0x45 # CHECK: jalr $9
0xe9 0x45 # CHECK: jalrs16 $9 0xe9 0x45 # CHECK: jalrs16 $9
0x89 0x45 # CHECK: jr16 $9 0x89 0x45 # CHECK: jr16 $9
0xff 0xed # CHECK: li16 $3, -1 0xff 0xed # CHECK: li16 $3, -1
0xfe 0xed # CHECK: li16 $3, 126 0xfe 0xed # CHECK: li16 $3, 126
0x83 0x6f # CHECK: addiur1sp $7, 4 0x83 0x6f # CHECK: addiur1sp $7, 4
0x7e 0x6f # CHECK: addiur2 $6, $7, -1 0x7e 0x6f # CHECK: addiur2 $6, $7, -1
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show All 21 Lines
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x89 0x84 # CHECK: sb16 $3, 4($16) 0x89 0x84 # CHECK: sb16 $3, 4($16)
0xaa 0x14 # CHECK: sh16 $4, 8($17) 0xaa 0x14 # CHECK: sh16 $4, 8($17)
0xea 0x11 # CHECK: sw16 $4, 4($17) 0xea 0x11 # CHECK: sw16 $4, 4($17)
0xe8 0x11 # CHECK: sw16 $zero, 4($17) 0xe8 0x11 # CHECK: sw16 $zero, 4($17)
0x46 0x09 # CHECK: mfhi $9 0x46 0x09 # CHECK: mfhi $9
0x46 0x49 # CHECK: mflo $9 0x46 0x49 # CHECK: mflo $9
0x0f 0x21 # CHECK: move $25, $1 0x0f 0x21 # CHECK: move $25, $1
0x85 0x9a # CHECK: movep $4, $21, $18, $17
0x45 0xa9 # CHECK: jrc $9 0x45 0xa9 # CHECK: jrc $9
0x45 0xc9 # CHECK: jalr $9 0x45 0xc9 # CHECK: jalr $9
0x45 0xe9 # CHECK: jalrs16 $9 0x45 0xe9 # CHECK: jalrs16 $9
0x45 0x89 # CHECK: jr16 $9 0x45 0x89 # CHECK: jr16 $9
0xed 0xff # CHECK: li16 $3, -1 0xed 0xff # CHECK: li16 $3, -1
0xed 0xfe # CHECK: li16 $3, 126 0xed 0xfe # CHECK: li16 $3, 126
0x6f 0x83 # CHECK: addiur1sp $7, 4 0x6f 0x83 # CHECK: addiur1sp $7, 4
0x6f 0x7e # CHECK: addiur2 $6, $7, -1 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
▲ Show 20 Lines • Show All 172 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show All 15 Lines
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x65 0x88 # CHECK: lw $3, 32($gp) 0x65 0x88 # CHECK: lw $3, 32($gp)
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x84 0x34 # CHECK: movep $5, $6, $2, $3 0x44 0x36 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4 0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2 0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8 0x2e 0x56 # CHECK: andi16 $4, $5, 8
0x46 0x70 # CHECK: not16 $4, $7 0x46 0x70 # CHECK: not16 $4, $7
0x45 0xf9 # CHECK: or16 $3, $7 0x45 0xf9 # CHECK: or16 $3, $7
0x25 0xe0 # CHECK: sll16 $3, $6, 8 0x25 0xe0 # CHECK: sll16 $3, $6, 8
0x25 0xe1 # CHECK: srl16 $3, $6, 8 0x25 0xe1 # CHECK: srl16 $3, $6, 8
0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
▲ Show 20 Lines • Show All 321 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show All 17 Lines
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x45 0x2b # CHECK: jalr $9 0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x84 0x34 # CHECK: movep $5, $6, $2, $3 0x44 0x36 # CHECK: movep $5, $6, $2, $3
0x45 0xf9 # CHECK: or16 $3, $7 0x45 0xf9 # CHECK: or16 $3, $7
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) 0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4) 0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27) 0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7 0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7 0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4) 0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4) 0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
▲ Show 20 Lines • Show All 290 Lines • Show Last 20 Lines

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40] lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08] lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08] lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34] movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0] rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90]
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

test/MC/Mips/micromips64r6/valid.s

Show All 29 Linesa:
dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x50] dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x58,0x85,0x20,0x50]
ldpc $2, 16 # CHECK: ldpc $2, 16 # encoding: [0x78,0x58,0x00,0x02] ldpc $2, 16 # CHECK: ldpc $2, 16 # encoding: [0x78,0x58,0x00,0x02]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66] lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12] lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82] lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34] movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
not16 $4, $7 # CHECK: not16 $4, $7 # encoding: [0x46,0x70] not16 $4, $7 # CHECK: not16 $4, $7 # encoding: [0x46,0x70]
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9] or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40] lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
▲ Show 20 Lines • Show All 304 Lines • Show Last 20 Lines