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Differential D39222

[InstCombine] Pull shifts through a select plus binop with constant
ClosedPublic

Authored by craig.topper on Oct 23 2017, 8:18 PM.

Details

Reviewers
spatel
davide
majnemer
Commits
rG7dd4d3243175: Recommit r317510 "[InstCombine] Pull shifts through a select plus binop with…
rG89176473336a: [InstCombine] Pull shifts through a select plus binop with constant
rL317600: Recommit r317510 "[InstCombine] Pull shifts through a select plus binop with…
rL317510: [InstCombine] Pull shifts through a select plus binop with constant
Summary

This pulls shifts through a select+binop with a constant where the select conditionally executes the binop. We already do this for just the binop, but not with the select.

This can allow us to get the select closer to other selects to enable removing one.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Oct 23 2017, 8:18 PM
craig.topper added reviewers: spatel, davide, majnemer.Oct 23 2017, 8:19 PM
craig.topper added a subscriber: llvm-commits.
craig.topper added a comment.Oct 30 2017, 11:05 AM

Ping

spatel added inline comments.Nov 6 2017, 9:29 AM
lib/Transforms/InstCombine/InstCombineShifts.cpp
318–320 ↗(On Diff #119996)

Since we're moving this, we might as well fix the formatting - capitalize variables.

539–544 ↗(On Diff #119996)

Use matchers to reduce the number of if-checks and indenting?

CmpInst::Predicate P;
BinaryOperator *TVI;
Value *FalseVal;
if (match(Op0, m_Select(P, m_OneUse(m_BinOp(TVI)), m_Value(FalseVal))) ...
craig.topper updated this revision to Diff 121758.Nov 6 2017, 10:57 AM

Address Sanjay's comments.

spatel accepted this revision.Nov 6 2017, 11:25 AM

LGTM. See inline for a couple of other minor bits.

lib/Transforms/InstCombine/InstCombineShifts.cpp
537–538 ↗(On Diff #121758)
// If we have a select that conditionally executes some binary operator,
// see if we can pull the shift and binop ahead of the select.

This would be clearer if we copied one of the test patterns in the comment as an example of this transform.

545–547 ↗(On Diff #121758)

More && clauses? Could combine these ifs.

This revision is now accepted and ready to land.Nov 6 2017, 11:25 AM
Closed by commit rL317510: [InstCombine] Pull shifts through a select plus binop with constant (authored by ctopper). · Explain WhyNov 6 2017, 1:08 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Transforms/
InstCombine/
109 lines
test/
Transforms/
InstCombine/
260 lines

Diff 121774

llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp

Show First 20 Lines • Show All 304 Lines • ▼ Show 20 Lines case Instruction::PHI: {
for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
PN->setIncomingValue(i, getShiftedValue(PN->getIncomingValue(i), NumBits, PN->setIncomingValue(i, getShiftedValue(PN->getIncomingValue(i), NumBits,
isLeftShift, IC, DL)); isLeftShift, IC, DL));
return PN; return PN;
} }
} }
} }
// If this is a bitwise operator or add with a constant RHS we might be able
// to pull it through a shift.
static bool canShiftBinOpWithConstantRHS(BinaryOperator &Shift,
BinaryOperator *BO,
const APInt &C) {
bool IsValid = true; // Valid only for And, Or Xor,
bool HighBitSet = false; // Transform ifhigh bit of constant set?
switch (BO->getOpcode()) {
default: IsValid = false; break; // Do not perform transform!
case Instruction::Add:
IsValid = Shift.getOpcode() == Instruction::Shl;
break;
case Instruction::Or:
case Instruction::Xor:
HighBitSet = false;
break;
case Instruction::And:
HighBitSet = true;
break;
}
// If this is a signed shift right, and the high bit is modified
// by the logical operation, do not perform the transformation.
// The HighBitSet boolean indicates the value of the high bit of
// the constant which would cause it to be modified for this
// operation.
//
if (IsValid && Shift.getOpcode() == Instruction::AShr)
IsValid = C.isNegative() == HighBitSet;
return IsValid;
}
Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
BinaryOperator &I) { BinaryOperator &I) {
bool isLeftShift = I.getOpcode() == Instruction::Shl; bool isLeftShift = I.getOpcode() == Instruction::Shl;
const APInt *Op1C; const APInt *Op1C;
if (!match(Op1, m_APInt(Op1C))) if (!match(Op1, m_APInt(Op1C)))
return nullptr; return nullptr;
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines if (BinaryOperator *Op0BO = dyn_cast<BinaryOperator>(Op0)) {
} }
} }
// If the operand is a bitwise operator with a constant RHS, and the // If the operand is a bitwise operator with a constant RHS, and the
// shift is the only use, we can pull it out of the shift. // shift is the only use, we can pull it out of the shift.
const APInt *Op0C; const APInt *Op0C;
if (match(Op0BO->getOperand(1), m_APInt(Op0C))) { if (match(Op0BO->getOperand(1), m_APInt(Op0C))) {
bool isValid = true; // Valid only for And, Or, Xor if (canShiftBinOpWithConstantRHS(I, Op0BO, *Op0C)) {
bool highBitSet = false; // Transform if high bit of constant set?
switch (Op0BO->getOpcode()) {
default: isValid = false; break; // Do not perform transform!
case Instruction::Add:
isValid = isLeftShift;
break;
case Instruction::Or:
case Instruction::Xor:
highBitSet = false;
break;
case Instruction::And:
highBitSet = true;
break;
}
// If this is a signed shift right, and the high bit is modified
// by the logical operation, do not perform the transformation.
// The highBitSet boolean indicates the value of the high bit of
// the constant which would cause it to be modified for this
// operation.
//
if (isValid && I.getOpcode() == Instruction::AShr)
isValid = Op0C->isNegative() == highBitSet;
if (isValid) {
Constant *NewRHS = ConstantExpr::get(I.getOpcode(), Constant *NewRHS = ConstantExpr::get(I.getOpcode(),
cast<Constant>(Op0BO->getOperand(1)), Op1); cast<Constant>(Op0BO->getOperand(1)), Op1);
Value *NewShift = Value *NewShift =
Builder.CreateBinOp(I.getOpcode(), Op0BO->getOperand(0), Op1); Builder.CreateBinOp(I.getOpcode(), Op0BO->getOperand(0), Op1);
NewShift->takeName(Op0BO); NewShift->takeName(Op0BO);
return BinaryOperator::Create(Op0BO->getOpcode(), NewShift, return BinaryOperator::Create(Op0BO->getOpcode(), NewShift,
Show All 10 Lines if (BinaryOperator *Op0BO = dyn_cast<BinaryOperator>(Op0)) {
cast<Constant>(Op0BO->getOperand(0)), Op1); cast<Constant>(Op0BO->getOperand(0)), Op1);
Value *NewShift = Builder.CreateShl(Op0BO->getOperand(1), Op1); Value *NewShift = Builder.CreateShl(Op0BO->getOperand(1), Op1);
NewShift->takeName(Op0BO); NewShift->takeName(Op0BO);
return BinaryOperator::CreateSub(NewRHS, NewShift); return BinaryOperator::CreateSub(NewRHS, NewShift);
} }
} }
// If we have a select that conditionally executes some binary operator,
// see if we can pull it the select and operator through the shift.
//
// For example, turning:
// shl (select C, (add X, C1), X), C2
// Into:
// Y = shl X, C2
// select C, (add Y, C1 << C2), Y
Value *Cond;
BinaryOperator *TBO;
Value *FalseVal;
if (match(Op0, m_Select(m_Value(Cond), m_OneUse(m_BinOp(TBO)),
m_Value(FalseVal)))) {
const APInt *C;
if (!isa<Constant>(FalseVal) && TBO->getOperand(0) == FalseVal &&
match(TBO->getOperand(1), m_APInt(C)) &&
canShiftBinOpWithConstantRHS(I, TBO, *C)) {
Constant *NewRHS = ConstantExpr::get(I.getOpcode(),
cast<Constant>(TBO->getOperand(1)), Op1);
Value *NewShift =
Builder.CreateBinOp(I.getOpcode(), FalseVal, Op1);
Value *NewOp = Builder.CreateBinOp(TBO->getOpcode(), NewShift,
NewRHS);
return SelectInst::Create(Cond, NewOp, NewShift);
}
}
BinaryOperator *FBO;
Value *TrueVal;
if (match(Op0, m_Select(m_Value(Cond), m_Value(TrueVal),
m_OneUse(m_BinOp(FBO))))) {
const APInt *C;
if (!isa<Constant>(TrueVal) && FBO->getOperand(0) == TrueVal &&
match(FBO->getOperand(1), m_APInt(C)) &&
canShiftBinOpWithConstantRHS(I, FBO, *C)) {
Constant *NewRHS = ConstantExpr::get(I.getOpcode(),
cast<Constant>(FBO->getOperand(1)), Op1);
Value *NewShift =
Builder.CreateBinOp(I.getOpcode(), TrueVal, Op1);
Value *NewOp = Builder.CreateBinOp(FBO->getOpcode(), NewShift,
NewRHS);
return SelectInst::Create(Cond, NewShift, NewOp);
}
}
} }
return nullptr; return nullptr;
} }
Instruction *InstCombiner::visitShl(BinaryOperator &I) { Instruction *InstCombiner::visitShl(BinaryOperator &I) {
if (Value *V = SimplifyVectorOp(I)) if (Value *V = SimplifyVectorOp(I))
return replaceInstUsesWith(I, V); return replaceInstUsesWith(I, V);
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

llvm/trunk/test/Transforms/InstCombine/shift.ll

Show First 20 Lines • Show All 1,326 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @test65( ; CHECK-LABEL: @test65(
; CHECK-NEXT: ret i7 0 ; CHECK-NEXT: ret i7 0
; ;
%shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width. %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width.
%x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit. %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit.
%y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0. %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0.
ret i7 %y ret i7 %y
} }
define i32 @shl_select_add_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_add_true(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = add i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @shl_select_add_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_add_false(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = add i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @shl_select_and_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_and_true(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @shl_select_and_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_and_false(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_and_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_and_true(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_and_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_and_false(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_and_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_and_true(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 2147483655
%2 = select i1 %cond, i32 %1, i32 %x
%3 = ashr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_and_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_and_false(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = and i32 %x, 2147483655
%2 = select i1 %cond, i32 %x, i32 %1
%3 = ashr i32 %2, 1
ret i32 %3
}
define i32 @shl_select_or_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_or_true(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @shl_select_or_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_or_false(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_or_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_or_true(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_or_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_or_false(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_or_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_or_true(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = ashr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_or_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_or_false(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = or i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = ashr i32 %2, 1
ret i32 %3
}
define i32 @shl_select_xor_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_xor_true(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @shl_select_xor_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @shl_select_xor_false(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = shl i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_xor_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_xor_true(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @lshr_select_xor_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @lshr_select_xor_false(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = lshr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_xor_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_xor_true(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %1, i32 %x
%3 = ashr i32 %2, 1
ret i32 %3
}
define i32 @ashr_select_xor_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @ashr_select_xor_false(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[TMP3]]
;
%1 = xor i32 %x, 7
%2 = select i1 %cond, i32 %x, i32 %1
%3 = ashr i32 %2, 1
ret i32 %3
}