[X86][SSE] Add extractps/pextrd equivalence to domain tables

[RKSimon]

Summary

There doesn't appear to be a shorter coding for the ps domain in this case

[craig.topper]

LGTM

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

static const uint16_t ReplaceableInstrs[][3] = {
   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
+  { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
+  { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
   // AVX 128-bit support
   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
static const uint16_t ReplaceableInstrs[][3] = {
   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
+  { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
+  { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
   // AVX 256-bit support
   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
static const uint16_t ReplaceableInstrs[][3] = {
   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
+  { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
+  { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
 };
 
 static const uint16_t ReplaceableInstrsAVX2[][3] = {
   //PackedSingle       PackedDouble       PackedInt
   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },

llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll

entry:
   %1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b
   store <2 x float> %1, <2 x float>* undef
   ret void
 }
 
 define void @zero_test() {
 ; X32-LABEL: zero_test:
 ; X32:       # BB#0: # %entry
-; X32-NEXT:    pxor %xmm0, %xmm0
-; X32-NEXT:    pextrd $1, %xmm0, (%eax)
-; X32-NEXT:    movd %xmm0, (%eax)
+; X32-NEXT:    xorps %xmm0, %xmm0
+; X32-NEXT:    extractps $1, %xmm0, (%eax)
+; X32-NEXT:    movss %xmm0, (%eax)
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: zero_test:
 ; X64:       # BB#0: # %entry
 ; X64-NEXT:    xorps %xmm0, %xmm0
 ; X64-NEXT:    movlps %xmm0, (%rax)
 ; X64-NEXT:    retq
 entry:

llvm/trunk/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown -mattr=-sse4.2,+sse4.1 < %s | FileCheck %s
 
 ; Make sure we don't load from the location pointed to by %p
 ; twice: it has non-obvious performance implications, and
 ; the relevant transformation doesn't know how to update
 ; the chains correctly.
 ; PR10747
 
 define <4 x i32> @test(<4 x i32>* %p) {
 ; CHECK-LABEL: test:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movdqa (%rdi), %xmm0
-; CHECK-NEXT:    pextrd $2, %xmm0, %eax
+; CHECK-NEXT:    movaps (%rdi), %xmm0
+; CHECK-NEXT:    extractps $2, %xmm0, %eax
 ; CHECK-NEXT:    cmpl $3, %eax
 ; CHECK-NEXT:    je .LBB0_2
 ; CHECK-NEXT:  # BB#1:
-; CHECK-NEXT:    pxor %xmm0, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    retq
   %v = load <4 x i32>, <4 x i32>* %p
   %e = extractelement <4 x i32> %v, i32 2
   %cmp = icmp eq i32 %e, 3
   %sel = select i1 %cmp, <4 x i32> %v, <4 x i32> zeroinitializer
   ret <4 x i32> %sel
 }

llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

; X64-NEXT:    retq
   %res = zext i16 %ext to i32
   ret i32 %res
 }
 
 define i32 @test_mm256_extract_epi32(<4 x i64> %a0) nounwind {
 ; X32-LABEL: test_mm256_extract_epi32:
 ; X32:       # BB#0:
 ; X32-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X32-NEXT:    vpextrd $1, %xmm0, %eax
+; X32-NEXT:    vextractps $1, %xmm0, %eax
 ; X32-NEXT:    vzeroupper
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_extract_epi32:
 ; X64:       # BB#0:
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X64-NEXT:    vpextrd $1, %xmm0, %eax
+; X64-NEXT:    vextractps $1, %xmm0, %eax
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
   %arg0 = bitcast <4 x i64> %a0 to <8 x i32>
   %res = extractelement <8 x i32> %arg0, i32 5
   ret i32 %res
 }
 
 define i64 @test_mm256_extract_epi64(<4 x i64> %a0) nounwind {
 ; X32-LABEL: test_mm256_extract_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X32-NEXT:    vpextrd $2, %xmm0, %eax
-; X32-NEXT:    vpextrd $3, %xmm0, %edx
+; X32-NEXT:    vextractps $2, %xmm0, %eax
+; X32-NEXT:    vextractps $3, %xmm0, %edx
 ; X32-NEXT:    vzeroupper
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_extract_epi64:
 ; X64:       # BB#0:
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; X64-NEXT:    vpextrq $1, %xmm0, %rax
 ; X64-NEXT:    vzeroupper

llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll

; CHECK-NEXT:    retq
   %r2 = extractelement <2 x i64> %x, i32 1
   store i64 %r2, i64* %dst, align 1
   ret i64 %r1
 }
 
 define i32 @extract_v16i32(<16 x i32> %x, i32* %dst) {
 ; CHECK-LABEL: extract_v16i32:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpextrd $1, %xmm0, %eax
-; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT:    vpextrd $1, %xmm0, (%rdi)
+; CHECK-NEXT:    vextractps $1, %xmm0, %eax
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vextractps $1, %xmm0, (%rdi)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %r1 = extractelement <16 x i32> %x, i32 1
   %r2 = extractelement <16 x i32> %x, i32 5
   store i32 %r2, i32* %dst, align 1
   ret i32 %r1
 }
 
 define i32 @extract_v8i32(<8 x i32> %x, i32* %dst) {
 ; CHECK-LABEL: extract_v8i32:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpextrd $1, %xmm0, %eax
-; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT:    vpextrd $1, %xmm0, (%rdi)
+; CHECK-NEXT:    vextractps $1, %xmm0, %eax
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vextractps $1, %xmm0, (%rdi)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %r1 = extractelement <8 x i32> %x, i32 1
   %r2 = extractelement <8 x i32> %x, i32 5
   store i32 %r2, i32* %dst, align 1
   ret i32 %r1
 }
 
 define i32 @extract_v4i32(<4 x i32> %x, i32* %dst) {
 ; CHECK-LABEL: extract_v4i32:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpextrd $1, %xmm0, %eax
-; CHECK-NEXT:    vpextrd $3, %xmm0, (%rdi)
+; CHECK-NEXT:    vextractps $1, %xmm0, %eax
+; CHECK-NEXT:    vextractps $3, %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
   %r1 = extractelement <4 x i32> %x, i32 1
   %r2 = extractelement <4 x i32> %x, i32 3
   store i32 %r2, i32* %dst, align 1
   ret i32 %r1
 }
 
 define i16 @extract_v32i16(<32 x i16> %x, i16* %dst) {

llvm/trunk/test/CodeGen/X86/extract-store.ll

 ; SSE2-X64:       # BB#0:
 ; SSE2-X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE2-X64-NEXT:    movd %xmm0, (%rdi)
 ; SSE2-X64-NEXT:    retq
 ;
 ; SSE41-X32-LABEL: extract_i32_3:
 ; SSE41-X32:       # BB#0:
 ; SSE41-X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; SSE41-X32-NEXT:    pextrd $3, %xmm0, (%eax)
+; SSE41-X32-NEXT:    extractps $3, %xmm0, (%eax)
 ; SSE41-X32-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: extract_i32_3:
 ; SSE41-X64:       # BB#0:
-; SSE41-X64-NEXT:    pextrd $3, %xmm0, (%rdi)
+; SSE41-X64-NEXT:    extractps $3, %xmm0, (%rdi)
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X32-LABEL: extract_i32_3:
 ; AVX-X32:       # BB#0:
 ; AVX-X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; AVX-X32-NEXT:    vpextrd $3, %xmm0, (%eax)
+; AVX-X32-NEXT:    vextractps $3, %xmm0, (%eax)
 ; AVX-X32-NEXT:    retl
 ;
 ; AVX-X64-LABEL: extract_i32_3:
 ; AVX-X64:       # BB#0:
-; AVX-X64-NEXT:    vpextrd $3, %xmm0, (%rdi)
+; AVX-X64-NEXT:    vextractps $3, %xmm0, (%rdi)
 ; AVX-X64-NEXT:    retq
 ;
 ; SSE-F128-LABEL: extract_i32_3:
 ; SSE-F128:       # BB#0:
 ; SSE-F128-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE-F128-NEXT:    movd %xmm0, (%rdi)
 ; SSE-F128-NEXT:    retq
   %vecext = extractelement <4 x i32> %foo, i32 3

llvm/trunk/test/CodeGen/X86/extractelement-index.ll

 ; SSE2-LABEL: extractelement_v4i32_3:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; SSE2-NEXT:    movd %xmm0, %eax
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: extractelement_v4i32_3:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pextrd $3, %xmm0, %eax
+; SSE41-NEXT:    extractps $3, %xmm0, %eax
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v4i32_3:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpextrd $3, %xmm0, %eax
+; AVX-NEXT:    vextractps $3, %xmm0, %eax
 ; AVX-NEXT:    retq
   %b = extractelement <4 x i32> %a, i256 3
   ret i32 %b
 }
 
 define i32 @extractelement_v8i32_0(<8 x i32> %a) nounwind {
 ; SSE-LABEL: extractelement_v8i32_0:
 ; SSE:       # BB#0:

 ; SSE2-LABEL: extractelement_v8i32_7:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[3,1,2,3]
 ; SSE2-NEXT:    movd %xmm0, %eax
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: extractelement_v8i32_7:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pextrd $3, %xmm1, %eax
+; SSE41-NEXT:    extractps $3, %xmm1, %eax
 ; SSE41-NEXT:    retq
 ;
-; AVX1-LABEL: extractelement_v8i32_7:
-; AVX1:       # BB#0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT:    vpextrd $3, %xmm0, %eax
-; AVX1-NEXT:    vzeroupper
-; AVX1-NEXT:    retq
-;
-; AVX2-LABEL: extractelement_v8i32_7:
-; AVX2:       # BB#0:
-; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
-; AVX2-NEXT:    vpextrd $3, %xmm0, %eax
-; AVX2-NEXT:    vzeroupper
-; AVX2-NEXT:    retq
+; AVX-LABEL: extractelement_v8i32_7:
+; AVX:       # BB#0:
+; AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX-NEXT:    vextractps $3, %xmm0, %eax
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
   %b = extractelement <8 x i32> %a, i64 7
   ret i32 %b
 }
 
 define i64 @extractelement_v2i64_0(<2 x i64> %a, i256 %i) nounwind {
 ; SSE-LABEL: extractelement_v2i64_0:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movq %xmm0, %rax

llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll

; X64-NEXT:    retq
   %9 = sitofp <4 x i64> %8 to <4 x float>
   ret <4 x float> %9
 }
 
 define float @signbits_ashr_extract_sitofp(<2 x i64> %a0) nounwind {
 ; X32-LABEL: signbits_ashr_extract_sitofp:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    vpextrd $1, %xmm0, %eax
+; X32-NEXT:    vextractps $1, %xmm0, %eax
 ; X32-NEXT:    vcvtsi2ssl %eax, %xmm1, %xmm0
 ; X32-NEXT:    vmovss %xmm0, (%esp)
 ; X32-NEXT:    flds (%esp)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: signbits_ashr_extract_sitofp:
 ; X64:       # BB#0:

llvm/trunk/test/CodeGen/X86/nontemporal-2.ll

 ; SSE4A:       # BB#0:
 ; SSE4A-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
 ; SSE4A-NEXT:    movd %xmm0, %eax
 ; SSE4A-NEXT:    movntil %eax, (%rdi)
 ; SSE4A-NEXT:    retq
 ;
 ; SSE41-LABEL: test_extract_i32:
 ; SSE41:       # BB#0:
-; SSE41-NEXT:    pextrd $1, %xmm0, %eax
+; SSE41-NEXT:    extractps $1, %xmm0, %eax
 ; SSE41-NEXT:    movntil %eax, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX-LABEL: test_extract_i32:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpextrd $1, %xmm0, %eax
+; AVX-NEXT:    vextractps $1, %xmm0, %eax
 ; AVX-NEXT:    movntil %eax, (%rdi)
 ; AVX-NEXT:    retq
 ;
 ; VLX-LABEL: test_extract_i32:
 ; VLX:       # BB#0:
-; VLX-NEXT:    vpextrd $1, %xmm0, %eax
+; VLX-NEXT:    vextractps $1, %xmm0, %eax
 ; VLX-NEXT:    movntil %eax, (%rdi)
 ; VLX-NEXT:    retq
   %1 = extractelement <4 x i32> %arg, i32 1
   store i32 %1, i32* %dst, align 1, !nontemporal !1
   ret void
 }
 
 define void @test_extract_f64(<2 x double> %arg, double* %dst) {

llvm/trunk/test/CodeGen/X86/oddshuffles.ll

 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
 ; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; AVX1-NEXT:    vpextrd $2, %xmm0, 8(%rdi)
 ; AVX1-NEXT:    vmovq %xmm1, (%rdi)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v3i32:
 ; AVX2:       # BB#0:
-; AVX2-NEXT:    vpbroadcastd %xmm1, %xmm1
-; AVX2-NEXT:    vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2,3]
-; AVX2-NEXT:    vpextrd $2, %xmm0, 8(%rdi)
-; AVX2-NEXT:    vmovq %xmm1, (%rdi)
+; AVX2-NEXT:    vbroadcastss %xmm1, %xmm1
+; AVX2-NEXT:    vblendps {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2,3]
+; AVX2-NEXT:    vextractps $2, %xmm0, 8(%rdi)
+; AVX2-NEXT:    vmovlps %xmm1, (%rdi)
 ; AVX2-NEXT:    retq
 ;
 ; XOP-LABEL: v3i32:
 ; XOP:       # BB#0:
 ; XOP-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
 ; XOP-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; XOP-NEXT:    vpextrd $2, %xmm0, 8(%rdi)
 ; XOP-NEXT:    vmovq %xmm1, (%rdi)

 ; SSE42-NEXT:    pextrd $3, %xmm0, 16(%rdi)
 ; SSE42-NEXT:    movdqa %xmm2, (%rdi)
 ; SSE42-NEXT:    retq
 ;
 ; AVX1-LABEL: v5i32:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vshufps {{.*#+}} xmm1 = xmm0[0,1],xmm1[1,2]
 ; AVX1-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; AVX1-NEXT:    vpextrd $3, %xmm0, 16(%rdi)
+; AVX1-NEXT:    vextractps $3, %xmm0, 16(%rdi)
 ; AVX1-NEXT:    vmovaps %xmm1, (%rdi)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v5i32:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
-; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = <0,5,1,6,3,u,u,u>
-; AVX2-NEXT:    vpermd %ymm1, %ymm2, %ymm1
-; AVX2-NEXT:    vpextrd $3, %xmm0, 16(%rdi)
-; AVX2-NEXT:    vmovdqa %xmm1, (%rdi)
+; AVX2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm1
+; AVX2-NEXT:    vmovaps {{.*#+}} ymm2 = <0,5,1,6,3,u,u,u>
+; AVX2-NEXT:    vpermps %ymm1, %ymm2, %ymm1
+; AVX2-NEXT:    vextractps $3, %xmm0, 16(%rdi)
+; AVX2-NEXT:    vmovaps %xmm1, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; XOP-LABEL: v5i32:
 ; XOP:       # BB#0:
 ; XOP-NEXT:    vshufps {{.*#+}} xmm1 = xmm0[0,1],xmm1[1,2]
 ; XOP-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,2,1,3]
-; XOP-NEXT:    vpextrd $3, %xmm0, 16(%rdi)
+; XOP-NEXT:    vextractps $3, %xmm0, 16(%rdi)
 ; XOP-NEXT:    vmovaps %xmm1, (%rdi)
 ; XOP-NEXT:    retq
   %r = shufflevector <4 x i32> %a, <4 x i32> %b, <5 x i32> <i32 0, i32 5, i32 1, i32 6, i32 3>
   store <5 x i32> %r, <5 x i32>* %p
   ret void
 }
 
 define void @v5f32(<4 x float> %a, <4 x float> %b, <5 x float>* %p) nounwind {

llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll

; X64-NEXT:    retq
   %ext = extractelement <16 x i8> %arg0, i32 1
   %res = zext i8 %ext to i32
   ret i32 %res
 }
 
 define i32 @test_mm_extract_epi32(<2 x i64> %a0) {
 ; X32-LABEL: test_mm_extract_epi32:
 ; X32:       # BB#0:
-; X32-NEXT:    pextrd $1, %xmm0, %eax
+; X32-NEXT:    extractps $1, %xmm0, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_extract_epi32:
 ; X64:       # BB#0:
-; X64-NEXT:    pextrd $1, %xmm0, %eax
+; X64-NEXT:    extractps $1, %xmm0, %eax
 ; X64-NEXT:    retq
   %arg0 = bitcast <2 x i64> %a0 to <4 x i32>
   %ext = extractelement <4 x i32> %arg0, i32 1
   ret i32 %ext
 }
 
 define i64 @test_mm_extract_epi64(<2 x i64> %a0) {
 ; X32-LABEL: test_mm_extract_epi64:
 ; X32:       # BB#0:
-; X32-NEXT:    pextrd $2, %xmm0, %eax
-; X32-NEXT:    pextrd $3, %xmm0, %edx
+; X32-NEXT:    extractps $2, %xmm0, %eax
+; X32-NEXT:    extractps $3, %xmm0, %edx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_extract_epi64:
 ; X64:       # BB#0:
 ; X64-NEXT:    pextrq $1, %xmm0, %rax
 ; X64-NEXT:    retq
   %arg0 = bitcast <2 x i64> %a0 to <4 x i32>
   %ext = extractelement <2 x i64> %a0, i32 1

llvm/trunk/test/CodeGen/X86/sse41-schedule.ll

; ZNVER1-NEXT:    retq # sched: [1:0.50]
   store i8 %2, i8 *%a1
   %3 = zext i8 %1 to i32
   ret i32 %3
 }
 
 define i32 @test_pextrd(<4 x i32> %a0, i32 *%a1) {
 ; GENERIC-LABEL: test_pextrd:
 ; GENERIC:       # BB#0:
+; GENERIC-NEXT:    paddd %xmm0, %xmm0 # sched: [1:0.50]
 ; GENERIC-NEXT:    pextrd $3, %xmm0, %eax # sched: [3:1.00]
 ; GENERIC-NEXT:    pextrd $1, %xmm0, (%rdi) # sched: [5:1.00]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; SLM-LABEL: test_pextrd:
 ; SLM:       # BB#0:
+; SLM-NEXT:    paddd %xmm0, %xmm0 # sched: [1:0.50]
 ; SLM-NEXT:    pextrd $3, %xmm0, %eax # sched: [1:1.00]
 ; SLM-NEXT:    pextrd $1, %xmm0, (%rdi) # sched: [4:2.00]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_pextrd:
 ; SANDY:       # BB#0:
+; SANDY-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; SANDY-NEXT:    vpextrd $3, %xmm0, %eax # sched: [3:1.00]
 ; SANDY-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [5:1.00]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_pextrd:
 ; HASWELL:       # BB#0:
+; HASWELL-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; HASWELL-NEXT:    vpextrd $3, %xmm0, %eax # sched: [2:1.00]
 ; HASWELL-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; HASWELL-NEXT:    retq # sched: [2:1.00]
 ;
 ; BROADWELL-LABEL: test_pextrd:
 ; BROADWELL:       # BB#0:
+; BROADWELL-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; BROADWELL-NEXT:    vpextrd $3, %xmm0, %eax # sched: [2:1.00]
 ; BROADWELL-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; BROADWELL-NEXT:    retq # sched: [2:1.00]
 ;
 ; SKYLAKE-LABEL: test_pextrd:
 ; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
 ; SKYLAKE-NEXT:    vpextrd $3, %xmm0, %eax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [2:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKX-LABEL: test_pextrd:
 ; SKX:       # BB#0:
+; SKX-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    vpextrd $3, %xmm0, %eax # sched: [3:1.00]
 ; SKX-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [2:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_pextrd:
 ; BTVER2:       # BB#0:
+; BTVER2-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vpextrd $3, %xmm0, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pextrd:
 ; ZNVER1:       # BB#0:
+; ZNVER1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    vpextrd $3, %xmm0, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [8:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
-  %1 = extractelement <4 x i32> %a0, i32 3
-  %2 = extractelement <4 x i32> %a0, i32 1
-  store i32 %2, i32 *%a1
-  ret i32 %1
+  %1 = add <4 x i32> %a0, %a0
+  %2 = extractelement <4 x i32> %1, i32 3
+  %3 = extractelement <4 x i32> %1, i32 1
+  store i32 %3, i32 *%a1
+  ret i32 %2
 }
 
 define i64 @test_pextrq(<2 x i64> %a0, <2 x i64> %a1, i64 *%a2) {
 ; GENERIC-LABEL: test_pextrq:
 ; GENERIC:       # BB#0:
 ; GENERIC-NEXT:    pextrq $1, %xmm0, %rax # sched: [3:1.00]
 ; GENERIC-NEXT:    pextrq $1, %xmm0, (%rdi) # sched: [5:1.00]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]

llvm/trunk/test/CodeGen/X86/sse41.ll

 ; X64:       ## BB#0:
 ; X64-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; X64-NEXT:    addss {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %s = extractelement <4 x float> %v, i32 3
   %t = fadd float %s, 1.0
   ret float %t
 }
+
 define float @ext_2(<4 x float> %v) nounwind {
 ; X32-LABEL: ext_2:
 ; X32:       ## BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; X32-NEXT:    movss %xmm0, (%esp)
 ; X32-NEXT:    flds (%esp)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ext_2:
 ; X64:       ## BB#0:
 ; X64-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
 ; X64-NEXT:    retq
   %s = extractelement <4 x float> %v, i32 3
   ret float %s
 }
+
 define i32 @ext_3(<4 x i32> %v) nounwind {
 ; X32-LABEL: ext_3:
 ; X32:       ## BB#0:
-; X32-NEXT:    pextrd $3, %xmm0, %eax
+; X32-NEXT:    extractps $3, %xmm0, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ext_3:
 ; X64:       ## BB#0:
-; X64-NEXT:    pextrd $3, %xmm0, %eax
+; X64-NEXT:    extractps $3, %xmm0, %eax
 ; X64-NEXT:    retq
   %i = extractelement <4 x i32> %v, i32 3
   ret i32 %i
 }
 
 define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
 ; X32-LABEL: insertps_1:
 ; X32:       ## BB#0:

 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    ptest %xmm1, %xmm0
 ; X64-NEXT:    seta %al
 ; X64-NEXT:    retq
   %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
   ret i32 %tmp1
 }
 
-
 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
 
 ; This used to compile to insertps $0  + insertps $16.  insertps $0 is always
 ; pointless.
 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind  {
 ; X32-LABEL: buildvector:

llvm/trunk/test/CodeGen/X86/widen_load-3.ll

 ; X86-SSE-NEXT:    movl 52(%ecx), %ecx
 ; X86-SSE-NEXT:    movl %ecx, 52(%eax)
 ; X86-SSE-NEXT:    movl %edx, 48(%eax)
 ; X86-SSE-NEXT:    movaps %xmm2, 32(%eax)
 ; X86-SSE-NEXT:    movaps %xmm1, 16(%eax)
 ; X86-SSE-NEXT:    movaps %xmm0, (%eax)
 ; X86-SSE-NEXT:    retl $4
 ;
-; X86-AVX1-LABEL: load7_aligned:
-; X86-AVX1:       # BB#0:
-; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX1-NEXT:    vmovaps (%ecx), %ymm0
-; X86-AVX1-NEXT:    vmovaps 32(%ecx), %ymm1
-; X86-AVX1-NEXT:    vmovaps %ymm0, (%eax)
-; X86-AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm0
-; X86-AVX1-NEXT:    vpextrd $1, %xmm0, 52(%eax)
-; X86-AVX1-NEXT:    vmovd %xmm0, 48(%eax)
-; X86-AVX1-NEXT:    vmovaps %xmm1, 32(%eax)
-; X86-AVX1-NEXT:    vzeroupper
-; X86-AVX1-NEXT:    retl $4
-;
-; X86-AVX2-LABEL: load7_aligned:
-; X86-AVX2:       # BB#0:
-; X86-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX2-NEXT:    vmovaps (%ecx), %ymm0
-; X86-AVX2-NEXT:    vmovdqa 32(%ecx), %ymm1
-; X86-AVX2-NEXT:    vmovaps %ymm0, (%eax)
-; X86-AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm0
-; X86-AVX2-NEXT:    vpextrd $1, %xmm0, 52(%eax)
-; X86-AVX2-NEXT:    vmovd %xmm0, 48(%eax)
-; X86-AVX2-NEXT:    vmovdqa %xmm1, 32(%eax)
-; X86-AVX2-NEXT:    vzeroupper
-; X86-AVX2-NEXT:    retl $4
+; X86-AVX-LABEL: load7_aligned:
+; X86-AVX:       # BB#0:
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT:    vmovaps (%ecx), %ymm0
+; X86-AVX-NEXT:    vmovaps 32(%ecx), %ymm1
+; X86-AVX-NEXT:    vmovaps %ymm0, (%eax)
+; X86-AVX-NEXT:    vextractf128 $1, %ymm1, %xmm0
+; X86-AVX-NEXT:    vextractps $1, %xmm0, 52(%eax)
+; X86-AVX-NEXT:    vmovss %xmm0, 48(%eax)
+; X86-AVX-NEXT:    vmovaps %xmm1, 32(%eax)
+; X86-AVX-NEXT:    vzeroupper
+; X86-AVX-NEXT:    retl $4
 ;
 ; X64-SSE-LABEL: load7_aligned:
 ; X64-SSE:       # BB#0:
 ; X64-SSE-NEXT:    movaps (%rsi), %xmm0
 ; X64-SSE-NEXT:    movaps 16(%rsi), %xmm1
 ; X64-SSE-NEXT:    movaps 32(%rsi), %xmm2
 ; X64-SSE-NEXT:    movq 48(%rsi), %rax
 ; X64-SSE-NEXT:    movq %rax, 48(%rdi)