[mips] Fix (dis)assembly of abs.fmt for micromips

[sdardis]

Summary

These instructions were previously marked as codegen only preventing
them from being assembled as microMIPS or disassembled.

[atanasyan]

LGTM

[sdardis]

Thanks for the review.

llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
                               fsqrt>, ROUND_W_FM_MM<1, 0x28>,
                ISA_MICROMIPS, FGR_32;
 
 def CVT_L_S_MM   : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
                    ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
                    ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
 
+}
+
+let DecoderNamespace = "MicroMips" in {
   def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
                   ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
+  def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
+                ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
+}
+
+let isCodeGenOnly = 1 in {
 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
                 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
 def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
                  ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32;
 def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
                    ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32;
 def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
                    ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;
 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
                  ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
 
-def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
-              ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
               ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32;
 
 def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
                   ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32;
 
 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
                                      II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

 let isPseudo = 1, isCodeGenOnly = 1 in {
   def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
   def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
   def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
                ABSS_FM<0x5, 16>;
+  defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
+}
+
 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
              ABSS_FM<0x7, 16>;
-defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
               II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
 
 // The odd-numbered registers are only referenced when doing loads,
 // stores, and moves between floating-point and integer registers.

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0x0a 0xaf # CHECK: bnez16 $6, 20
 0x42 0xcc # CHECK: b16 132
 0x88 0x65 # CHECK: lw $3, 32($gp)
 0x12 0x45 # CHECK: lwm16 $16, $17, $ra, 8($sp)
 0x52 0x45 # CHECK: swm16 $16, $17, $ra, 8($sp)
 0x88 0x46 # CHECK: break16 8
 0xce 0x46 # CHECK: sdbbp16 14
 0x34 0x84 # CHECK: movep $5, $6, $2, $3
+0x40 0x54 0x7b 0x03 # CHECK: abs.s $f2, $f0
+0x40 0x54 0x7b 0x23 # CHECK: abs.d $f2, $f0
 0xe6 0x00 0x10 0x49 # CHECK: add $9, $6, $7
 0x26 0x11 0x67 0x45 # CHECK: addi $9, $6, 17767
 0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
 0x26 0x11 0x67 0x45 # CHECK: addi $9, $6, 17767
 0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
 0xe6 0x00 0x50 0x49 # CHECK: addu $9, $6, $7
 0x80 0x43 0xe6 0xff # CHECK: bc1f -48
 0xa0 0x43 0xe2 0xff # CHECK: bc1t -56

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

 0xaf 0x0a # CHECK: bnez16 $6, 20
 0xcc 0x42 # CHECK: b16 132
 0x65 0x88 # CHECK: lw $3, 32($gp)
 0x45 0x12 # CHECK: lwm16 $16, $17, $ra, 8($sp)
 0x45 0x52 # CHECK: swm16 $16, $17, $ra, 8($sp)
 0x46 0x88 # CHECK: break16 8
 0x46 0xce # CHECK: sdbbp16 14
 0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x54 0x40 0x03 0x7b # CHECK: abs.s $f2, $f0
+0x54 0x40 0x23 0x7b # CHECK: abs.d $f2, $f0
 0x00 0xe6 0x49 0x10 # CHECK: add $9, $6, $7
 0x11 0x26 0x45 0x67 # CHECK: addi $9, $6, 17767
 0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
 0x11 0x26 0x45 0x67 # CHECK: addi $9, $6, 17767
 0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
 0x00 0xe6 0x49 0x50 # CHECK: addu $9, $6, $7
 0x43 0x80 0xff 0xe6 # CHECK: bc1f -48
 0x43 0xa0 0xff 0xe2 # CHECK: bc1t -56

llvm/trunk/test/MC/Mips/micromips/valid.s

 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
 movep $5, $6, $2, $3        # CHECK: movep $5, $6, $2, $3        # encoding: [0x84,0x34]
 break16 8                   # CHECK: break16 8          # encoding: [0x46,0x88]
 sdbbp16 14                  # CHECK: sdbbp16 14         # encoding: [0x46,0xce]
 lw $3, 32($sp)              # CHECK: lw $3, 32($sp)     # encoding: [0x48,0x68]
 sw $4, 124($sp)             # CHECK: sw $4, 124($sp)    # encoding: [0xc8,0x9f]
 lw $3, 32($gp)              # CHECK: lw $3, 32($gp)     # encoding: [0x65,0x88]
+abs.s $f0, $f2              # CHECK:  abs.s $f0, $f2    # encoding: [0x54,0x02,0x03,0x7b]
+                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_S_MM
+abs.d $f4, $f6              # CHECK:  abs.d $f4, $f6    # encoding: [0x54,0x86,0x23,0x7b]
+                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_MM
 add $9, $6, $7              # CHECK: add $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x10]
 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
 addu $9, $6, $7             # CHECK: addu $9, $6, $7        # encoding: [0x00,0xe6,0x49,0x50]
 sub $9, $6, $7              # CHECK: sub $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x90]
 subu $4, $3, $5             # CHECK: subu $4, $3, $5        # encoding: [0x00,0xa3,0x21,0xd0]