MIPS64r6 LSA/DLSA instructions

[jkolek]

Summary

Implemented *_DESC and *_ENC classes for MIPS64r6 LSA and DLSA instructions.

[dsanders]

LSA/DLSA in MIPS32r6/MIPS64r6 are the same instructions as in the MSA ASE. Can you explain the need for a second copy rather than correcting the predicates of the pre-existing one?

[jkolek]

This patch implements support for LSA & DLSA instructions using predicates. This approach first includes all the MSA instructions in MIPS32r6/MIPS64r6 and then excludes all of them except LSA and DLSA. Maybe there is a better solution for this using predicates, but I didn't have a better idea. Zoran's suggestion is that we could reuse *_DESC and *_ENC classes from MSA, but to introduce new instruction definitions for MIPS32r6/MIPS64r6.

[dsanders]

To be clear, I was only requesting an explanation for the seemingly redundant definition. I was guessing that the 32 feature bit limitation was likely to be the reason you couldn't follow the pattern used elsewhere (see below for details) in which case I would have requested a FIXME comment and approved it.

Your previous patch is better than the current one. The current one makes it impossible to use MSA on MIPS32r6/MIPS64r6.

See FeatureMips3_32 for an example of how to do a 'FeatureX || FeatureY' predicate. You define a feature that is the set of instructions in both MIPS32r6 and MSA (likewise for MIPS64r6 and MSA) and make that feature an implied bit for both MIPS32r6 and MSA. The snag is that this requires extra feature bits and tablegen currently asserts when there's more than 32. I have some plans for fixing this (either lifting the 32 feature limit, or adding support for an or condition) but it won't be a quick fix.

lib/Target/Mips/MipsMSAInstrInfo.td

3252

It's a moot point since I've asked you to go back to the previous version of the patch but DLSA does not require the N64 ABI. It's requires 64-bit GPRs.

[jkolek]

Previous version of patch, rebased.

[dsanders]

You haven't answered the original question yet but I've just tried the FeatureMips3_32-style approach and we do hit the 32 feature bit limit. I know what needs to be done to fix that but I lack the time to do so at the moment. I therefore think it's best that we go ahead with this patch (with a minor change described below) and fix the 32 feature bit limit issue later.

Can you add a RUN line for mips32r6 and mips64r6 to test/CodeGen/Mips/msa/special.ll? E.g:

; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \
; RUN:   FileCheck %s --check-prefix=MIPS32
; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \
; RUN:   FileCheck %s --check-prefix=MIPS64

This will ensure that the two definitions don't cause problems for MSA on MIPS32r6/MIPS64r6.

With that change it will LGTM.

[jkolek]

I have added the RUN lines to test/CodeGen/Mips/msa/special.ll.

[dsanders]

LGTM

[jkolek]

Closed by commit rL211346 (authored by zjovanovic).

lib/Target/Mips/Mips.td

 def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
-def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
+def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32, FeatureMSA]>;
 
 def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
 def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
-def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
+def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64, FeatureMSA]>;
 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 

lib/Target/Mips/MipsMSAInstrFormats.td

              AssemblerPredicate<"FeatureMSA">;
 
 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
-  let Predicates = [HasMSA];
+  let Predicates = [HasMSA, NotMips32r6, NotMips64r6];
   let Inst{31-26} = 0b011110;
 }
 
 class MSA64Inst : MSAInst {
-  let Predicates = [HasMSA, HasMips64];
+  let Predicates = [HasMSA, HasMips64, NotMips32r6, NotMips64r6];
 }
 
 class MSACBranch : MSAInst {

 class MSAPseudo<dag outs, dag ins, list<dag> pattern,
                 InstrItinClass itin = IIPseudo>:
   MipsPseudo<outs, ins, pattern, itin> {
-  let Predicates = [HasMSA];
+  let Predicates = [HasMSA, NotMips32r6, NotMips64r6];
 }
 
 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {

lib/Target/Mips/MipsMSAInstrInfo.td

 def LDI_W : LDI_W_ENC, LDI_W_DESC;
 def LDI_D : LDI_D_ENC, LDI_D_DESC;
 
+let Predicates = [HasMSA] in {
 def LSA : LSA_ENC, LSA_DESC;
+}
+let Predicates = [HasMSA, IsN64] in {
 def DLSA : DLSA_ENC, DLSA_DESC;
+}
 
 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;

test/MC/Mips/mips32r6/valid.s

         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
+        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]

test/MC/Mips/mips64r6/valid.s

         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
+        lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
+        dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x95]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
 #        mul     $2,$3,$4         # CHECK-TODO: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]