MIPS64r6 Relocation R_MIPS_PC18_S3

[zoran.jovanovic]

Summary

Implemented relocation R_MIPS_PC18_S3.

[dsanders]

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

107

The S3 means 'right shift by 3' so this should be either '>> 3' or '/ 8'.

246

You need to update the big-endian table as well.

lib/Target/Mips/MipsInstrInfo.td

347

See comments on D3866 about how there should only be one kind of immediate.

[zoran.jovanovic]

Fixed reported issues from previous version.

[dsanders]

LGTM with a nit

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

644

The string says 'Lsl2' instead of 'Lsl3'

[zoran.jovanovic]

Closed by commit rL210908 (authored by zjovanovic).

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case Mips::fixup_MICROMIPS_PC16_S1:
     Value -= 4;
     // Forcing a signed division because Value can be negative.
     Value = (int64_t)Value / 2;
     // We now check if Value can be encoded as a 16-bit signed immediate.
     if (!isIntN(16, Value) && Ctx)
       Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
     break;
+  case Mips::fixup_MIPS_PC18_S3:
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 8;
+    // We now check if Value can be encoded as a 18-bit signed immediate.
+    if (!isIntN(18, Value) && Ctx)
+      Ctx->FatalError(Fixup.getLoc(), "out of range PC18 fixup");
+    break;
   case Mips::fixup_MIPS_PC21_S2:
     Value -= 4;
     // Forcing a signed division because Value can be negative.
     Value = (int64_t) Value / 4;
     // We now check if Value can be encoded as a 21-bit signed immediate.
     if (!isIntN(21, Value) && Ctx)
       Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup");
     break;
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_Mips_TLSGD",        0,     16,   0 },
     { "fixup_Mips_GOTTPREL",     0,     16,   0 },
     { "fixup_Mips_TPREL_HI",     0,     16,   0 },
     { "fixup_Mips_TPREL_LO",     0,     16,   0 },
     { "fixup_Mips_TLSLDM",       0,     16,   0 },
     { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
     { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
     { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
     { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
     { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
     { "fixup_Mips_GOT_OFST",     0,     16,   0 },
     { "fixup_Mips_GOT_DISP",     0,     16,   0 },
     { "fixup_Mips_HIGHER",       0,     16,   0 },
     { "fixup_Mips_HIGHEST",      0,     16,   0 },
     { "fixup_Mips_GOT_HI16",     0,     16,   0 },
     { "fixup_Mips_GOT_LO16",     0,     16,   0 },
     { "fixup_Mips_CALL_HI16",    0,     16,   0 },
     { "fixup_Mips_CALL_LO16",    0,     16,   0 },
+    { "fixup_Mips_PC18_S3",      0,     18,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC21_S2",      0,     21,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC26_S2",      0,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
     { "fixup_MICROMIPS_HI16",    0,     16,   0 },
     { "fixup_MICROMIPS_LO16",    0,     16,   0 },
     { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_Mips_GOT_OFST",    16,     16,   0 },
     { "fixup_Mips_GOT_DISP",    16,     16,   0 },
     { "fixup_Mips_HIGHER",      16,     16,   0 },
     { "fixup_Mips_HIGHEST",     16,     16,   0 },
     { "fixup_Mips_GOT_HI16",    16,     16,   0 },
     { "fixup_Mips_GOT_LO16",    16,     16,   0 },
     { "fixup_Mips_CALL_HI16",   16,     16,   0 },
     { "fixup_Mips_CALL_LO16",   16,     16,   0 },
+    { "fixup_Mips_PC18_S3",     14,     18,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC21_S2",     11,     21,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC26_S2",      6,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   6,     26,   0 },
     { "fixup_MICROMIPS_HI16",   16,     16,   0 },
     { "fixup_MICROMIPS_LO16",   16,     16,   0 },
     { "fixup_MICROMIPS_GOT16",  16,     16,   0 },

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
     Type = ELF::R_MICROMIPS_TLS_DTPREL_LO16;
     break;
   case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
     Type = ELF::R_MICROMIPS_TLS_TPREL_HI16;
     break;
   case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
     Type = ELF::R_MICROMIPS_TLS_TPREL_LO16;
     break;
+  case Mips::fixup_MIPS_PC18_S3:
+    Type = ELF::R_MIPS_PC18_S3;
+    break;
   case Mips::fixup_MIPS_PC21_S2:
     Type = ELF::R_MIPS_PC21_S2;
     break;
   case Mips::fixup_MIPS_PC26_S2:
     Type = ELF::R_MIPS_PC26_S2;
     break;
   case Mips::fixup_MIPS_PCHI16:
     Type = ELF::R_MIPS_PCHI16;

lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
     fixup_Mips_GOT_LO16,
 
     // resulting in - R_MIPS_CALL_HI16
     fixup_Mips_CALL_HI16,
 
     // resulting in - R_MIPS_CALL_LO16
     fixup_Mips_CALL_LO16,
 
+    // resulting in - R_MIPS_PC18_S3
+    fixup_MIPS_PC18_S3,
+
     // resulting in - R_MIPS_PC21_S2
     fixup_MIPS_PC21_S2,
 
     // resulting in - R_MIPS_PC26_S2
     fixup_MIPS_PC26_S2,
 
     // resulting in - R_MIPS_PCHI16
     fixup_MIPS_PCHI16,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
   assert((Res & 3) == 0);
   return Res >> 2;
 }
 
 unsigned
 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
                                          SmallVectorImpl<MCFixup> &Fixups,
                                          const MCSubtargetInfo &STI) const {
-  assert(MI.getOperand(OpNo).isImm());
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm()) {
     // The immediate is encoded as 'immediate << 3'.
     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
     assert((Res & 7) == 0);
     return Res >> 3;
   }
 
+  assert(MO.isExpr() &&
+         "getSimm18Lsl2Encoding expects only expressions or an immediate");
+
+  const MCExpr *Expr = MO.getExpr();
+  Fixups.push_back(MCFixup::Create(0, Expr,
+                                   MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
+  return 0;
+}
+
 #include "MipsGenMCCodeEmitter.inc"

lib/Target/Mips/MipsInstrInfo.td

 def simm19_lsl2 : Operand<i32> {
   let EncoderMethod = "getSimm19Lsl2Encoding";
   let DecoderMethod = "DecodeSimm19Lsl2";
 }
 
 def simm18_lsl3 : Operand<i32> {
   let EncoderMethod = "getSimm18Lsl3Encoding";
   let DecoderMethod = "DecodeSimm18Lsl3";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
 def simm20      : Operand<i32> {
 }
 
 def uimm20      : Operand<i32> {
 }
 
 def uimm10      : Operand<i32> {
 }

test/MC/Mips/mips64r6/relocations.s

 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar)    # encoding: [0xec,0x5f,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_HI16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCHI16
 # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_LO16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: ldpc    $2, bar               # encoding: [0xec,0b010110AA,A,A]
+# CHECK-FIXUP:                               # fixup A - offset: 0,
+# CHECK-FIXUP:                                 value: bar,
+# CHECK-FIXUP:                                 kind: fixup_Mips_PC18_S3
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MIPS_PC16 bar 0x0
 # CHECK-ELF:     0x4 R_MIPS_PC16 bar 0x0
 # CHECK-ELF:     0x8 R_MIPS_PC21_S2 bar 0x0
 # CHECK-ELF:     0xC R_MIPS_PC21_S2 bar 0x0
 # CHECK-ELF:     0x10 R_MIPS_PC26_S2 bar 0x0
 # CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar 0x0
 # CHECK-ELF:     0x18 R_MIPS_PCHI16 bar 0x0
 # CHECK-ELF:     0x1C R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF:     0x20 R_MIPS_PC18_S3 bar 0x0
 # CHECK-ELF: ]
 
   beqc  $5, $6, bar
   bnec  $5, $6, bar
   beqzc $9, bar
   bnezc $9, bar
   balc  bar
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
+  ldpc      $2,bar