This is an archive of the discontinued LLVM Phabricator instance.

Differential D38851

[Hexagon] New HVX target features.
ClosedPublic

Authored by sgundapa on Oct 12 2017, 9:25 AM.

Details

Reviewers
kparzysz
Commits
rGe1983bcf5529: [Hexagon] New HVX target features.
rL316101: [Hexagon] New HVX target features.
Summary

This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Diff Detail

Event Timeline

sgundapa created this revision.Oct 12 2017, 9:25 AM
Herald added subscribers: eraman, qcolombet, MatzeB. · View Herald TranscriptOct 12 2017, 9:25 AM
kparzysz accepted this revision.Oct 12 2017, 9:55 AM

LGTM with a comment.

test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll
37

Could you replace all occurrences of -hvx-length128b with +hvx-length64b?

This revision is now accepted and ready to land.Oct 12 2017, 9:55 AM
Closed by commit rL316101: [Hexagon] New HVX target features. (authored by sgundapa). · Explain WhyOct 18 2017, 11:07 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Hexagon/
56 lines
66 lines
2 lines
46 lines
9 lines
16 lines
MCTargetDesc/
2 lines
test/
CodeGen/
Hexagon/
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
2 lines
2 lines
4 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
4 lines
2 lines
7 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
intrinsics/
2 lines
2 lines
2 lines
2 lines
loop-idiom/
2 lines
2 lines
2 lines
4 lines
4 lines
4 lines
2 lines
2 lines
4 lines
2 lines
2 lines
2 lines
8 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
2 lines
2 lines
2 lines
2 lines
2 lines
4 lines
2 lines
4 lines
2 lines
2 lines
2 lines
2 lines
4 lines
4 lines
2 lines
MC/
Hexagon/
2 lines
2 lines
4 lines
4 lines
2 lines
4 lines
4 lines
4 lines
4 lines
4 lines
4 lines
4 lines
2 lines
Transforms/
SimplifyCFG/
Hexagon/
2 lines
tools/
llvm-objdump/
Hexagon/
2 lines

Diff 118801

lib/Target/Hexagon/Hexagon.td

Show All 19 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Subtarget features. // Hexagon Subtarget features.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Architectures // Hexagon Architectures
include "HexagonDepArch.td" include "HexagonDepArch.td"
// Hexagon ISA Extensions // Hexagon ISA Extensions
def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
"Hexagon HVX instructions">; "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
"Hexagon HVX Double instructions">; "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
[ExtensionHVXV60]>;
def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
"Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
[ExtensionHVXV60,
ExtensionHVXV62]>;
def ExtensionHVX64B
: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
"Hexagon HVX 64B instructions",
[ExtensionHVXV60, ExtensionHVXV62]>;
def ExtensionHVX128B
: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
"Hexagon HVX 128B instructions",
[ExtensionHVXV60, ExtensionHVXV62]>;
// This is an alias to ExtensionHVX128B to accept the hvx-double as
// an acceptable subtarget feature.
def ExtensionHVXDbl
: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
"Hexagon HVX 128B instructions",
[ExtensionHVXV60, ExtensionHVXV62]>;
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Use constant-extended calls">; "Use constant-extended calls">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions. // Hexagon Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def UseMEMOP : Predicate<"HST->useMemOps()">; def UseMEMOP : Predicate<"HST->useMemOps()">;
def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
AssemblerPredicate<"ExtensionHVXDbl">; AssemblerPredicate<"ExtensionHVX64B">;
def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; def UseHVX128B : Predicate<"HST->useHVX128BOps()">,
def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, AssemblerPredicate<"ExtensionHVX128B">;
AssemblerPredicate<"ExtensionHVX">; def UseHVX : Predicate<"HST->useHVXOps()">,
AssemblerPredicate<"ExtensionHVXV60">;
def Hvx64 : HwMode<"+hvx,-hvx-double">; def UseHVXV60 : Predicate<"HST->useHVXOps()">,
def Hvx128 : HwMode<"+hvx,+hvx-double">; AssemblerPredicate<"ExtensionHVXV60">;
def UseHVXV62 : Predicate<"HST->useHVXOps()">,
AssemblerPredicate<"ExtensionHVXV62">;
def Hvx64 : HwMode<"+hvx-length64b">;
def Hvx64old : HwMode<"-hvx-double">;
def Hvx128 : HwMode<"+hvx-length128b">;
def Hvx128old : HwMode<"+hvx-double">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Classes used for relation maps. // Classes used for relation maps.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ImmRegShl; class ImmRegShl;
// PredRel - Filter class used to relate non-predicated instructions with their // PredRel - Filter class used to relate non-predicated instructions with their
// predicated forms. // predicated forms.
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
def : Proc<"hexagonv4", HexagonModelV4, def : Proc<"hexagonv4", HexagonModelV4,
[ArchV4]>; [ArchV4]>;
def : Proc<"hexagonv5", HexagonModelV4, def : Proc<"hexagonv5", HexagonModelV4,
[ArchV4, ArchV5]>; [ArchV4, ArchV5]>;
def : Proc<"hexagonv55", HexagonModelV55, def : Proc<"hexagonv55", HexagonModelV55,
[ArchV4, ArchV5, ArchV55]>; [ArchV4, ArchV5, ArchV55]>;
def : Proc<"hexagonv60", HexagonModelV60, def : Proc<"hexagonv60", HexagonModelV60,
[ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; [ArchV4, ArchV5, ArchV55, ArchV60]>;
def : Proc<"hexagonv62", HexagonModelV62, def : Proc<"hexagonv62", HexagonModelV62,
[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>; [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declare the target which we are implementing // Declare the target which we are implementing
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HexagonAsmParser : AsmParser { def HexagonAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = 1; let ShouldEmitMatchRegisterAltName = 1;
bit HasMnemonicFirst = 0; bit HasMnemonicFirst = 0;
Show All 13 Lines

lib/Target/Hexagon/HexagonISelLowering.cpp

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Linesstatic bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
}; };
static const MCPhysReg VecLstD[] = { static const MCPhysReg VecLstD[] = {
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
Hexagon::W5, Hexagon::W6, Hexagon::W7 Hexagon::W5, Hexagon::W6, Hexagon::W7
}; };
auto &MF = State.getMachineFunction(); auto &MF = State.getMachineFunction();
auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &HST = MF.getSubtarget<HexagonSubtarget>();
if (HST.useHVXSglOps() && if (HST.useHVX64BOps() &&
(LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) { if (unsigned Reg = State.AllocateReg(VecLstS)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
unsigned Offset = State.AllocateStack(64, 64); unsigned Offset = State.AllocateStack(64, 64);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||
LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) { LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) { if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
unsigned Offset = State.AllocateStack(128, 128); unsigned Offset = State.AllocateStack(128, 128);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
// 128B Mode // 128B Mode
if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||
LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) { if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
unsigned Offset = State.AllocateStack(256, 256); unsigned Offset = State.AllocateStack(256, 256);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (HST.useHVXDblOps() && if (HST.useHVX128BOps() &&
(LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) { if (unsigned Reg = State.AllocateReg(VecLstS)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
unsigned Offset = State.AllocateStack(128, 128); unsigned Offset = State.AllocateStack(128, 128);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Show All 31 Linesstatic bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
} else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
LocVT == MVT::v512i1) { LocVT == MVT::v512i1) {
LocVT = MVT::v16i32; LocVT = MVT::v16i32;
ValVT = MVT::v16i32; ValVT = MVT::v16i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
} else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
(LocVT == MVT::v1024i1 && HST.useHVXDblOps())) { (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
LocVT = MVT::v32i32; LocVT = MVT::v32i32;
ValVT = MVT::v32i32; ValVT = MVT::v32i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
} else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
LocVT = MVT::v64i32; LocVT = MVT::v64i32;
ValVT = MVT::v64i32; ValVT = MVT::v64i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesstatic bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &HST = MF.getSubtarget<HexagonSubtarget>();
if (LocVT == MVT::v16i32) { if (LocVT == MVT::v16i32) {
if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
} else if (LocVT == MVT::v32i32) { } else if (LocVT == MVT::v32i32) {
unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0; unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;
if (unsigned Reg = State.AllocateReg(Req)) { if (unsigned Reg = State.AllocateReg(Req)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
} }
} else if (LocVT == MVT::v64i32) { } else if (LocVT == MVT::v64i32) {
if (unsigned Reg = State.AllocateReg(Hexagon::W0)) { if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false; return false;
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
if (VA.isRegLoc()) if (VA.isRegLoc())
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} }
if (NeedsArgAlign && Subtarget.hasV60TOps()) { if (NeedsArgAlign && Subtarget.hasV60TOps()) {
DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
// V6 vectors passed by value have 64 or 128 byte alignment depending // V6 vectors passed by value have 64 or 128 byte alignment depending
// on whether we are 64 byte vector mode or 128 byte. // on whether we are 64 byte vector mode or 128 byte.
bool UseHVXDbl = Subtarget.useHVXDblOps(); bool UseHVX128B = Subtarget.useHVX128BOps();
assert(Subtarget.useHVXOps()); assert(Subtarget.useHVXOps());
const unsigned ObjAlign = UseHVXDbl ? 128 : 64; const unsigned ObjAlign = UseHVX128B ? 128 : 64;
LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign); LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
MFI.ensureMaxAlignment(LargestAlignSeen); MFI.ensureMaxAlignment(LargestAlignSeen);
} }
// Transform all store nodes into one single node because all store // Transform all store nodes into one single node because all store
// nodes are independent of each other. // nodes are independent of each other.
if (!MemOpChains.empty()) if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
SDValue &Base, SDValue &Offset, SDValue &Base, SDValue &Offset,
bool &IsInc, SelectionDAG &DAG) { bool &IsInc, SelectionDAG &DAG) {
if (Ptr->getOpcode() != ISD::ADD) if (Ptr->getOpcode() != ISD::ADD)
return false; return false;
auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget()); auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
bool ValidHVXDblType = bool ValidHVX128BType =
HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
VT == MVT::v64i16 || VT == MVT::v128i8); VT == MVT::v64i16 || VT == MVT::v128i8);
bool ValidHVXType = bool ValidHVXType =
HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
VT == MVT::v32i16 || VT == MVT::v64i8); VT == MVT::v32i16 || VT == MVT::v64i8);
if (ValidHVXDblType || ValidHVXType || if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||
VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { VT == MVT::i16 || VT == MVT::i8) {
IsInc = (Ptr->getOpcode() == ISD::ADD); IsInc = (Ptr->getOpcode() == ISD::ADD);
Base = Ptr->getOperand(0); Base = Ptr->getOperand(0);
Offset = Ptr->getOperand(1); Offset = Ptr->getOperand(1);
// Ensure that Offset is a constant. // Ensure that Offset is a constant.
return isa<ConstantSDNode>(Offset); return isa<ConstantSDNode>(Offset);
} }
return false; return false;
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines if ( (VA.isRegLoc() && !Flags.isByVal())
// Single Vector // Single Vector
} else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
} else if (Subtarget.useHVXDblOps() && } else if (Subtarget.useHVX128BOps() &&
((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
// Double Vector // Double Vector
} else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
} else if (Subtarget.useHVXDblOps() && } else if (Subtarget.useHVX128BOps() &&
((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
} else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
assert(0 && "need to support VecPred regs"); assert(0 && "need to support VecPred regs");
▲ Show 20 Lines • Show All 529 Lines • ▼ Show 20 LinesHexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
if (Subtarget.hasV5TOps()) { if (Subtarget.hasV5TOps()) {
addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
} }
if (Subtarget.hasV60TOps()) { if (Subtarget.hasV60TOps()) {
if (Subtarget.useHVXSglOps()) { if (Subtarget.useHVX64BOps()) {
addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
} else if (Subtarget.useHVXDblOps()) { } else if (Subtarget.useHVX128BOps()) {
addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass);
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 LinesHexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
} }
setOperationAction(ISD::SETCC, MVT::v2i16, Custom); setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
if (Subtarget.useHVXOps()) { if (Subtarget.useHVXOps()) {
if (Subtarget.useHVXSglOps()) { if (Subtarget.useHVX64BOps()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
// We try to generate the vpack{e/o} instructions. If we fail // We try to generate the vpack{e/o} instructions. If we fail
// we fall back upon ExpandOp. // we fall back upon ExpandOp.
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
} else if (Subtarget.useHVXDblOps()) { } else if (Subtarget.useHVX128BOps()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
// We try to generate the vpack{e/o} instructions. If we fail // We try to generate the vpack{e/o} instructions. If we fail
// we fall back upon ExpandOp. // we fall back upon ExpandOp.
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 LinesHexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
// Handling of indexed loads/stores: default is "expand". // Handling of indexed loads/stores: default is "expand".
// //
for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) { for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal); setIndexedLoadAction(ISD::POST_INC, VT, Legal);
setIndexedStoreAction(ISD::POST_INC, VT, Legal); setIndexedStoreAction(ISD::POST_INC, VT, Legal);
} }
if (Subtarget.useHVXSglOps()) { if (Subtarget.useHVX64BOps()) {
for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) { MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal); setIndexedLoadAction(ISD::POST_INC, VT, Legal);
setIndexedStoreAction(ISD::POST_INC, VT, Legal); setIndexedStoreAction(ISD::POST_INC, VT, Legal);
} }
} else if (Subtarget.useHVXDblOps()) { } else if (Subtarget.useHVX128BOps()) {
for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64, for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) { MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal); setIndexedLoadAction(ISD::POST_INC, VT, Legal);
setIndexedStoreAction(ISD::POST_INC, VT, Legal); setIndexedStoreAction(ISD::POST_INC, VT, Legal);
} }
} }
computeRegisterProperties(&HRI); computeRegisterProperties(&HRI);
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
DAG.getConstant(Lane, dl, MVT::i32)); DAG.getConstant(Lane, dl, MVT::i32));
} }
if (UseHVX) { if (UseHVX) {
ArrayRef<int> Mask = SVN->getMask(); ArrayRef<int> Mask = SVN->getMask();
size_t MaskLen = Mask.size(); size_t MaskLen = Mask.size();
unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen; unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;
if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) || if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) ||
(Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) { (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) {
StridedLoadKind Pattern = isStridedLoad(Mask); StridedLoadKind Pattern = isStridedLoad(Mask);
if (Pattern == StridedLoadKind::NoPattern) if (Pattern == StridedLoadKind::NoPattern)
return SDValue(); return SDValue();
unsigned Opc = Pattern == StridedLoadKind::Even ? HexagonISD::VPACKE unsigned Opc = Pattern == StridedLoadKind::Even ? HexagonISD::VPACKE
: HexagonISD::VPACKO; : HexagonISD::VPACKO;
return DAG.getNode(Opc, dl, VT, {Op.getOperand(1), Op.getOperand(0)}); return DAG.getNode(Opc, dl, VT, {Op.getOperand(1), Op.getOperand(0)});
} }
▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 LinesHexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
if (NElts == 2) { if (NElts == 2) {
MVT ST = VecVT.getSimpleVT(); MVT ST = VecVT.getSimpleVT();
// We are trying to concat two v2i16 to a single v4i16, or two v4i8 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
// into a single v8i8. // into a single v8i8.
if (ST == MVT::v2i16 || ST == MVT::v4i8) if (ST == MVT::v2i16 || ST == MVT::v4i8)
return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0); return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
if (UseHVX) { if (UseHVX) {
assert((Width == 64*8 && Subtarget.useHVXSglOps()) || assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) ||
(Width == 128*8 && Subtarget.useHVXDblOps())); (Width == 128 * 8 && Subtarget.useHVX128BOps()));
SDValue Vec1 = Op.getOperand(1); SDValue Vec1 = Op.getOperand(1);
MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32; MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32;
MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32; MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32;
SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0); SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1); SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0); SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
return DAG.getNode(ISD::BITCAST, dl, VT, VC); return DAG.getNode(ISD::BITCAST, dl, VT, VC);
} }
} }
if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64) if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
Show All 29 Lines
} }
SDValue SDValue
HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
EVT VT = Op.getOperand(0).getValueType(); EVT VT = Op.getOperand(0).getValueType();
SDLoc dl(Op); SDLoc dl(Op);
bool UseHVX = Subtarget.useHVXOps(); bool UseHVX = Subtarget.useHVXOps();
bool UseHVXSgl = Subtarget.useHVXSglOps(); bool UseHVX64B = Subtarget.useHVX64BOps();
// Just in case... // Just in case...
if (!VT.isVector() || !UseHVX) if (!VT.isVector() || !UseHVX)
return SDValue(); return SDValue();
EVT ResVT = Op.getValueType(); EVT ResVT = Op.getValueType();
unsigned ResSize = ResVT.getSizeInBits(); unsigned ResSize = ResVT.getSizeInBits();
unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8); unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8);
unsigned OpSize = VT.getSizeInBits(); unsigned OpSize = VT.getSizeInBits();
// We deal only with cases where the result is the vector size // We deal only with cases where the result is the vector size
// and the vector operand is a double register. // and the vector operand is a double register.
if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) || if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
!(VT.isByteSized() && OpSize == 2 * VectorSizeInBits)) !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
return SDValue(); return SDValue();
▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines case 'q': // q0-q3
break; break;
case 'v': // V0-V31 case 'v': // V0-V31
switch (VT.getSizeInBits()) { switch (VT.getSizeInBits()) {
default: default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
case 512: case 512:
return std::make_pair(0U, &Hexagon::HvxVRRegClass); return std::make_pair(0U, &Hexagon::HvxVRRegClass);
case 1024: case 1024:
if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps()) if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
return std::make_pair(0U, &Hexagon::HvxVRRegClass); return std::make_pair(0U, &Hexagon::HvxVRRegClass);
return std::make_pair(0U, &Hexagon::HvxWRRegClass); return std::make_pair(0U, &Hexagon::HvxWRRegClass);
case 2048: case 2048:
return std::make_pair(0U, &Hexagon::HvxWRRegClass); return std::make_pair(0U, &Hexagon::HvxWRRegClass);
} }
break; break;
default: default:
llvm_unreachable("Unknown asm register class"); llvm_unreachable("Unknown asm register class");
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 LinesHexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
case MVT::v8i64: case MVT::v8i64:
RRC = &Hexagon::HvxVRRegClass; RRC = &Hexagon::HvxVRRegClass;
break; break;
case MVT::v128i8: case MVT::v128i8:
case MVT::v64i16: case MVT::v64i16:
case MVT::v32i32: case MVT::v32i32:
case MVT::v16i64: case MVT::v16i64:
if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
Subtarget.useHVXDblOps()) Subtarget.useHVX128BOps())
RRC = &Hexagon::HvxVRRegClass; RRC = &Hexagon::HvxVRRegClass;
else else
RRC = &Hexagon::HvxWRRegClass; RRC = &Hexagon::HvxWRRegClass;
break; break;
case MVT::v256i8: case MVT::v256i8:
case MVT::v128i16: case MVT::v128i16:
case MVT::v64i32: case MVT::v64i32:
case MVT::v32i64: case MVT::v32i64:
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonPseudo.td

Show First 20 Lines • Show All 421 Lines • ▼ Show 20 Lineslet Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
class LDrivv_template<RegisterClass RC, InstHexagon rootInst> class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
: InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
"", [], "", rootInst.Itinerary, rootInst.Type>; "", [], "", rootInst.Itinerary, rootInst.Type>;
def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>, def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,
Requires<[HasV60T,UseHVX]>; Requires<[HasV60T,UseHVX]>;
def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>, def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,
Requires<[HasV60T,UseHVXSgl]>; Requires<[HasV60T,UseHVX]>;
def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>, def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,
Requires<[HasV60T,UseHVX]>; Requires<[HasV60T,UseHVX]>;
let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in
def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd), def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
(ins IntRegs:$Rs, s32_0Imm:$Off), "", []>, (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
Requires<[HasV60T,UseHVX]>; Requires<[HasV60T,UseHVX]>;
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonRegisterInfo.td

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lineslet Namespace = "Hexagon" in {
def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
} }
// HVX types // HVX types
def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], def VecI1
[v512i1, v1024i1, v512i1]>; : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v512i1, v512i1, v1024i1, v1024i1, v512i1]>;
[v64i8, v128i8, v64i8]>; def VecI8
def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i16, v64i16, v32i16]>; [v64i8, v64i8, v128i8, v128i8, v64i8]>;
def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], def VecI16
[v16i32, v32i32, v16i32]>; : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v32i16, v32i16, v64i16, v64i16, v32i16]>;
[v8i64, v16i64, v8i64]>; def VecI32
def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v128i8, v256i8, v128i8]>; [v16i32, v16i32, v32i32, v32i32, v16i32]>;
def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], def VecI64
[v64i16, v128i16, v64i16]>; : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v8i64, v8i64, v16i64, v16i64, v8i64]>;
[v32i32, v64i32, v32i32]>; def VecPI8
def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i64, v32i64, v16i64]>; [v128i8, v128i8, v256i8, v256i8, v128i8]>;
def VecPI16
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v64i16, v64i16, v128i16, v128i16, v64i16]>;
def VecPI32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i32, v32i32, v64i32, v64i32, v32i32]>;
def VecPI64
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i64, v16i64, v32i64, v32i64, v16i64]>;
// Register classes. // Register classes.
// //
// FIXME: the register order should be defined in terms of the preferred // FIXME: the register order should be defined in terms of the preferred
// allocation order... // allocation order...
// //
def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
(add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28),
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonSubtarget.h

Show All 40 Lines
class SDep; class SDep;
class SUnit; class SUnit;
class TargetMachine; class TargetMachine;
class Triple; class Triple;
class HexagonSubtarget : public HexagonGenSubtargetInfo { class HexagonSubtarget : public HexagonGenSubtargetInfo {
virtual void anchor(); virtual void anchor();
bool UseMemOps, UseHVXOps, UseHVXDblOps; bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
bool UseLongCalls; bool UseLongCalls;
bool ModeIEEERndNear; bool ModeIEEERndNear;
public: public:
Hexagon::ArchEnum HexagonArchVersion; Hexagon::ArchEnum HexagonArchVersion;
Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4;
/// True if the target should use Back-Skip-Back scheduling. This is the /// True if the target should use Back-Skip-Back scheduling. This is the
/// default for V60. /// default for V60.
bool UseBSBScheduling; bool UseBSBScheduling;
struct UsrOverflowMutation : public ScheduleDAGMutation { struct UsrOverflowMutation : public ScheduleDAGMutation {
void apply(ScheduleDAGInstrs *DAG) override; void apply(ScheduleDAGInstrs *DAG) override;
}; };
struct HVXMemLatencyMutation : public ScheduleDAGMutation { struct HVXMemLatencyMutation : public ScheduleDAGMutation {
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linespublic:
bool hasV62TOps() const { bool hasV62TOps() const {
return getHexagonArchVersion() >= Hexagon::ArchEnum::V62; return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
} }
bool hasV62TOpsOnly() const { bool hasV62TOpsOnly() const {
return getHexagonArchVersion() == Hexagon::ArchEnum::V62; return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
} }
bool modeIEEERndNear() const { return ModeIEEERndNear; } bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXOps() const { return UseHVXOps; } bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
bool useLongCalls() const { return UseLongCalls; } bool useLongCalls() const { return UseLongCalls; }
bool usePredicatedCalls() const; bool usePredicatedCalls() const;
bool useBSBScheduling() const { return UseBSBScheduling; } bool useBSBScheduling() const { return UseBSBScheduling; }
bool enableMachineScheduler() const override; bool enableMachineScheduler() const override;
// Always use the TargetLowering default scheduler. // Always use the TargetLowering default scheduler.
// FIXME: This will use the vliw scheduler which is probably just hurting // FIXME: This will use the vliw scheduler which is probably just hurting
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonSubtarget.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near", static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Generate non-chopped conversion from fp to int.")); cl::desc("Generate non-chopped conversion from fp to int."));
static cl::opt<bool> EnableBSBSched("enable-bsb-sched", static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(true)); cl::Hidden, cl::ZeroOrMore, cl::init(true));
static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Hexagon Double Vector eXtensions"));
static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Hexagon Vector eXtensions"));
static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched", static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(false)); cl::Hidden, cl::ZeroOrMore, cl::init(false));
static cl::opt<bool> EnableDotCurSched("enable-cur-sched", static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::init(true),
cl::desc("Enable the scheduler to generate .cur")); cl::desc("Enable the scheduler to generate .cur"));
static cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched", static cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched",
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 LinesHexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
}; };
auto FoundIt = CpuTable.find(CPUString); auto FoundIt = CpuTable.find(CPUString);
if (FoundIt != CpuTable.end()) if (FoundIt != CpuTable.end())
HexagonArchVersion = FoundIt->second; HexagonArchVersion = FoundIt->second;
else else
llvm_unreachable("Unrecognized Hexagon processor version"); llvm_unreachable("Unrecognized Hexagon processor version");
UseHVXOps = false; UseHVX128BOps = false;
UseHVXDblOps = false; UseHVX64BOps = false;
UseLongCalls = false; UseLongCalls = false;
UseMemOps = DisableMemOps ? false : EnableMemOps; UseMemOps = DisableMemOps ? false : EnableMemOps;
ModeIEEERndNear = EnableIEEERndNear; ModeIEEERndNear = EnableIEEERndNear;
UseBSBScheduling = hasV60TOps() && EnableBSBSched; UseBSBScheduling = hasV60TOps() && EnableBSBSched;
ParseSubtargetFeatures(CPUString, FS); ParseSubtargetFeatures(CPUString, FS);
if (EnableHexagonHVX.getPosition())
UseHVXOps = EnableHexagonHVX;
if (EnableHexagonHVXDouble.getPosition())
UseHVXDblOps = EnableHexagonHVXDouble;
if (OverrideLongCalls.getPosition()) if (OverrideLongCalls.getPosition())
UseLongCalls = OverrideLongCalls; UseLongCalls = OverrideLongCalls;
return *this; return *this;
} }
void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) { void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
for (SUnit &SU : DAG->SUnits) { for (SUnit &SU : DAG->SUnits) {
▲ Show 20 Lines • Show All 419 Lines • Show Last 20 Lines

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 LinesMCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU); StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU);
if (!isCPUValid(CPUName.str())) { if (!isCPUValid(CPUName.str())) {
errs() << "error: invalid CPU \"" << CPUName.str().c_str() errs() << "error: invalid CPU \"" << CPUName.str().c_str()
<< "\" specified\n"; << "\" specified\n";
return nullptr; return nullptr;
} }
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) { if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) {
llvm::FeatureBitset Features = X->getFeatureBits(); llvm::FeatureBitset Features = X->getFeatureBits();
X->setFeatureBits(Features.set(Hexagon::ExtensionHVX)); X->setFeatureBits(Features.set(Hexagon::ExtensionHVX));
} }
return X; return X;
} }
unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
static std::map<StringRef,unsigned> ElfFlags = { static std::map<StringRef,unsigned> ElfFlags = {
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/SUnit-boundary-prob.ll

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines"for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x", %"for op_vmpy_v__uh_v__uh__1.s0.y"
br i1 %62, label %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", label %"for op_vmpy_v__uh_v__uh__1.s0.x.x" br i1 %62, label %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", label %"for op_vmpy_v__uh_v__uh__1.s0.x.x"
"end for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x" "end for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x"
%63 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 1 %63 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 1
br label %"for op_vmpy_v__uh_v__uh__1.s0.y" br label %"for op_vmpy_v__uh_v__uh__1.s0.y"
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #2 = { nounwind } attributes #2 = { nounwind }
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 2, !"halide_mattrs", !"+hvx"} !0 = !{i32 2, !"halide_mattrs", !"+hvx"}
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"in_u32", !3} !2 = !{!"in_u32", !3}
!3 = !{!"Halide buffer"} !3 = !{!"Halide buffer"}
!4 = !{!5, !5, i64 0} !4 = !{!5, !5, i64 0}
!5 = !{!"in_u16", !3} !5 = !{!"in_u16", !3}
!6 = !{!7, !7, i64 0} !6 = !{!7, !7, i64 0}
!7 = !{!"op_vmpy_v__uh_v__uh__1", !3} !7 = !{!"op_vmpy_v__uh_v__uh__1", !3}

test/CodeGen/Hexagon/bit-bitsplit-at.ll

Show All 24 Linesb8: ; preds = %b4
store i8 %v3, i8* undef, align 2 store i8 %v3, i8* undef, align 2
unreachable unreachable
b9: ; preds = %b6, %b4 b9: ; preds = %b6, %b4
%v10 = phi i32 [ %v7, %b6 ], [ %v5, %b4 ] %v10 = phi i32 [ %v7, %b6 ], [ %v5, %b4 ]
ret i32 %v10 ret i32 %v10
} }
attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/bit-bitsplit-src.ll

Show All 26 Linesb0:
tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @g1, i32 0, i32 0), i64 %v8) #0 tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @g1, i32 0, i32 0), i64 %v8) #0
tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @g2, i32 0, i32 0), i64 %v12) #0 tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @g2, i32 0, i32 0), i64 %v12) #0
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0 declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/bit-bitsplit.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: bitsplit(r{{[0-9]+}},#5) ; CHECK: bitsplit(r{{[0-9]+}},#5)
target triple = "hexagon" target triple = "hexagon"
define i32 @fred(i32 %a, i32* nocapture readonly %b) local_unnamed_addr #0 { define i32 @fred(i32 %a, i32* nocapture readonly %b) local_unnamed_addr #0 {
entry: entry:
%and = and i32 %a, 31 %and = and i32 %a, 31
%shr = lshr i32 %a, 5 %shr = lshr i32 %a, 5
%arrayidx = getelementptr inbounds i32, i32* %b, i32 %shr %arrayidx = getelementptr inbounds i32, i32* %b, i32 %shr
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%shr1 = lshr i32 %0, %and %shr1 = lshr i32 %0, %and
%and2 = and i32 %shr1, 1 %and2 = and i32 %shr1, 1
ret i32 %and2 ret i32 %and2
} }
attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" }

test/CodeGen/Hexagon/bit-ext-sat.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
declare i32 @llvm.hexagon.A2.zxtb(i32) #1 declare i32 @llvm.hexagon.A2.zxtb(i32) #1
declare i32 @llvm.hexagon.A2.zxth(i32) #1 declare i32 @llvm.hexagon.A2.zxth(i32) #1
declare i32 @llvm.hexagon.A2.satb(i32) #1 declare i32 @llvm.hexagon.A2.satb(i32) #1
declare i32 @llvm.hexagon.A2.sath(i32) #1 declare i32 @llvm.hexagon.A2.sath(i32) #1
declare i32 @llvm.hexagon.A2.satub(i32) #1 declare i32 @llvm.hexagon.A2.satub(i32) #1
declare i32 @llvm.hexagon.A2.satuh(i32) #1 declare i32 @llvm.hexagon.A2.satuh(i32) #1
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/bit-extract-off.ll

Show All 13 Lines
b5: ; preds = %b5, %b4 b5: ; preds = %b5, %b4
%v6 = call double @fabs(double undef) #1 %v6 = call double @fabs(double undef) #1
store double %v6, double* undef, align 8 store double %v6, double* undef, align 8
br label %b5 br label %b5
} }
declare double @fabs(double) #1 declare double @fabs(double) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/bit-extract.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; CHECK: extract(r0,#16,#8) ; CHECK: extract(r0,#16,#8)
define i32 @sd(i32 %x) local_unnamed_addr #0 { define i32 @sd(i32 %x) local_unnamed_addr #0 {
entry: entry:
%bf.shl = shl i32 %x, 8 %bf.shl = shl i32 %x, 8
%bf.ashr = ashr i32 %bf.shl, 16 %bf.ashr = ashr i32 %bf.shl, 16
ret i32 %bf.ashr ret i32 %bf.ashr
} }
attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/bit-has.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Linesb23: ; preds = %b21
%v26 = and i32 %v25, 65534 %v26 = and i32 %v25, 65534
%v27 = or i32 %v26, 0 %v27 = or i32 %v26, 0
store i32 %v27, i32* undef, align 4 store i32 %v27, i32* undef, align 4
ret void ret void
} }
declare i32 @llvm.hexagon.A2.sath(i32) #1 declare i32 @llvm.hexagon.A2.sath(i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll

Show All 18 Lines
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret i32 0 ret i32 0
} }
declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2 declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2
declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2 declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2
attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { optsize } attributes #2 = { optsize }

test/CodeGen/Hexagon/bit-rie.ll

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #2 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #2
declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2
declare i32 @llvm.hexagon.S2.clbnorm(i32) #2 declare i32 @llvm.hexagon.S2.clbnorm(i32) #2
declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) #2 declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) #2
declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #2 declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #2
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}
!5 = distinct !{!5, !6} !5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.threadify", i32 81508608} !6 = !{!"llvm.loop.threadify", i32 81508608}
!7 = !{!8, !8, i64 0} !7 = !{!8, !8, i64 0}
!8 = !{!"short", !3, i64 0} !8 = !{!"short", !3, i64 0}
!9 = distinct !{!9, !10} !9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.threadify", i32 1441813} !10 = !{!"llvm.loop.threadify", i32 1441813}
!11 = distinct !{!11, !10} !11 = distinct !{!11, !10}

test/CodeGen/Hexagon/bitconvert-vector.ll

Show All 18 Linesentry:
%t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2) %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128 store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128
store <32 x i32> %t3, <32 x i32>* undef, align 128 store <32 x i32> %t3, <32 x i32>* undef, align 128
unreachable unreachable
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

test/CodeGen/Hexagon/build-vector-shuffle.ll

Show All 11 Linesentry:
%2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1) %2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
store <16 x i32> %2, <16 x i32>* undef, align 2 store <16 x i32> %2, <16 x i32>* undef, align 2
unreachable unreachable
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/builtin-expect.ll

Show All 33 Lines
b14: ; preds = %b13, %b10 b14: ; preds = %b13, %b10
%v15 = phi i32 [ %v12, %b10 ], [ 0, %b13 ] %v15 = phi i32 [ %v12, %b10 ], [ 0, %b13 ]
ret i32 %v15 ret i32 %v15
} }
declare i32 @bar(i32) local_unnamed_addr #0 declare i32 @bar(i32) local_unnamed_addr #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" }
!0 = !{!"branch_weights", i32 1, i32 2000} !0 = !{!"branch_weights", i32 1, i32 2000}

test/CodeGen/Hexagon/cfgopt-fall-through.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
b17: ; preds = %b15, %b14, %b13, %b12, %b6 b17: ; preds = %b15, %b14, %b13, %b12, %b6
%v18 = phi i32 [ 0, %b13 ], [ 0, %b12 ], [ %v16, %b15 ], [ 0, %b14 ], [ 0, %b6 ] %v18 = phi i32 [ 0, %b13 ], [ 0, %b12 ], [ %v16, %b15 ], [ 0, %b14 ], [ 0, %b6 ]
ret i32 %v18 ret i32 %v18
b19: ; preds = %b4 b19: ; preds = %b4
unreachable unreachable
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/cfi-offset.ll

Show All 33 Lines
declare i64 @_Z3barxxx(i64, i64, i64) #0 declare i64 @_Z3barxxx(i64, i64, i64) #0
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare i8* @__cxa_begin_catch(i8*) declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch() declare void @__cxa_end_catch()
attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/Hexagon/common-gep-inbounds.ll

Show All 11 Lines
; Function Attrs: nounwind ; Function Attrs: nounwind
define i16 @TraceBack() #0 { define i16 @TraceBack() #0 {
entry: entry:
%p = getelementptr inbounds %struct.0, %struct.0* undef, i32 0, i32 0 %p = getelementptr inbounds %struct.0, %struct.0* undef, i32 0, i32 0
%a = load i16, i16* %p %a = load i16, i16* %p
ret i16 %a ret i16 %a
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/const-pool-tf.ll

; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s ; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
; CHECK: @PCREL ; CHECK: jumpr
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @hex_h.s0.__outermost(i32 %h.stride.114) #0 { define void @hex_h.s0.__outermost(i32 %h.stride.114) #0 {
entry: entry:
br i1 undef, label %"for h.s0.y.preheader", label %call_destructor.exit, !prof !1 br i1 undef, label %"for h.s0.y.preheader", label %call_destructor.exit, !prof !1
Show All 29 Lines

test/CodeGen/Hexagon/convert-to-dot-old.ll

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
declare i32 @llvm.hexagon.A2.add(i32, i32) #2 declare i32 @llvm.hexagon.A2.add(i32, i32) #2
declare i32 @llvm.hexagon.A2.sxth(i32) #2 declare i32 @llvm.hexagon.A2.sxth(i32) #2
declare i32 @llvm.hexagon.A2.sub(i32, i32) #2 declare i32 @llvm.hexagon.A2.sub(i32, i32) #2
declare i32 @llvm.hexagon.A2.asrh(i32) #2 declare i32 @llvm.hexagon.A2.asrh(i32) #2
declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2
declare i32 @llvm.hexagon.A2.aslh(i32) #2 declare i32 @llvm.hexagon.A2.aslh(i32) #2
declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3 declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3
attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }
attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #4 = { nounwind optsize } attributes #4 = { nounwind optsize }

test/CodeGen/Hexagon/convert_const_i1_to_i8.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-NOT: .space {{[0-9][0-9][0-9][0-9]}} ; CHECK-NOT: .space {{[0-9][0-9][0-9][0-9]}}
; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}}) ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}})
define void @convert_const_i1_to_i8() #0 { define void @convert_const_i1_to_i8() #0 {
entry: entry:
%v0 = load <32 x i32>, <32 x i32>* undef, align 128 %v0 = load <32 x i32>, <32 x i32>* undef, align 128
%v1 = tail call <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32> %v0, <32 x i32> undef) %v1 = tail call <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32> %v0, <32 x i32> undef)
%v2 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef, <32 x i32> %v1) %v2 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef, <32 x i32> %v1)
store <32 x i32> %v2, <32 x i32>* null, align 128 store <32 x i32> %v2, <32 x i32>* null, align 128
ret void ret void
} }
declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>) declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>)
declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>)
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }

test/CodeGen/Hexagon/dead-store-stack.ll

; RUN: llc -O2 -march=hexagon < %s | FileCheck %s ; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s
; CHECK: ParseFunc: ; CHECK: ParseFunc:
; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])
; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]
@.str.3 = external unnamed_addr constant [8 x i8], align 1 @.str.3 = external unnamed_addr constant [8 x i8], align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @ParseFunc() local_unnamed_addr #0 { define void @ParseFunc() local_unnamed_addr #0 {
entry: entry:
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
sw.epilog: sw.epilog:
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1 declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1
attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind } attributes #2 = { nounwind }

test/CodeGen/Hexagon/early-if-merge-loop.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Linesexit: ; preds = %loop
%v61 = trunc i64 %v60 to i32 %v61 = trunc i64 %v60 to i32
ret i32 %v61 ret i32 %v61
} }
declare i64 @llvm.hexagon.A2.addp(i64, i64) #1 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
declare i64 @llvm.hexagon.A2.subp(i64, i64) #1 declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"long", !2, i64 0} !1 = !{!"long", !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/early-if-vecpi.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesif.end: ; preds = %if.then, %for.body
%incdec.ptr3 = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.1, i32 1 %incdec.ptr3 = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.1, i32 1
%exitcond = icmp eq i32 %add, 100 %exitcond = icmp eq i32 %add, 100
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %if.end for.end: ; preds = %if.end
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }

test/CodeGen/Hexagon/early-if-vecpred.ll

Show All 25 Linesb5: ; preds = %b3, %b1
%v7 = bitcast <1024 x i1> %v6 to <32 x i32> %v7 = bitcast <1024 x i1> %v6 to <32 x i32>
tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> %v7, <32 x i32>* undef, <32 x i32> undef) #2 tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> %v7, <32 x i32>* undef, <32 x i32> undef) #2
ret void ret void
} }
declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1 declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1 declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }

test/CodeGen/Hexagon/eliminate-pred-spill.ll

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1
declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #1
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/expand-condsets-dead-bad.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linesb9: ; preds = %b8, %b7
%v22 = and i32 %v21, 2147483647 %v22 = and i32 %v21, 2147483647
store i32 %v22, i32* undef, align 4 store i32 %v22, i32* undef, align 4
unreachable unreachable
b23: ; preds = %b0 b23: ; preds = %b0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/expand-condsets-dead-pred.ll

Show All 36 Linesb2: ; preds = %b2, %b1
br i1 %v19, label %b20, label %b2 br i1 %v19, label %b20, label %b2
b20: ; preds = %b2 b20: ; preds = %b2
%v21 = getelementptr inbounds [80 x i32], [80 x i32]* @x, i32 0, i32 %v16 %v21 = getelementptr inbounds [80 x i32], [80 x i32]* @x, i32 0, i32 %v16
store i32 -2000, i32* %v21, align 4 store i32 -2000, i32* %v21, align 4
br label %b1 br label %b1
} }
attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/expand-vselect-kill.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
} }
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #2 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #2
declare <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #2 declare <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #2
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }

test/CodeGen/Hexagon/expand-vstorerw-undef.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Linesb22: ; preds = %b22, %b18
%v32 = bitcast i8* %v31 to <32 x i32>* %v32 = bitcast i8* %v31 to <32 x i32>*
store <32 x i32> %v29, <32 x i32>* %v32, align 128 store <32 x i32> %v29, <32 x i32>* %v32, align 128
%v33 = icmp eq i32 0, 0 %v33 = icmp eq i32 0, 0
br i1 %v33, label %b21, label %b22 br i1 %v33, label %b21, label %b22
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" } attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #3 = { nobuiltin nounwind } attributes #3 = { nobuiltin nounwind }

test/CodeGen/Hexagon/expand-vstorerw-undef2.ll

Show First 20 Lines • Show All 204 Lines • ▼ Show 20 Linesb34: ; preds = %b34, %b24
%v144 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v142) %v144 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v142)
store <32 x i32> %v144, <32 x i32>* undef, align 128 store <32 x i32> %v144, <32 x i32>* undef, align 128
store <32 x i32> %v143, <32 x i32>* undef, align 128 store <32 x i32> %v143, <32 x i32>* undef, align 128
%v145 = add nuw nsw i32 %v38, 1 %v145 = add nuw nsw i32 %v38, 1
%v146 = icmp eq i32 %v38, undef %v146 = icmp eq i32 %v38, undef
br i1 %v146, label %b33, label %b34 br i1 %v146, label %b33, label %b34
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }
attributes #3 = { nobuiltin nounwind } attributes #3 = { nobuiltin nounwind }

test/CodeGen/Hexagon/find-loop-instr.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesb20: ; preds = %b18
br label %b21 br label %b21
b21: ; preds = %b20, %b19, %b16, %b10 b21: ; preds = %b20, %b19, %b16, %b10
%v22 = add i32 %v11, -8 %v22 = add i32 %v11, -8
%v23 = icmp eq i32 %v22, 0 %v23 = icmp eq i32 %v22, 0
br i1 %v23, label %b13, label %b10 br i1 %v23, label %b13, label %b10
} }
attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/fminmax.ll

Show All 16 Lines
entry: entry:
%call = tail call float @fmaxf(float %x, float %y) #1 %call = tail call float @fmaxf(float %x, float %y) #1
ret float %call ret float %call
} }
declare float @fminf(float, float) #0 declare float @fminf(float, float) #0
declare float @fmaxf(float, float) #0 declare float @fmaxf(float, float) #0
attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/frame-offset-overflow.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #0 declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #0
declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0 declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
declare <32 x i32> @llvm.hexagon.V6.vaddhw(<16 x i32>, <16 x i32>) #0 declare <32 x i32> @llvm.hexagon.V6.vaddhw(<16 x i32>, <16 x i32>) #0
declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0
declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/hasfp-crash1.ll

Show All 12 Lines
entry: entry:
tail call void @llvm.dbg.value(metadata i32 %a6, i64 0, metadata !51, metadata !52), !dbg !53 tail call void @llvm.dbg.value(metadata i32 %a6, i64 0, metadata !51, metadata !52), !dbg !53
ret i32 undef, !dbg !54 ret i32 undef, !dbg !54
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone speculatable } attributes #1 = { nounwind readnone speculatable }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!26, !27} !llvm.module.flags = !{!26, !27}
!llvm.linker.options = !{!29, !30, !31, !32, !29, !30, !31, !32} !llvm.linker.options = !{!29, !30, !31, !32, !29, !30, !31, !32}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "Clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !22) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "Clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !22)
!1 = !DIFile(filename: "foo.i", directory: "/path") !1 = !DIFile(filename: "foo.i", directory: "/path")
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/hasfp-crash2.ll

Show All 13 Linesentry:
tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !51, metadata !52), !dbg !53 tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !51, metadata !52), !dbg !53
tail call void @foo0(), !dbg !54 tail call void @foo0(), !dbg !54
ret void ret void
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone speculatable } attributes #1 = { nounwind readnone speculatable }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!26, !27} !llvm.module.flags = !{!26, !27}
!llvm.linker.options = !{!29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32} !llvm.linker.options = !{!29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32, !29, !30, !31, !32}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "Clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !22) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "Clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !22)
!1 = !DIFile(filename: "foo.i", directory: "/path") !1 = !DIFile(filename: "foo.i", directory: "/path")
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1
attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!llvm.ident = !{!0} !llvm.ident = !{!0}
!0 = !{!"QuIC LLVM Hexagon Clang version hexagon-clang-82-2622 (based on LLVM 5.0.0)"} !0 = !{!"QuIC LLVM Hexagon Clang version hexagon-clang-82-2622 (based on LLVM 5.0.0)"}
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}
!5 = !{!3, !3, i64 0} !5 = !{!3, !3, i64 0}

test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1
attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!llvm.ident = !{!0} !llvm.ident = !{!0}
!0 = !{!"QuIC LLVM Hexagon Clang version hexagon-clang-82-2622 (based on LLVM 5.0.0)"} !0 = !{!"QuIC LLVM Hexagon Clang version hexagon-clang-82-2622 (based on LLVM 5.0.0)"}
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}
!5 = !{!3, !3, i64 0} !5 = !{!3, !3, i64 0}

test/CodeGen/Hexagon/hvx-nontemporal.ll

Show All 14 Lines; CHECK: vmem(r3+#3):nt = v1
%add.ptr2 = getelementptr inbounds <32 x i32>, <32 x i32>* %b, i32 3 %add.ptr2 = getelementptr inbounds <32 x i32>, <32 x i32>* %b, i32 3
store <32 x i32> %1, <32 x i32>* %add.ptr2, align 128, !tbaa !1, !nontemporal !4 store <32 x i32> %1, <32 x i32>* %add.ptr2, align 128, !tbaa !1, !nontemporal !4
; CHECK: vmem(r2+#0):nt = v0 ; CHECK: vmem(r2+#0):nt = v0
store <32 x i32> %0, <32 x i32>* %a, align 128, !tbaa !1, !nontemporal !4 store <32 x i32> %0, <32 x i32>* %a, align 128, !tbaa !1, !nontemporal !4
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}
!4 = !{i32 1} !4 = !{i32 1}

test/CodeGen/Hexagon/hwloop-noreturn-call.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
noret: noret:
call void (...) %f() #1 call void (...) %f() #1
br label %for.cont br label %for.cont
} }
declare void @trap() #1 declare void @trap() #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
attributes #1 = { nounwind noreturn } attributes #1 = { nounwind noreturn }

test/CodeGen/Hexagon/hwloop-preh.ll

Show All 35 Linesreturn: ; preds = %return.loopexit, %for.cond.preheader, %entry
%retval.0 = phi i32 [ 2, %entry ], [ 0, %for.cond.preheader ], [ 0, %return.loopexit ] %retval.0 = phi i32 [ 2, %entry ], [ 0, %for.cond.preheader ], [ 0, %return.loopexit ]
ret i32 %retval.0 ret i32 %retval.0
} }
!0 = !{!"int", !1} !0 = !{!"int", !1}
!1 = !{!"omnipotent char", !2} !1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"} !2 = !{!"Simple C/C++ TBAA"}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" }

test/CodeGen/Hexagon/inline-asm-qv.ll

Show All 9 Lines
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 { define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 {
entry: entry:
%0 = tail call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1 %0 = tail call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1
store <16 x i32> %0, <16 x i32>* %p, align 64 store <16 x i32> %0, <16 x i32>* %p, align 64
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/inline-asm-vecpred128.ll

; RUN: llc -march=hexagon < %s | FileCheck %s ; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; Make sure we can handle the 'q' constraint in the 128-byte mode. ; Make sure we can handle the 'q' constraint in the 128-byte mode.
target triple = "hexagon" target triple = "hexagon"
; CHECK-LABEL: fred ; CHECK-LABEL: fred
; CHECK: if (q{{[0-3]}}) vmem ; CHECK: if (q{{[0-3]}}) vmem
define void @fred() #0 { define void @fred() #0 {
tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> undef, <32 x i32>* undef, <32 x i32> undef) #0 tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<32 x i32> undef, <32 x i32>* undef, <32 x i32> undef) #0
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

test/CodeGen/Hexagon/intrinsics/byte-store-double.ll

; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s ; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq_128B ; CHECK-LABEL: V6_vmaskedstoreq_128B
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorenq_128B ; CHECK-LABEL: V6_vmaskedstorenq_128B
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentq_128B ; CHECK-LABEL: V6_vmaskedstorentq_128B
Show All 32 Lines

test/CodeGen/Hexagon/intrinsics/byte-store.ll

; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s ; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq ; CHECK-LABEL: V6_vmaskedstoreq
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorenq ; CHECK-LABEL: V6_vmaskedstorenq
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentq ; CHECK-LABEL: V6_vmaskedstorentq
Show All 32 Lines

test/CodeGen/Hexagon/intrinsics/system_user.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
declare void @llvm.hexagon.prefetch(i8* nocapture) #1 declare void @llvm.hexagon.prefetch(i8* nocapture) #1
declare void @llvm.hexagon.Y2.dccleana(i8* nocapture readonly) #2 declare void @llvm.hexagon.Y2.dccleana(i8* nocapture readonly) #2
declare void @llvm.hexagon.Y2.dccleaninva(i8* nocapture readonly) #2 declare void @llvm.hexagon.Y2.dccleaninva(i8* nocapture readonly) #2
declare void @llvm.hexagon.Y2.dcinva(i8* nocapture readonly) #2 declare void @llvm.hexagon.Y2.dcinva(i8* nocapture readonly) #2
declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3 declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3
declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2 declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2
declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2 declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { inaccessiblemem_or_argmemonly nounwind } attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
attributes #2 = { nounwind } attributes #2 = { nounwind }
attributes #3 = { argmemonly nounwind writeonly } attributes #3 = { argmemonly nounwind writeonly }

test/CodeGen/Hexagon/jt-in-text.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linessw.bb4: ; preds = %entry
store i32 1, i32* @lane2_pwr_st, align 4 store i32 1, i32* @lane2_pwr_st, align 4
store i32 1, i32* @lane3_pwr_st, align 4 store i32 1, i32* @lane3_pwr_st, align 4
br label %sw.epilog br label %sw.epilog
sw.epilog: ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb sw.epilog: ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
ret void ret void
} }
attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
if.end437: ; preds = %if.then409, %for.body405 if.end437: ; preds = %if.then409, %for.body405
%mul431.sink = phi i32 [ %add420, %if.then409 ], [ undef, %for.body405 ] %mul431.sink = phi i32 [ %add420, %if.then409 ], [ undef, %for.body405 ]
%shr432257 = lshr i32 %mul431.sink, 15 %shr432257 = lshr i32 %mul431.sink, 15
%conv433 = trunc i32 %shr432257 to i16 %conv433 = trunc i32 %shr432257 to i16
store i16 %conv433, i16* %arrayidx412, align 2 store i16 %conv433, i16* %arrayidx412, align 2
br label %for.body405 br label %for.body405
} }
attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
b44: ; preds = %b42 b44: ; preds = %b42
%v45 = add i8 %v6, 1 %v45 = add i8 %v6, 1
br label %b3 br label %b3
b46: ; preds = %b3 b46: ; preds = %b3
ret i16 %v5 ret i16 %v5
} }
attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/loop-prefetch.ll

Show All 18 Lineswhile.body: ; preds = %entry, %while.body
store i32 %0, i32* %d.addr.03, align 4 store i32 %0, i32* %d.addr.03, align 4
%tobool = icmp eq i32 %dec, 0 %tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %while.end, label %while.body br i1 %tobool, label %while.end, label %while.body
while.end: ; preds = %while.body, %entry while.end: ; preds = %while.body, %entry
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" }

test/CodeGen/Hexagon/lower-extract-subvector.ll

Show All 37 Lines
"consume processed": ; preds = %"produce processed" "consume processed": ; preds = %"produce processed"
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

test/CodeGen/Hexagon/memops-stack.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
declare void @foo(i32*) #2 declare void @foo(i32*) #2
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #3 = { nounwind } attributes #3 = { nounwind }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll

Show All 36 Lines"consume demosaiced": ; preds = %"for demosaiced.s0.y.y"
unreachable unreachable
"consume processed": ; preds = %"produce processed" "consume processed": ; preds = %"produce processed"
ret void ret void
} }
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

test/CodeGen/Hexagon/multi-cycle.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
} }
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/newify-crash.ll

Show All 34 Lines
b18: ; preds = %b7 b18: ; preds = %b7
tail call void @f0() #0 tail call void @f0() #0
ret void ret void
} }
declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1
declare void @f0() #0 declare void @f0() #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/newvaluejump3.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Linesb20: ; preds = %b16
br i1 %v23, label %b16, label %b24 br i1 %v23, label %b16, label %b24
b24: ; preds = %b20, %b16, %b9, %b2 b24: ; preds = %b20, %b16, %b9, %b2
%v25 = phi i8* [ null, %b2 ], [ null, %b9 ], [ %v17, %b16 ], [ null, %b20 ] %v25 = phi i8* [ null, %b2 ], [ null, %b9 ], [ %v17, %b16 ], [ null, %b20 ]
ret i8* %v25 ret i8* %v25
} }
attributes #0 = { argmemonly nounwind } attributes #0 = { argmemonly nounwind }
attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }

test/CodeGen/Hexagon/peephole-kill-flags.ll

Show All 17 Lines
for.body: ; preds = %for.cond for.body: ; preds = %for.cond
unreachable unreachable
for.end13: ; preds = %for.cond for.end13: ; preds = %for.cond
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }

test/CodeGen/Hexagon/plt-rel.ll

Show All 28 Linesif.then: ; preds = %entry
store volatile i32 0, i32* @_ZL13g_usr1_called, align 4 store volatile i32 0, i32* @_ZL13g_usr1_called, align 4
br label %return br label %return
return: ; preds = %entry, %if.then return: ; preds = %entry, %if.then
%.sink = phi i1 [ true, %if.then ], [ false, %entry ] %.sink = phi i1 [ true, %if.then ], [ false, %entry ]
ret i1 %.sink ret i1 %.sink
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }

test/CodeGen/Hexagon/post-inc-aa-metadata.ll

Show All 23 Lineswhile.body: ; preds = %entry, %while.body
store <16 x i32> %0, <16 x i32>* %p.addr.03, align 64, !tbaa !1 store <16 x i32> %0, <16 x i32>* %p.addr.03, align 64, !tbaa !1
%tobool = icmp eq i32 %dec, 0 %tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %while.end, label %while.body br i1 %tobool, label %while.end, label %while.body
while.end: ; preds = %while.body, %entry while.end: ; preds = %while.body, %entry
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/propagate-vcombine.ll

Show All 36 Lines
declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #2 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #2
declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3
declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }

test/CodeGen/Hexagon/rdf-def-mask.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Linesb26: ; preds = %b3, %b1
%v27 = phi i64 [ %v25, %b3 ], [ 2147483648, %b1 ] %v27 = phi i64 [ %v25, %b3 ], [ 2147483648, %b1 ]
ret i64 %v27 ret i64 %v27
} }
declare i32 @llvm.hexagon.S2.clb(i32) #1 declare i32 @llvm.hexagon.S2.clb(i32) #1
declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1
declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1 declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1
attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll

Show All 20 Lines
} }
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind } attributes #2 = { nounwind }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}
!5 = !{i32 110, i32 129, i32 146, i32 163, i32 183} !5 = !{i32 110, i32 129, i32 146, i32 163, i32 183}

test/CodeGen/Hexagon/rdf-inline-asm.ll

Show All 18 Linesif.then: ; preds = %entry
store i32 %sub, i32* %1, align 4, !tbaa !6 store i32 %sub, i32* %1, align 4, !tbaa !6
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
%retval1.0 = phi i32 [ -1, %if.then ], [ %0, %entry ] %retval1.0 = phi i32 [ -1, %if.then ], [ %0, %entry ]
ret i32 %retval1.0 ret i32 %retval1.0
} }
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind } attributes #1 = { nounwind }
!1 = !{i32 155} !1 = !{i32 155}
!2 = !{!3, !3, i64 0} !2 = !{!3, !3, i64 0}
!3 = !{!"any pointer", !4, i64 0} !3 = !{!"any pointer", !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0} !4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C/C++ TBAA"} !5 = !{!"Simple C/C++ TBAA"}
!6 = !{!7, !7, i64 0} !6 = !{!7, !7, i64 0}
!7 = !{!"long", !4, i64 0} !7 = !{!"long", !4, i64 0}

test/CodeGen/Hexagon/reg-scavengebug-3.ll

; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s ; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vmem ; CHECK: vmem
target triple = "hexagon" target triple = "hexagon"
@vecpreds = external global [15 x <16 x i32>], align 64 @vecpreds = external global [15 x <16 x i32>], align 64
@vectors = external global [15 x <16 x i32>], align 64 @vectors = external global [15 x <16 x i32>], align 64
@vector_pairs = external global [15 x <32 x i32>], align 128 @vector_pairs = external global [15 x <32 x i32>], align 128
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Linesentry:
%3 = tail call <16 x i32> asm "nop", "=q,q,q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63, <16 x i32> %asmresult64) #1 %3 = tail call <16 x i32> asm "nop", "=q,q,q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63, <16 x i32> %asmresult64) #1
tail call void asm sideeffect "nop", "q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63) #2 tail call void asm sideeffect "nop", "q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63) #2
tail call void asm sideeffect "nop", "q,q"(<16 x i32> %asmresult64, <16 x i32> %3) #2 tail call void asm sideeffect "nop", "q,q"(<16 x i32> %asmresult64, <16 x i32> %3) #2
tail call void asm sideeffect "nop", "v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v"(<16 x i32> %asmresult29, <16 x i32> %asmresult30, <16 x i32> %asmresult31, <16 x i32> %asmresult32, <16 x i32> %asmresult33, <16 x i32> %asmresult34, <16 x i32> %asmresult35, <16 x i32> %asmresult36, <16 x i32> %asmresult37, <16 x i32> %asmresult38, <16 x i32> %asmresult39, <16 x i32> %asmresult40, <16 x i32> %asmresult41, <16 x i32> %asmresult42, <16 x i32> %asmresult43, <16 x i32> %asmresult44, <16 x i32> %asmresult45, <16 x i32> %asmresult46, <16 x i32> %asmresult47, <16 x i32> %asmresult48, <16 x i32> %asmresult49, <16 x i32> %asmresult50, <16 x i32> %asmresult51, <16 x i32> %asmresult52, <16 x i32> %asmresult53, <16 x i32> %asmresult54, <16 x i32> %asmresult55, <16 x i32> %asmresult56, <16 x i32> %asmresult57, <16 x i32> %asmresult58, <16 x i32> %asmresult59, <16 x i32> %asmresult60) #2 tail call void asm sideeffect "nop", "v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v"(<16 x i32> %asmresult29, <16 x i32> %asmresult30, <16 x i32> %asmresult31, <16 x i32> %asmresult32, <16 x i32> %asmresult33, <16 x i32> %asmresult34, <16 x i32> %asmresult35, <16 x i32> %asmresult36, <16 x i32> %asmresult37, <16 x i32> %asmresult38, <16 x i32> %asmresult39, <16 x i32> %asmresult40, <16 x i32> %asmresult41, <16 x i32> %asmresult42, <16 x i32> %asmresult43, <16 x i32> %asmresult44, <16 x i32> %asmresult45, <16 x i32> %asmresult46, <16 x i32> %asmresult47, <16 x i32> %asmresult48, <16 x i32> %asmresult49, <16 x i32> %asmresult50, <16 x i32> %asmresult51, <16 x i32> %asmresult52, <16 x i32> %asmresult53, <16 x i32> %asmresult54, <16 x i32> %asmresult55, <16 x i32> %asmresult56, <16 x i32> %asmresult57, <16 x i32> %asmresult58, <16 x i32> %asmresult59, <16 x i32> %asmresult60) #2
tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14, i32 %asmresult15, i32 %asmresult16, i32 %asmresult17, i32 %asmresult18, i32 %asmresult19, i32 %asmresult20, i32 %asmresult21, i32 %asmresult22, i32 %asmresult23, i32 %asmresult24, i32 %asmresult25, i32 %asmresult26, i32 %asmresult27, i32 %asmresult28) #2 tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14, i32 %asmresult15, i32 %asmresult16, i32 %asmresult17, i32 %asmresult18, i32 %asmresult19, i32 %asmresult20, i32 %asmresult21, i32 %asmresult22, i32 %asmresult23, i32 %asmresult24, i32 %asmresult25, i32 %asmresult26, i32 %asmresult27, i32 %asmresult28) #2
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }

test/CodeGen/Hexagon/regalloc-bad-undef.mir

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines--- |
for.end: ; preds = %if.end82, %for.body for.end: ; preds = %if.end82, %for.body
unreachable unreachable
} }
declare i32 @lrand48() #0 declare i32 @lrand48() #0
declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1 declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1
attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double" } attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
... ...
--- ---
name: main name: main
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
▲ Show 20 Lines • Show All 135 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/regalloc-block-overlap.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Linesb42: ; preds = %b40
%v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2 %v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2
%v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2 %v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2
%v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2 %v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2
%v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2
store <32 x i32> %v54, <32 x i32>* undef, align 128 store <32 x i32> %v54, <32 x i32>* undef, align 128
br label %b39 br label %b39
} }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }

test/CodeGen/Hexagon/select-instr-align.ll

; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK-LABEL: aligned_load: ; CHECK-LABEL: aligned_load:
; CHECK: = vmem({{.*}}) ; CHECK: = vmem({{.*}})
; CHECK-LABEL: aligned_store: ; CHECK-LABEL: aligned_store:
; CHECK: vmem({{.*}}) = ; CHECK: vmem({{.*}}) =
; CHECK-LABEL: unaligned_load: ; CHECK-LABEL: unaligned_load:
; CHECK: = vmemu({{.*}}) ; CHECK: = vmemu({{.*}})
; CHECK-LABEL: unaligned_store: ; CHECK-LABEL: unaligned_store:
; CHECK: vmemu({{.*}}) = ; CHECK: vmemu({{.*}}) =
Show All 22 Lines

test/CodeGen/Hexagon/stack-align-reset.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Linesb10: ; preds = %b11
br label %b7 br label %b7
b11: ; preds = %b11, %b7 b11: ; preds = %b11, %b7
br i1 undef, label %b10, label %b11 br i1 undef, label %b10, label %b11
} }
declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1 declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/store-shift.ll

Show All 36 Linesentry:
%1 = load i32, i32* %arrayidx, align 4, !tbaa !1 %1 = load i32, i32* %arrayidx, align 4, !tbaa !1
%add13 = add nsw i32 %N, 25 %add13 = add nsw i32 %N, 25
%arrayidx15 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add13, i32 %add %arrayidx15 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add13, i32 %add
store i32 %1, i32* %arrayidx15, align 4, !tbaa !1 store i32 %1, i32* %arrayidx15, align 4, !tbaa !1
store i32 5, i32* @G, align 4, !tbaa !1 store i32 5, i32* @G, align 4, !tbaa !1
ret void ret void
} }
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/switch-lut-explicit-section.ll

Show All 23 Linesswitch.lookup: ; preds = %entry
%switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x %switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x
%switch.load = load i32, i32* %switch.gep, align 4 %switch.load = load i32, i32* %switch.gep, align 4
ret i32 %switch.load ret i32 %switch.load
return: ; preds = %entry return: ; preds = %entry
ret i32 19 ret i32 19
} }
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Hexagon/switch-lut-function-section.ll

Show All 21 Linesswitch.lookup: ; preds = %entry
%switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x %switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x
%switch.load = load i32, i32* %switch.gep, align 4 %switch.load = load i32, i32* %switch.gep, align 4
ret i32 %switch.load ret i32 %switch.load
return: ; preds = %entry return: ; preds = %entry
ret i32 19 ret i32 19
} }
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Hexagon/switch-lut-multiple-functions.ll

Show All 33 Linesswitch.lookup: ; preds = %entry
%switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x %switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x
%switch.load = load i32, i32* %switch.gep, align 4 %switch.load = load i32, i32* %switch.gep, align 4
ret i32 %switch.load ret i32 %switch.load
return: ; preds = %entry return: ; preds = %entry
ret i32 19 ret i32 19
} }
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Hexagon/switch-lut-text-section.ll

Show All 18 Linesswitch.lookup: ; preds = %entry
%switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x %switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x
%switch.load = load i32, i32* %switch.gep, align 4 %switch.load = load i32, i32* %switch.gep, align 4
ret i32 %switch.load ret i32 %switch.load
return: ; preds = %entry return: ; preds = %entry
ret i32 19 ret i32 19
} }
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Hexagon/undo-dag-shift.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
define void @store_0(i32 %b, i32* nocapture %a, i32 %v) #1 { define void @store_0(i32 %b, i32* nocapture %a, i32 %v) #1 {
entry: entry:
%shr = lshr i32 %b, 5 %shr = lshr i32 %b, 5
%arrayidx = getelementptr inbounds i32, i32* %a, i32 %shr %arrayidx = getelementptr inbounds i32, i32* %a, i32 %shr
store i32 %v, i32* %arrayidx, align 4 store i32 %v, i32* %arrayidx, align 4
ret void ret void
} }
attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }
attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" }

test/CodeGen/Hexagon/v60-cur.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1 declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1 declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0} !2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"} !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/v60-vsel1.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1 declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/v60Intrins.ll

Show First 20 Lines • Show All 2,549 Lines • ▼ Show 20 Lines
declare <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32>, <32 x i32>, i32) #1 declare <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32>, <32 x i32>, i32) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/v60Vasr.ll

; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s ; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat ; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
%struct.buffer_t = type { i64, i8*, [4 x i32], [4 x i32], [4 x i32], i32, i8, i8, [6 x i8] } %struct.buffer_t = type { i64, i8*, [4 x i32], [4 x i32], [4 x i32], i32, i8, i8, [6 x i8] }
▲ Show 20 Lines • Show All 238 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/v60small.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1 declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/Hexagon/v6vec-vprint.ll

; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
; generate .long XXXX which is a vector debug print instruction. ; generate .long XXXX which is a vector debug print instruction.
; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0
; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0
; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0
; VSTPRINT: .long 0x1dffe0 ; VSTPRINT: .long 0x1dffe0
; VSTPRINT-NOT: .long 0x1dffe0 ; VSTPRINT-NOT: .long 0x1dffe0
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon" target triple = "hexagon"
Show All 26 Lines

test/CodeGen/Hexagon/vassign-to-combine.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesb2: ; preds = %b1, %entry
%17 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %16) #1 %17 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %16) #1
%18 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %17) #1 %18 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %17) #1
%19 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %18, <32 x i32> undef) #1 %19 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %18, <32 x i32> undef) #1
store <32 x i32> %19, <32 x i32>* undef, align 128 store <32 x i32> %19, <32 x i32>* undef, align 128
ret void ret void
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

test/CodeGen/Hexagon/vdmpy-halide-test.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
destructor_block: ; preds = %"for testOne.s0.x.x44.preheader", %"end for testOne.s0.x.x" destructor_block: ; preds = %"for testOne.s0.x.x44.preheader", %"end for testOne.s0.x.x"
ret i32 0 ret i32 0
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!5 = !{!6, !6, i64 0} !5 = !{!6, !6, i64 0}
!6 = !{!"inputOne", !7} !6 = !{!"inputOne", !7}
!7 = !{!"Halide buffer"} !7 = !{!"Halide buffer"}
!8 = !{!9, !9, i64 0} !8 = !{!9, !9, i64 0}
!9 = !{!"inputTwo", !7} !9 = !{!"inputTwo", !7}
!10 = !{!11, !11, i64 0} !10 = !{!11, !11, i64 0}
!11 = !{!"testOne", !7} !11 = !{!"testOne", !7}

test/CodeGen/Hexagon/vec-pred-spill1.ll

; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
; CHECK: call puts ; CHECK: call puts
; CHECK: call print_vecpred ; CHECK: call print_vecpred
; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3) ; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3)
target triple = "hexagon" target triple = "hexagon"
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

test/CodeGen/Hexagon/vec-vararg-align.ll

Show All 21 Linesb0:
%v6 = fpext float %v5 to double %v6 = fpext float %v5 to double
call void (i8*, i32, ...) @VarVec1(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str.1, i32 0, i32 0), i32 4, <16 x i32> %v2, <32 x i32> %v3, i32 %v4, double %v6) call void (i8*, i32, ...) @VarVec1(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str.1, i32 0, i32 0), i32 4, <16 x i32> %v2, <32 x i32> %v3, i32 %v4, double %v6)
ret i32 0 ret i32 0
} }
declare i32 @printf(i8*, ...) #0 declare i32 @printf(i8*, ...) #0
declare void @VarVec1(i8*, i32, ...) #0 declare void @VarVec1(i8*, i32, ...) #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }

test/CodeGen/Hexagon/vector-align.ll

; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ ; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; Check that the store to Q6VecPredResult does not get expanded into multiple ; Check that the store to Q6VecPredResult does not get expanded into multiple
; stores. There should be no memd's. This relies on the alignment specified ; stores. There should be no memd's. This relies on the alignment specified
; in the data layout string, so don't provide one here to make sure that the ; in the data layout string, so don't provide one here to make sure that the
; default one from HexagonTargetMachine is correct. ; default one from HexagonTargetMachine is correct.
; CHECK-NOT: memd ; CHECK-NOT: memd
Show All 29 Lines

test/CodeGen/Hexagon/vload-postinc-sel.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
call_destructor.exit: ; preds = %entry call_destructor.exit: ; preds = %entry
ret void ret void
} }
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }

test/CodeGen/Hexagon/vmpa-halide-test.ll

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
destructor_block: ; preds = %"for testOne.s0.x.x44.preheader", %"end for testOne.s0.x.x" destructor_block: ; preds = %"for testOne.s0.x.x44.preheader", %"end for testOne.s0.x.x"
ret i32 0 ret i32 0
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1 declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!5 = !{!6, !6, i64 0} !5 = !{!6, !6, i64 0}
!6 = !{!"inputOne", !7} !6 = !{!"inputOne", !7}
!7 = !{!"Halide buffer"} !7 = !{!"Halide buffer"}
!8 = !{!9, !9, i64 0} !8 = !{!9, !9, i64 0}
!9 = !{!"inputTwo", !7} !9 = !{!"inputTwo", !7}
!10 = !{!11, !11, i64 0} !10 = !{!11, !11, i64 0}
!11 = !{!"testOne", !7} !11 = !{!"testOne", !7}

test/CodeGen/Hexagon/vpack_eo.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesentry:
%34 = bitcast i16* %.inc52 to <16 x i32>* %34 = bitcast i16* %.inc52 to <16 x i32>*
store <16 x i32> %33, <16 x i32>* %34, align 2, !tbaa !9 store <16 x i32> %33, <16 x i32>* %34, align 2, !tbaa !9
ret i32 0 ret i32 0
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
!4 = !{!5, !5, i64 0} !4 = !{!5, !5, i64 0}
!5 = !{!"InputOne", !6} !5 = !{!"InputOne", !6}
!6 = !{!"Halide buffer"} !6 = !{!"Halide buffer"}
!7 = !{!8, !8, i64 0} !7 = !{!8, !8, i64 0}
!8 = !{!"InputTwo", !6} !8 = !{!"InputTwo", !6}
!9 = !{!10, !10, i64 0} !9 = !{!10, !10, i64 0}
!10 = !{!"Strided_LoadTest", !6} !10 = !{!"Strided_LoadTest", !6}

test/CodeGen/Hexagon/vselect-pseudo.ll

; RUN: llc -march=hexagon < %s ; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "hexagon" target triple = "hexagon"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fred() #0 { define void @fred() #0 {
entry: entry:
br label %for.body9.us br label %for.body9.us
Show All 24 Lines

test/MC/Hexagon/align.s

# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s
# Verify that the .align directive emits the proper insn packets. # Verify that the .align directive emits the proper insn packets.
{ r1 = sub(#1, r1) } { r1 = sub(#1, r1) }
# CHECK: 76414021 { r1 = sub(#1,r1) # CHECK: 76414021 { r1 = sub(#1,r1)
# CHECK-NEXT: 7f004000 nop # CHECK-NEXT: 7f004000 nop
# CHECK-NEXT: 7f004000 nop # CHECK-NEXT: 7f004000 nop
# CHECK-NEXT: 7f00c000 nop } # CHECK-NEXT: 7f00c000 nop }
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

test/MC/Hexagon/double-vector-producer.s

# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=obj %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s
{ {
v1:0 = vshuff(v1,v0,r7) v1:0 = vshuff(v1,v0,r7)
v2.w = vadd(v13.w,v15.w) v2.w = vadd(v13.w,v15.w)
v3.w = vadd(v8.w,v14.w) v3.w = vadd(v8.w,v14.w)
vmem(r2+#-2) = v0.new vmem(r2+#-2) = v0.new
} }
# CHECK: 60 61 07 1b # CHECK: 60 61 07 1b
# CHECK: 02 4d 4f 1c # CHECK: 02 4d 4f 1c
# CHECK: 03 48 4e 1c # CHECK: 03 48 4e 1c
# CHECK: 26 e6 22 28 # CHECK: 26 e6 22 28

test/MC/Hexagon/test.s

#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s #RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s
{ vmem (r0 + #0) = v0 { vmem (r0 + #0) = v0
r0 = memw(r0) } r0 = memw(r0) }
No newline at end of file

test/MC/Hexagon/v60-alu.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd } #CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd }
v23.w=vavg(v11.w,v2.w):rnd v23.w=vavg(v11.w,v2.w):rnd
#CHECK: 1cf4d323 { v3.h = vnavg(v19.h,{{ *}}v20.h) } #CHECK: 1cf4d323 { v3.h = vnavg(v19.h,{{ *}}v20.h) }
v3.h=vnavg(v19.h,v20.h) v3.h=vnavg(v19.h,v20.h)
▲ Show 20 Lines • Show All 302 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-misc.s

# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -d - | FileCheck %s # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s
.L0: .L0:
# CHECK: 5c00c000 { if (p0) jump:nt # CHECK: 5c00c000 { if (p0) jump:nt
if (p0) jump .L0 if (p0) jump .L0
# CHECK: 5cffe1fe { if (!p1) jump:nt # CHECK: 5cffe1fe { if (!p1) jump:nt
if (!p1) jump .L0 if (!p1) jump .L0
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-permute.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat } #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat }
v15.b=vpack(v21.h,v18.h):sat v15.b=vpack(v21.h,v18.h):sat
#CHECK: 1fd7d7a2 { v2.ub = vpack(v23.h{{ *}},{{ *}}v23.h):sat } #CHECK: 1fd7d7a2 { v2.ub = vpack(v23.h{{ *}},{{ *}}v23.h):sat }
v2.ub=vpack(v23.h,v23.h):sat v2.ub=vpack(v23.h,v23.h):sat
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-shift.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) } #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) }
v9.uw=vlsr(v24.uw,r15) v9.uw=vlsr(v24.uw,r15)
#CHECK: 1999d645 { v5.uh = vlsr(v22.uh,{{ *}}r25) } #CHECK: 1999d645 { v5.uh = vlsr(v22.uh,{{ *}}r25) }
v5.uh=vlsr(v22.uh,r25) v5.uh=vlsr(v22.uh,r25)
Show All 29 Lines

test/MC/Hexagon/v60-vcmp.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) } #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
q2|=vcmp.eq(v17.b,v1.b) q2|=vcmp.eq(v17.b,v1.b)
#CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) } #CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) }
q2&=vcmp.gt(v27.uw,v4.uw) q2&=vcmp.gt(v27.uw,v4.uw)
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-vmem.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 292cc11b { vmem(r12++#1) = v27 } #CHECK: 292cc11b { vmem(r12++#1) = v27 }
{ {
vmem(r12++#1)=v27 vmem(r12++#1)=v27
} }
#CHECK: 294dc319 { v25 = vmem(r13++#3):nt } #CHECK: 294dc319 { v25 = vmem(r13++#3):nt }
▲ Show 20 Lines • Show All 414 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-vmpy-acc.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat } #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat }
v23.w += vdmpy(v15:14.h,r22.uh,#1):sat v23.w += vdmpy(v15:14.h,r22.uh,#1):sat
#CHECK: 193bf90f { v15.w += vdmpy(v25.h,r27.uh):sat } #CHECK: 193bf90f { v15.w += vdmpy(v25.h,r27.uh):sat }
v15.w += vdmpy(v25.h,r27.uh):sat v15.w += vdmpy(v25.h,r27.uh):sat
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

test/MC/Hexagon/v60-vmpy1.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
#CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat } #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
v3.w=vdmpy(v3:2.h,r25.uh,#1):sat v3.w=vdmpy(v3:2.h,r25.uh,#1):sat
#CHECK: 1936de0d { v13.w = vdmpy(v30.h,{{ *}}r22.uh):sat } #CHECK: 1936de0d { v13.w = vdmpy(v30.h,{{ *}}r22.uh):sat }
v13.w=vdmpy(v30.h,r22.uh):sat v13.w=vdmpy(v30.h,r22.uh):sat
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

test/MC/Hexagon/v60lookup.s

#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ #RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
#RUN: FileCheck %s #RUN: FileCheck %s
V31.b = vlut32(V29.b, V15.b, R1) V31.b = vlut32(V29.b, V15.b, R1)
# CHECK: 1b79fd3f { v31.b = vlut32(v29.b,v15.b,r1) } # CHECK: 1b79fd3f { v31.b = vlut32(v29.b,v15.b,r1) }
V31.b |= vlut32(V29.b, V15.b, R2) V31.b |= vlut32(V29.b, V15.b, R2)
# CHECK: 1b7afdbf { v31.b |= vlut32(v29.b,v15.b,r2) } # CHECK: 1b7afdbf { v31.b |= vlut32(v29.b,v15.b,r2) }
V31:30.h = vlut16(V29.b, V15.h, R3) V31:30.h = vlut16(V29.b, V15.h, R3)
# CHECK: 1b7bfdde { v31:30.h = vlut16(v29.b,v15.h,r3) } # CHECK: 1b7bfdde { v31:30.h = vlut16(v29.b,v15.h,r3) }
v31:30.h |= vlut16(v2.b, v9.h, r4) v31:30.h |= vlut16(v2.b, v9.h, r4)
# CHECK: 1b4ce2fe { v31:30.h |= vlut16(v2.b,v9.h,r4) } # CHECK: 1b4ce2fe { v31:30.h |= vlut16(v2.b,v9.h,r4) }
v31.w = vinsert(r4) v31.w = vinsert(r4)
# CHECK: 19a4e03f { v31.w = vinsert(r4) } # CHECK: 19a4e03f { v31.w = vinsert(r4) }

test/MC/Hexagon/v62_all.s

# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -mhvx -d - | FileCheck %s
// V6_lvsplatb // V6_lvsplatb
// Vd32.b=vsplat(Rt32) // Vd32.b=vsplat(Rt32)
V0.b=vsplat(R0) V0.b=vsplat(R0)
# CHECK: 19c0c040 { v0.b = vsplat(r0) } # CHECK: 19c0c040 { v0.b = vsplat(r0) }
// V6_lvsplath // V6_lvsplath
// Vd32.h=vsplat(Rt32) // Vd32.h=vsplat(Rt32)
▲ Show 20 Lines • Show All 543 Lines • Show Last 20 Lines

test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linessw.default: ; preds = %entry
store i32 19, i32* %retval, align 4 store i32 19, i32* %retval, align 4
br label %return br label %return
return: ; preds = %sw.default, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb return: ; preds = %sw.default, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
%1 = load i32, i32* %retval, align 4 %1 = load i32, i32* %retval, align 4
ret i32 %1 ret i32 %1
} }
attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll

Show All 28 Linesentry:
%call = call i32 @foo(), !dbg !21 %call = call i32 @foo(), !dbg !21
%add = add nsw i32 %1, %call, !dbg !22 %add = add nsw i32 %1, %call, !dbg !22
ret i32 %add, !dbg !23 ret i32 %add, !dbg !23
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" }
kparzyszUnsubmitted
Not Done
ReplyInline Actions

Could you replace all occurrences of -hvx-length128b with +hvx-length64b?

kparzysz: Could you replace all occurrences of `-hvx-length128b` with `+hvx-length64b`?
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!6, !7} !llvm.module.flags = !{!6, !7}
!llvm.ident = !{!8} !llvm.ident = !{!8}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (http://llvm.org/git/clang d19a95e94dc57c5a72fd25d64f26134aa7d25fa0) (http://llvm.org/git/llvm.git 313924e6ff8a332063f61d3fda03812c220762f6)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !3) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (http://llvm.org/git/clang d19a95e94dc57c5a72fd25d64f26134aa7d25fa0) (http://llvm.org/git/llvm.git 313924e6ff8a332063f61d3fda03812c220762f6)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !3)
!1 = !DIFile(filename: "source-interleave-hexagon.c", directory: "SRC_COMPDIR") !1 = !DIFile(filename: "source-interleave-hexagon.c", directory: "SRC_COMPDIR")
Show All 27 Lines