[X86][SelectionDAG] Add support for simplifying demanded bits of target nodes. Use it to simplify demanded bits of CMOV

[craig.topper]

Summary

This adds infrastructure to support simplify demanded bits for target nodes and then uses it to support X86ISD::CMOV. This is step towards being able to promote 16-bit CMOVs to 32-bits.

[RKSimon]

A few comments but nice to see this being pursued - not sure if this will need breaking down into incremental changes at commit time.

Also, rather random question - why is SimplifyDemandedBits inside TargetLowering instead of in SelectionDAG with KnownBits/SignBits handling? Was the original intention for targets to override SimplifyDemandedBits directly?

lib/Target/X86/X86ISelLowering.cpp

27268

Do we have test cases for all of these?

27293

bracket indentation?

27312

Any easy way to remove this code duplication for Op0 and Op1?

27322

For the other 'ForTargetNode' style calls we don't do a 'drop through' to the base class - should we match that approach here?

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

27268

My primary interest was in the constant simplification. It looks like we may not have any real tests for the two recursive calls.

Maybe I'll remove those for now and add a fixme.

27322

The default implementation was less trivial than the other 2 cases so I wasn't sure if we wanted to replicate that code.

[RKSimon]

lib/Target/X86/X86ISelLowering.cpp

27322

If you drop the early break after the SimplifyDemandedBitsForTargetNode call in TargetLowering::SimplifyDemandedBits then you should be able to remove this and the extra code in TargetLowering::SimplifyDemandedBitsForTargetNode?

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

27322

But doesn't that mean we'd effectively compute the known bits and do the recursion twice when it doesn't simplify?

[RKSimon]

lib/Target/X86/X86ISelLowering.cpp

27322

Does it? I thought it'd just mean that we go through computeKnownBits to rediscover that its a target node instead of directly to computeKnownBitsForTargetNode.

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

27322

But SimplifyDemandedBitsForTarget node would have recursed and calculated known bits regardless of whether it returned true or false. If it returned false we already have the known its. If I remove the early break we'll throw that information away and recurse again through computeKnownBits right?

[RKSimon]

What state is this patch in now? Did D42088 affect it?

[craig.topper]

Rebase.

[craig.topper]

Remove the recursive calls on the cmov operands. Stick to cmov with constant inputs for now.

[craig.topper]

I don't know that we really have the test coverage to justify this approach. I have a simpler cmov patch I'm going to post.

include/llvm/Target/TargetLowering.h

public:
   ///    has multiple uses.
   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                             KnownBits &Known,
                             TargetLoweringOpt &TLO,
                             unsigned Depth = 0,
                             bool AssumeSingleUse = false) const;
 
   /// Helper wrapper around SimplifyDemandedBits
-  bool SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
+  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                             DAGCombinerInfo &DCI) const;
 
   /// Determine which of the bits specified in Mask are known to be either zero
   /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
   /// argument allows us to only collect the known bits that are shared by the
   /// requested vector elements.
   virtual void computeKnownBitsForTargetNode(const SDValue Op,
                                              KnownBits &Known,
                                              const APInt &DemandedElts,
                                              const SelectionDAG &DAG,
                                              unsigned Depth = 0) const;
 
   /// This method can be implemented by targets that want to expose additional
   /// information about sign bits to the DAG Combiner. The DemandedElts
   /// argument allows us to only collect the minimum sign bits that are shared
   /// by the requested vector elements.
   virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
                                                    const APInt &DemandedElts,
                                                    const SelectionDAG &DAG,
                                                    unsigned Depth = 0) const;
 
+  /// This method can be implemented by targets that want to perform demanded
+  /// bits simplifications on and across target nodes. If target implements
+  /// this they must always compute Known or defer back to the default
+  /// implementation.
+  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
+                                                 const APInt &DemandedMask,
+                                                 KnownBits &Known,
+                                                 TargetLoweringOpt &TLO,
+                                                 unsigned Depth) const;
+
   struct DAGCombinerInfo {
     void *DC;  // The DAG Combiner object.
     CombineLevel Level;
     bool CalledByLegalizer;
 
   public:
     SelectionDAG &DAG;
 

lib/CodeGen/SelectionDAG/TargetLowering.cpp

TargetLowering::SimplifyDemandedBits(SDNode *User, unsigned OpIdx,
   // with it.
   DCI.AddToWorklist(Op.getNode());
   // User's operands have been updated, so we may be able to do new combines
   // with it.
   DCI.AddToWorklist(User);
   return true;
 }
 
-bool TargetLowering::SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
+bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                                           DAGCombinerInfo &DCI) const {
 
   SelectionDAG &DAG = DCI.DAG;
   TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
                         !DCI.isBeforeLegalizeOps());
   KnownBits Known;
 
   bool Simplified = SimplifyDemandedBits(Op, DemandedMask, Known, TLO);
if (SimplifyDemandedBits(Op.getOperand(0), LoMask, Known2, TLO, Depth+1) ||
                                         Flags);
         return TLO.CombineTo(Op, NewOp);
       }
       return true;
     }
     LLVM_FALLTHROUGH;
   }
   default:
+    if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
+      if (SimplifyDemandedBitsForTargetNode(Op, NewMask, Known, TLO, Depth))
+        return true;
+
+      // Expect Known handled by above.
+      break;
+    }
+
     // Just use computeKnownBits to compute output bits.
     TLO.DAG.computeKnownBits(Op, Known, Depth);
     break;
   }
 
   // If we know the value of all of the demanded bits, return this as a
   // constant.
   if (NewMask.isSubsetOf(Known.Zero|Known.One)) {
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
          "Should use ComputeNumSignBits if you don't know whether Op"
          " is a target node!");
   return 1;
 }
 
+bool
+TargetLowering::SimplifyDemandedBitsForTargetNode(SDValue Op,
+                                                  const APInt &DemandedMask,
+                                                  KnownBits &Known,
+                                                  TargetLoweringOpt &TLO,
+                                                  unsigned Depth) const {
+  assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+         "Should use SimplifyDemandedBits if you don't know whether Op"
+         " is a target node!");
+  EVT VT = Op.getValueType();
+  APInt DemandedElts = VT.isVector()
+                             ? APInt::getAllOnesValue(VT.getVectorNumElements())
+                             : APInt(1, 1);
+  computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
+  return false;
+}
+
 // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
 // work with truncating build vectors and vectors with elements of less than
 // 8 bits.
 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
   if (!N)
     return false;
 
   APInt CVal;

lib/Target/X86/X86ISelLowering.h

void computeKnownBitsForTargetNode(const SDValue Op,
                                        unsigned Depth = 0) const override;
 
     /// Determine the number of bits in the operation that are sign bits.
     unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
                                              const APInt &DemandedElts,
                                              const SelectionDAG &DAG,
                                              unsigned Depth) const override;
 
+    // Simplify demanded bits for target specific nodes.
+    bool SimplifyDemandedBitsForTargetNode(SDValue Op,
+                                           const APInt &DemandedMask,
+                                           KnownBits &Known,
+                                           TargetLoweringOpt &TLO,
+                                           unsigned Depth) const override;
+
     SDValue unwrapAddress(SDValue N) const override;
 
     bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
                         int64_t &Offset) const override;
 
     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 
     bool ExpandInlineAsm(CallInst *CI) const override;

lib/Target/X86/X86ISelLowering.cpp

case X86ISD::CMOV: {
     return std::min(Tmp0, Tmp1);
   }
   }
 
   // Fallback case.
   return 1;
 }
 
+bool
+X86TargetLowering::SimplifyDemandedBitsForTargetNode(SDValue Op,
+                                                     const APInt &DemandedMask,
+                                                     KnownBits &Known,
+                                                     TargetLoweringOpt &TLO,
+                                                     unsigned Depth) const {
+  unsigned Opc = Op.getOpcode();
+  assert((Opc >= ISD::BUILTIN_OP_END ||
+          Opc == ISD::INTRINSIC_WO_CHAIN ||
+          Opc == ISD::INTRINSIC_W_CHAIN ||
+          Opc == ISD::INTRINSIC_VOID) &&
+         "Should use MaskedValueIsZero if you don't know whether Op"
+         " is a target node!");
+
+  switch (Opc) {
+  case X86ISD::CMOV: {
+    if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, Known, TLO,
+                             Depth+1))
+      return true;
+    KnownBits Known2;
+    if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, Known2, TLO,
+                             Depth+1))
+      return true;
+    assert(!Known.hasConflict() && "Bits known to be one AND zero?");
+    assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
+
+    if (auto *Op0C = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
+      const APInt &C = Op0C->getAPIntValue();
+      if (!C.isSubsetOf(DemandedMask)) {
+        SDLoc DL(Op);
+        EVT VT = Op.getValueType();
+        // Make sure we don't mess with 64-bit constants unless they fit
+        // a sign extended 32-bit value.
+        APInt NC = DemandedMask & C;
+        if (C.getMinSignedBits() > 32 || NC.getMinSignedBits() <= 32) {
+          SDValue NewC = TLO.DAG.getConstant(NC, DL, VT);
+          SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), DL, VT, NewC,
+                                          Op.getOperand(1), Op.getOperand(2),
+                                          Op.getOperand(3));
+          return TLO.CombineTo(Op, NewOp);
+      }
+      }
+    }
+
+    if (auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      const APInt &C = Op1C->getAPIntValue();
+      if (!C.isSubsetOf(DemandedMask)) {
+        SDLoc DL(Op);
+        EVT VT = Op.getValueType();
+        // Make sure we don't mess with 64-bit constants unless they fit
+        // a sign extended 32-bit value.
+        APInt NC = DemandedMask & C;
+        if (C.getMinSignedBits() > 32 || NC.getMinSignedBits() <= 32) {
+          SDValue NewC = TLO.DAG.getConstant(NC, DL, VT);
+          SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), DL, VT,
+                                          Op.getOperand(0), NewC,
+                                          Op.getOperand(2), Op.getOperand(3));
+          return TLO.CombineTo(Op, NewOp);
+        }
+      }
+    }
+
+    Known.One &= Known2.One;
+    Known.Zero &= Known2.Zero;
+    return false;
+  }
+  }
+
+  return TargetLowering::SimplifyDemandedBitsForTargetNode(Op, DemandedMask,
+                                                           Known, TLO, Depth);
+}
+
 SDValue X86TargetLowering::unwrapAddress(SDValue N) const {
   if (N->getOpcode() == X86ISD::Wrapper || N->getOpcode() == X86ISD::WrapperRIP)
     return N->getOperand(0);
   return N;
 }
 
 /// Returns true (and the GlobalValue and the offset) if the node is a
 /// GlobalAddress + offset.

test/CodeGen/X86/select.ll

 ; PR2139
 define i32 @test2() nounwind {
 ; GENERIC-LABEL: test2:
 ; GENERIC:       ## BB#0: ## %entry
 ; GENERIC-NEXT:    pushq %rax
 ; GENERIC-NEXT:    callq _return_false
 ; GENERIC-NEXT:    xorl %ecx, %ecx
 ; GENERIC-NEXT:    testb $1, %al
-; GENERIC-NEXT:    movl $-480, %eax
+; GENERIC-NEXT:    movl $536870432, %eax ## imm = 0x1FFFFE20
 ; GENERIC-NEXT:    cmovnel %ecx, %eax
 ; GENERIC-NEXT:    shll $3, %eax
 ; GENERIC-NEXT:    cmpl $32768, %eax ## imm = 0x8000
 ; GENERIC-NEXT:    jge LBB1_1
 ; GENERIC-NEXT:  ## BB#2: ## %bb91
 ; GENERIC-NEXT:    xorl %eax, %eax
 ; GENERIC-NEXT:    popq %rcx
 ; GENERIC-NEXT:    retq
 ; GENERIC-NEXT:  LBB1_1: ## %bb90
-; GENERIC-NEXT:    ## -- End function
 ;
 ; ATOM-LABEL: test2:
 ; ATOM:       ## BB#0: ## %entry
 ; ATOM-NEXT:    pushq %rax
 ; ATOM-NEXT:    callq _return_false
 ; ATOM-NEXT:    xorl %ecx, %ecx
-; ATOM-NEXT:    movl $-480, %edx
+; ATOM-NEXT:    movl $536870432, %edx ## imm = 0x1FFFFE20
 ; ATOM-NEXT:    testb $1, %al
 ; ATOM-NEXT:    cmovnel %ecx, %edx
 ; ATOM-NEXT:    shll $3, %edx
 ; ATOM-NEXT:    cmpl $32768, %edx ## imm = 0x8000
 ; ATOM-NEXT:    jge LBB1_1
 ; ATOM-NEXT:  ## BB#2: ## %bb91
 ; ATOM-NEXT:    xorl %eax, %eax
 ; ATOM-NEXT:    popq %rcx
 ; ATOM-NEXT:    retq
 ; ATOM-NEXT:  LBB1_1: ## %bb90
-; ATOM-NEXT:    ## -- End function
 ;
 ; MCU-LABEL: test2:
 ; MCU:       # BB#0: # %entry
 ; MCU-NEXT:    calll return_false
-; MCU-NEXT:    xorl    %ecx, %ecx
+; MCU-NEXT:    xorl %ecx, %ecx
 ; MCU-NEXT:    testb $1, %al
 ; MCU-NEXT:    jne .LBB1_2
 ; MCU-NEXT:  # BB#1: # %entry
-; MCU-NEXT:    movl $-480, %ecx # imm = 0xFE20
-; MCU-NEXT:  .LBB1_2:
+; MCU-NEXT:    movl $536870432, %ecx # imm = 0x1FFFFE20
+; MCU-NEXT:  .LBB1_2: # %entry
 ; MCU-NEXT:    shll $3, %ecx
 ; MCU-NEXT:    cmpl $32768, %ecx # imm = 0x8000
 ; MCU-NEXT:    jge .LBB1_3
 ; MCU-NEXT:  # BB#4: # %bb91
 ; MCU-NEXT:    xorl %eax, %eax
 ; MCU-NEXT:    retl
 ; MCU-NEXT:  .LBB1_3: # %bb90
 entry:

test/CodeGen/X86/select_const.ll

 
 ; 4294967297 = 0x100000001.
 ; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
 
 define i64 @opaque_constant(i1 %cond, i64 %x) {
 ; CHECK-LABEL: opaque_constant:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    movl $23, %ecx
+; CHECK-NEXT:    movl $1, %ecx
 ; CHECK-NEXT:    movq $-4, %rax
 ; CHECK-NEXT:    cmoveq %rcx, %rax
 ; CHECK-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
 ; CHECK-NEXT:    andq %rcx, %rax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    cmpq %rcx, %rsi
 ; CHECK-NEXT:    sete %dl
 ; CHECK-NEXT:    subq %rdx, %rax

test/CodeGen/X86/vector-compare-all_of.ll

; AVX512-NEXT:    retq
   %8 = sext i16 %7 to i32
   ret i32 %8
 }
 
 define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) {
 ; SSE-LABEL: test_v8i16_sext:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pcmpgtw %xmm1, %xmm0
-; SSE-NEXT:    pmovmskb %xmm0, %eax
-; SSE-NEXT:    xorl %ecx, %ecx
-; SSE-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; SSE-NEXT:    movl $-1, %eax
-; SSE-NEXT:    cmovnel %ecx, %eax
+; SSE-NEXT:    pmovmskb %xmm0, %ecx
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; SSE-NEXT:    cmovel %ecx, %eax
 ; SSE-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_v8i16_sext:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmovmskb %xmm0, %eax
-; AVX-NEXT:    xorl %ecx, %ecx
-; AVX-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; AVX-NEXT:    movl $-1, %eax
-; AVX-NEXT:    cmovnel %ecx, %eax
+; AVX-NEXT:    vpmovmskb %xmm0, %ecx
+; AVX-NEXT:    xorl %eax, %eax
+; AVX-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; AVX-NEXT:    cmovel %ecx, %eax
 ; AVX-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; AVX-NEXT:    retq
 ;
 ; AVX512-LABEL: test_v8i16_sext:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpcmpgtw %xmm1, %xmm0, %k0
 ; AVX512-NEXT:    vpmovm2w %k0, %xmm0
 ; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]

 }
 
 define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) {
 ; SSE-LABEL: test_v16i16_sext:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pcmpgtw %xmm3, %xmm1
 ; SSE-NEXT:    pcmpgtw %xmm2, %xmm0
 ; SSE-NEXT:    pand %xmm1, %xmm0
-; SSE-NEXT:    pmovmskb %xmm0, %eax
-; SSE-NEXT:    xorl %ecx, %ecx
-; SSE-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; SSE-NEXT:    movl $-1, %eax
-; SSE-NEXT:    cmovnel %ecx, %eax
+; SSE-NEXT:    pmovmskb %xmm0, %ecx
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; SSE-NEXT:    cmovel %ecx, %eax
 ; SSE-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: test_v16i16_sext:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
 ; AVX1-NEXT:    vpcmpgtw %xmm2, %xmm3, %xmm2

 }
 
 define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) {
 ; SSE-LABEL: test_v16i16_legal_sext:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pcmpgtw %xmm3, %xmm1
 ; SSE-NEXT:    pcmpgtw %xmm2, %xmm0
 ; SSE-NEXT:    packsswb %xmm1, %xmm0
-; SSE-NEXT:    pmovmskb %xmm0, %eax
-; SSE-NEXT:    xorl %ecx, %ecx
-; SSE-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; SSE-NEXT:    movl $-1, %eax
-; SSE-NEXT:    cmovnel %ecx, %eax
+; SSE-NEXT:    pmovmskb %xmm0, %ecx
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; SSE-NEXT:    cmovel %ecx, %eax
 ; SSE-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: test_v16i16_legal_sext:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
 ; AVX1-NEXT:    vpcmpgtw %xmm2, %xmm3, %xmm2
 ; AVX1-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpacksswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vpmovmskb %xmm0, %eax
-; AVX1-NEXT:    xorl %ecx, %ecx
-; AVX1-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; AVX1-NEXT:    movl $-1, %eax
-; AVX1-NEXT:    cmovnel %ecx, %eax
+; AVX1-NEXT:    vpmovmskb %xmm0, %ecx
+; AVX1-NEXT:    xorl %eax, %eax
+; AVX1-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; AVX1-NEXT:    cmovel %ecx, %eax
 ; AVX1-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: test_v16i16_legal_sext:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpcmpgtw %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpacksswb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpmovmskb %xmm0, %eax
-; AVX2-NEXT:    xorl %ecx, %ecx
-; AVX2-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; AVX2-NEXT:    movl $-1, %eax
-; AVX2-NEXT:    cmovnel %ecx, %eax
+; AVX2-NEXT:    vpmovmskb %xmm0, %ecx
+; AVX2-NEXT:    xorl %eax, %eax
+; AVX2-NEXT:    cmpl $65535, %ecx # imm = 0xFFFF
+; AVX2-NEXT:    cmovel %ecx, %eax
 ; AVX2-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: test_v16i16_legal_sext:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpcmpgtw %ymm1, %ymm0, %k0
 ; AVX512-NEXT:    vpmovm2b %k0, %xmm0

 
 define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) {
 ; SSE-LABEL: test_v16i8_sext:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pcmpgtb %xmm1, %xmm0
 ; SSE-NEXT:    pmovmskb %xmm0, %eax
 ; SSE-NEXT:    xorl %ecx, %ecx
 ; SSE-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; SSE-NEXT:    movl $-1, %eax
+; SSE-NEXT:    movl $255, %eax
 ; SSE-NEXT:    cmovnel %ecx, %eax
 ; SSE-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_v16i8_sext:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpcmpgtb %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpmovmskb %xmm0, %eax
 ; AVX-NEXT:    xorl %ecx, %ecx
 ; AVX-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; AVX-NEXT:    movl $-1, %eax
+; AVX-NEXT:    movl $255, %eax
 ; AVX-NEXT:    cmovnel %ecx, %eax
 ; AVX-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; AVX-NEXT:    retq
 ;
 ; AVX512-LABEL: test_v16i8_sext:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpcmpgtb %xmm1, %xmm0, %k0
 ; AVX512-NEXT:    vpmovm2b %k0, %xmm0

 ; SSE-LABEL: test_v32i8_sext:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pcmpgtb %xmm3, %xmm1
 ; SSE-NEXT:    pcmpgtb %xmm2, %xmm0
 ; SSE-NEXT:    pand %xmm1, %xmm0
 ; SSE-NEXT:    pmovmskb %xmm0, %eax
 ; SSE-NEXT:    xorl %ecx, %ecx
 ; SSE-NEXT:    cmpl $65535, %eax # imm = 0xFFFF
-; SSE-NEXT:    movl $-1, %eax
+; SSE-NEXT:    movl $255, %eax
 ; SSE-NEXT:    cmovnel %ecx, %eax
 ; SSE-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: test_v32i8_sext:
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3