[mips][mips64r6] Add R_MIPS_PC19_S2

[zoran.jovanovic]

Summary

Implemented R_MIPS_PC19_S2 relocation.

[zoran.jovanovic]

Fixed one comment, one error message nad added check for relocation address and symbol value.

[zoran.jovanovic]

Fixed option in test case.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1961–1981 ↗

(On Diff #9746)

There should only be one kind of immediate (including symbols and relocations) in the parser. Adding more causes erratic behaviour that depends on the order instructions appear in the matcher table.

Instead of adding additional parsers you should use custom predicates and/or renderers to restrict and/or convert the immediates parsed by the generic parser.

lib/Target/Mips/MipsInstrInfo.td

321 ↗

(On Diff #9746)

Delete this line. The generic parser should correctly parse constants and expressions.

[zoran.jovanovic]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1961–1981 ↗

(On Diff #9746)

Current implementation does not have method that parses immediate or symbol as instruction operand, thus it seems appropriate to implement one for pc relative instructions.
Very similar situation is with target operand of branch or jump instructions, where operand can be immediate, symbol or register, and additional parser is introduced there (MipsAsmParser::ParseJumpTarget). I did the same for operands of pc relative instructions.
I do agree that name of the method is not appropriate because both 18 and 19 bit pc relative operands will be parsed with it. I did change the name to ParsePCRelImm in following patch for R_MIPS_PC18_S3 relocation (http://reviews.llvm.org/D3890). I can do that in this patch or change name completely to avoid referencing 'pc relative'.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1961–1981 ↗

(On Diff #9746)

Current implementation does not have method that parses immediate or > symbol as instruction operand, thus it seems appropriate to implement > one for pc relative instructions.

Yes it does, it's ParseJumpTarget. 'ParseJumpTarget' is not meant to correspond to 'jumptarget' in the tablegen definitions (although admittedly this influenced the name since ParseImmOrAnyRegisterOrSymbol is rather long). It is meant to accept any input that could be used with the target of any branch-like/jump-like/call-like instruction.

Just to illustrate the problem with having multiple parsers that accept the same input tokens: One obvious bug in ParsePCRelImm is that it will parse $sp as a symbol named '$sp' rather than as a register. If this parser function is called first it will commit the assembly matcher to treating it as a symbol, even when trying to match another instruction that could accept a GPR (MipsOperand::isGPRAsmReg() will return false because the operand is a k_Immediate).

Even if you fixed that bug by adding the missing ParseAnyRegister call to ParsePCRelImm, having two identical functions will eventually lead to them diverging.

[zoran.jovanovic]

New implementation which does not introduce new parser method.

[dsanders]

Thanks. LGTM

[zoran.jovanovic]

Closed by commit rL210773 (authored by zjovanovic).

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

case Mips::fixup_Mips_PC16:
     Value -= 4;
     // The displacement is then divided by 4 to give us an 18 bit
     // address range. Forcing a signed division because Value can be negative.
     Value = (int64_t)Value / 4;
     // We now check if Value can be encoded as a 16-bit signed immediate.
     if (!isIntN(16, Value) && Ctx)
       Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
     break;
+  case Mips::fixup_MIPS_PC19_S2:
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 4;
+    // We now check if Value can be encoded as a 19-bit signed immediate.
+    if (!isIntN(19, Value) && Ctx)
+      Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup");
+    break;
   case Mips::fixup_Mips_26:
     // So far we are only using this type for jumps.
     // The displacement is then divided by 4 to give us an 28 bit
     // address range.
     Value >>= 2;
     break;
   case Mips::fixup_Mips_HI16:
   case Mips::fixup_Mips_GOT_Local:
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_Mips_GOT_OFST",     0,     16,   0 },
     { "fixup_Mips_GOT_DISP",     0,     16,   0 },
     { "fixup_Mips_HIGHER",       0,     16,   0 },
     { "fixup_Mips_HIGHEST",      0,     16,   0 },
     { "fixup_Mips_GOT_HI16",     0,     16,   0 },
     { "fixup_Mips_GOT_LO16",     0,     16,   0 },
     { "fixup_Mips_CALL_HI16",    0,     16,   0 },
     { "fixup_Mips_CALL_LO16",    0,     16,   0 },
+    { "fixup_MIPS_PC19_S2",      0,     19,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC21_S2",      0,     21,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC26_S2",      0,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
     { "fixup_MICROMIPS_HI16",    0,     16,   0 },
     { "fixup_MICROMIPS_LO16",    0,     16,   0 },
     { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_Mips_GOT_OFST",    16,     16,   0 },
     { "fixup_Mips_GOT_DISP",    16,     16,   0 },
     { "fixup_Mips_HIGHER",      16,     16,   0 },
     { "fixup_Mips_HIGHEST",     16,     16,   0 },
     { "fixup_Mips_GOT_HI16",    16,     16,   0 },
     { "fixup_Mips_GOT_LO16",    16,     16,   0 },
     { "fixup_Mips_CALL_HI16",   16,     16,   0 },
     { "fixup_Mips_CALL_LO16",   16,     16,   0 },
+    { "fixup_MIPS_PC19_S2",     13,     19,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC21_S2",     11,     21,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PC26_S2",      6,     26,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCHI16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MIPS_PCLO16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   6,     26,   0 },
     { "fixup_MICROMIPS_HI16",   16,     16,   0 },
     { "fixup_MICROMIPS_LO16",   16,     16,   0 },
     { "fixup_MICROMIPS_GOT16",  16,     16,   0 },

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
     Type = ELF::R_MICROMIPS_TLS_DTPREL_LO16;
     break;
   case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
     Type = ELF::R_MICROMIPS_TLS_TPREL_HI16;
     break;
   case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
     Type = ELF::R_MICROMIPS_TLS_TPREL_LO16;
     break;
+  case Mips::fixup_MIPS_PC19_S2:
+    Type = ELF::R_MIPS_PC19_S2;
+    break;
   case Mips::fixup_MIPS_PC21_S2:
     Type = ELF::R_MIPS_PC21_S2;
     break;
   case Mips::fixup_MIPS_PC26_S2:
     Type = ELF::R_MIPS_PC26_S2;
     break;
   case Mips::fixup_MIPS_PCHI16:
     Type = ELF::R_MIPS_PCHI16;

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
     fixup_Mips_GOT_LO16,
 
     // resulting in - R_MIPS_CALL_HI16
     fixup_Mips_CALL_HI16,
 
     // resulting in - R_MIPS_CALL_LO16
     fixup_Mips_CALL_LO16,
 
+    // resulting in - R_MIPS_PC19_S2
+    fixup_MIPS_PC19_S2,
+
     // resulting in - R_MIPS_PC21_S2
     fixup_MIPS_PC21_S2,
 
     // resulting in - R_MIPS_PC26_S2
     fixup_MIPS_PC26_S2,
 
     // resulting in - R_MIPS_PCHI16
     fixup_MIPS_PCHI16,

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
   // The immediate is encoded as 'immediate - 1'.
   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
 }
 
 unsigned
 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
                                          SmallVectorImpl<MCFixup> &Fixups,
                                          const MCSubtargetInfo &STI) const {
-  assert(MI.getOperand(OpNo).isImm());
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm()) {
     // The immediate is encoded as 'immediate << 2'.
-  unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
+    unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
     assert((Res & 3) == 0);
     return Res >> 2;
   }
 
+  assert(MO.isExpr() &&
+         "getSimm19Lsl2Encoding expects only expressions or an immediate");
+
+  const MCExpr *Expr = MO.getExpr();
+  Fixups.push_back(MCFixup::Create(0, Expr,
+                                   MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
+  return 0;
+}
+
 unsigned
 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
                                          SmallVectorImpl<MCFixup> &Fixups,
                                          const MCSubtargetInfo &STI) const {
   assert(MI.getOperand(OpNo).isImm());
   // The immediate is encoded as 'immediate << 3'.
   unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
   assert((Res & 7) == 0);
   return Res >> 3;
 }
 
 #include "MipsGenMCCodeEmitter.inc"

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 
 def simm16      : Operand<i32> {
   let DecoderMethod= "DecodeSimm16";
 }
 
 def simm19_lsl2 : Operand<i32> {
   let EncoderMethod = "getSimm19Lsl2Encoding";
   let DecoderMethod = "DecodeSimm19Lsl2";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
 def simm18_lsl3 : Operand<i32> {
   let EncoderMethod = "getSimm18Lsl3Encoding";
   let DecoderMethod = "DecodeSimm18Lsl3";
 }
 
 def simm20      : Operand<i32> {

llvm/trunk/test/MC/Mips/mips32r6/relocations.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
 # RUN:   | FileCheck %s -check-prefix=CHECK-FIXUP
 # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
 # RUN:   | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
 #------------------------------------------------------------------------------
 # Check that the assembler can handle the documented syntax for fixups.
 #------------------------------------------------------------------------------
+# CHECK-FIXUP: addiupc $2, bar  # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP:                  # fixup A - offset: 0,
+# CHECK-FIXUP:                    value: bar, kind: fixup_MIPS_PC19_S2
 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_PC16
 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_PC16
 # CHECK-FIXUP: beqzc $9, bar    # encoding: [0xd9,0b001AAAAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,

 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar)    # encoding: [0xec,0x5f,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_HI16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCHI16
 # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_LO16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lwpc    $2, bar  # encoding: [0xec,0b01001AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: lwupc   $2, bar  # encoding: [0xec,0b01010AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
-# CHECK-ELF:     0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF:     0x0 R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0x4 R_MIPS_PC16 bar 0x0
-# CHECK-ELF:     0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF:     0x8 R_MIPS_PC16 bar 0x0
 # CHECK-ELF:     0xC R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF:     0x10 R_MIPS_PC21_S2 bar 0x0
 # CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF:     0x18 R_MIPS_PCHI16 bar 0x0
-# CHECK-ELF:     0x1C R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF:     0x18 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF:     0x1C R_MIPS_PCHI16 bar 0x0
+# CHECK-ELF:     0x20 R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF:     0x24 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF: ]
 
+  addiupc   $2,bar
   beqc  $5, $6, bar
   bnec  $5, $6, bar
   beqzc $9, bar
   bnezc $9, bar
   balc  bar
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
+  lwpc      $2,bar
+  lwupc     $2,bar

llvm/trunk/test/MC/Mips/mips64r6/relocations.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
 # RUN:   | FileCheck %s -check-prefix=CHECK-FIXUP
 # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
 # RUN:   | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
 #------------------------------------------------------------------------------
 # Check that the assembler can handle the documented syntax for fixups.
 #------------------------------------------------------------------------------
-# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
+# CHECK-FIXUP: addiupc $2, bar  # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: beqc     $5, $6, bar # encoding: [0x20,0xa6,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_PC16
 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_PC16
 # CHECK-FIXUP: beqzc $9, bar    # encoding: [0xd9,0b001AAAAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC21_S2

 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar)    # encoding: [0xec,0x5f,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_HI16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCHI16
 # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: bar@PCREL_LO16,
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lwpc    $2, bar  # encoding: [0xec,0b01001AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
+# CHECK-FIXUP: lwupc   $2, bar  # encoding: [0xec,0b01010AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
-# CHECK-ELF:     0x0 R_MIPS_PC16 bar 0x0
+# CHECK-ELF:     0x0 R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0x4 R_MIPS_PC16 bar 0x0
-# CHECK-ELF:     0x8 R_MIPS_PC21_S2 bar 0x0
+# CHECK-ELF:     0x8 R_MIPS_PC16 bar 0x0
 # CHECK-ELF:     0xC R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF:     0x10 R_MIPS_PC21_S2 bar 0x0
 # CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF:     0x18 R_MIPS_PCHI16 bar 0x0
-# CHECK-ELF:     0x1C R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF:     0x18 R_MIPS_PC26_S2 bar 0x0
+# CHECK-ELF:     0x1C R_MIPS_PCHI16 bar 0x0
+# CHECK-ELF:     0x20 R_MIPS_PCLO16 bar 0x0
+# CHECK-ELF:     0x24 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF: ]
 
+  addiupc   $2,bar
   beqc  $5, $6, bar
   bnec  $5, $6, bar
   beqzc $9, bar
   bnezc $9, bar
   balc  bar
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
+  lwpc  $2,bar
+  lwupc $2,bar