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Differential D38638

[MC] Suppress .Lcfi labels when emitting textual assembly
ClosedPublic

Authored by rnk on Oct 6 2017, 11:03 AM.

Details

Reviewers
majnemer
MatzeB
Commits
rGab23dace5673: [MC] Suppress .Lcfi labels when emitting textual assembly
rL315259: [MC] Suppress .Lcfi labels when emitting textual assembly
Summary

This suppresses the generation of .Lcfi labels in our textual assembler.
It was annoying that this generated cascading .Lcfi labels:

llc foo.ll -o - | llvm-mc | llvm-mc

After three trips through MCAsmStreamer, we'd have three labels in the
output when none are necessary. We should only bother creating the
labels and frame data when making a real object file.

This supercedes D38605, which moved the entire .seh_ implementation into
MCObjectStreamer.

This has the advantage that we do more checking when emitting textual
assembly, as a minor efficiency cost. Outputting textual assembly is not
performance critical, so this shouldn't matter.

Diff Detail

Repository
rL LLVM

Event Timeline

rnk created this revision.Oct 6 2017, 11:03 AM
Herald added subscribers: JDevlieghere, hiraditya, eraman and 3 others. · View Herald TranscriptOct 6 2017, 11:03 AM
Closed by commit rL315259: [MC] Suppress .Lcfi labels when emitting textual assembly (authored by rnk). · Explain WhyOct 9 2017, 5:58 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 118301

llvm/trunk/include/llvm/MC/MCObjectStreamer.h

Show All 37 Linesclass MCObjectStreamer : public MCStreamer {
MCSection::iterator CurInsertionPoint; MCSection::iterator CurInsertionPoint;
bool EmitEHFrame; bool EmitEHFrame;
bool EmitDebugFrame; bool EmitDebugFrame;
SmallVector<MCSymbol *, 2> PendingLabels; SmallVector<MCSymbol *, 2> PendingLabels;
virtual void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0; virtual void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0;
void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
MCSymbol *EmitCFILabel() override;
protected: protected:
MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS,
MCCodeEmitter *Emitter); MCCodeEmitter *Emitter);
~MCObjectStreamer() override; ~MCObjectStreamer() override;
public: public:
/// state management /// state management
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

llvm/trunk/include/llvm/MC/MCStreamer.h

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
class MCStreamer { class MCStreamer {
MCContext &Context; MCContext &Context;
std::unique_ptr<MCTargetStreamer> TargetStreamer; std::unique_ptr<MCTargetStreamer> TargetStreamer;
std::vector<MCDwarfFrameInfo> DwarfFrameInfos; std::vector<MCDwarfFrameInfo> DwarfFrameInfos;
MCDwarfFrameInfo *getCurrentDwarfFrameInfo(); MCDwarfFrameInfo *getCurrentDwarfFrameInfo();
void EnsureValidDwarfFrame(); void EnsureValidDwarfFrame();
MCSymbol *EmitCFILabel();
MCSymbol *EmitCFICommon(); MCSymbol *EmitCFICommon();
/// Similar to DwarfFrameInfos, but for SEH unwind info. Chained frames may /// Similar to DwarfFrameInfos, but for SEH unwind info. Chained frames may
/// refer to each other, so use std::unique_ptr to provide pointer stability. /// refer to each other, so use std::unique_ptr to provide pointer stability.
std::vector<std::unique_ptr<WinEH::FrameInfo>> WinFrameInfos; std::vector<std::unique_ptr<WinEH::FrameInfo>> WinFrameInfos;
WinEH::FrameInfo *CurrentWinFrameInfo; WinEH::FrameInfo *CurrentWinFrameInfo;
void EnsureValidWinFrameInfo(); void EnsureValidWinFrameInfo();
Show All 13 Linesclass MCStreamer {
unsigned NextWinCFIID = 0; unsigned NextWinCFIID = 0;
protected: protected:
MCStreamer(MCContext &Ctx); MCStreamer(MCContext &Ctx);
virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame); virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame); virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame);
/// When emitting an object file, create and emit a real label. When emitting
/// textual assembly, this should do nothing to avoid polluting our output.
virtual MCSymbol *EmitCFILabel();
WinEH::FrameInfo *getCurrentWinFrameInfo() { WinEH::FrameInfo *getCurrentWinFrameInfo() {
return CurrentWinFrameInfo; return CurrentWinFrameInfo;
} }
virtual void EmitWindowsUnwindTables(); virtual void EmitWindowsUnwindTables();
virtual void EmitRawTextImpl(StringRef String); virtual void EmitRawTextImpl(StringRef String);
▲ Show 20 Lines • Show All 700 Lines • Show Last 20 Lines

llvm/trunk/lib/MC/MCObjectStreamer.cpp

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines if (Value->evaluateAsAbsolute(AbsValue, getAssembler())) {
return; return;
} }
DF->getFixups().push_back( DF->getFixups().push_back(
MCFixup::create(DF->getContents().size(), Value, MCFixup::create(DF->getContents().size(), Value,
MCFixup::getKindForSize(Size, false), Loc)); MCFixup::getKindForSize(Size, false), Loc));
DF->getContents().resize(DF->getContents().size() + Size, 0); DF->getContents().resize(DF->getContents().size() + Size, 0);
} }
MCSymbol *MCObjectStreamer::EmitCFILabel() {
MCSymbol *Label = getContext().createTempSymbol("cfi", true);
EmitLabel(Label);
return Label;
}
void MCObjectStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { void MCObjectStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) {
// We need to create a local symbol to avoid relocations. // We need to create a local symbol to avoid relocations.
Frame.Begin = getContext().createTempSymbol(); Frame.Begin = getContext().createTempSymbol();
EmitLabel(Frame.Begin); EmitLabel(Frame.Begin);
} }
void MCObjectStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { void MCObjectStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) {
Frame.End = getContext().createTempSymbol(); Frame.End = getContext().createTempSymbol();
▲ Show 20 Lines • Show All 451 Lines • Show Last 20 Lines

llvm/trunk/lib/MC/MCStreamer.cpp

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Linesvoid MCStreamer::EmitCFIEndProc() {
EnsureValidDwarfFrame(); EnsureValidDwarfFrame();
MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo();
EmitCFIEndProcImpl(*CurFrame); EmitCFIEndProcImpl(*CurFrame);
} }
void MCStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { void MCStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) {
// Put a dummy non-null value in Frame.End to mark that this frame has been // Put a dummy non-null value in Frame.End to mark that this frame has been
// closed. // closed.
Frame.End = (MCSymbol *) 1; Frame.End = (MCSymbol *)1;
} }
MCSymbol *MCStreamer::EmitCFILabel() { MCSymbol *MCStreamer::EmitCFILabel() {
MCSymbol *Label = getContext().createTempSymbol("cfi", true); // Return a dummy non-null value so that label fields appear filled in when
EmitLabel(Label); // generating textual assembly.
return Label; return (MCSymbol *)1;
} }
MCSymbol *MCStreamer::EmitCFICommon() { MCSymbol *MCStreamer::EmitCFICommon() {
EnsureValidDwarfFrame(); EnsureValidDwarfFrame();
return EmitCFILabel(); return EmitCFILabel();
} }
void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
▲ Show 20 Lines • Show All 357 Lines • ▼ Show 20 Lines
} }
void MCStreamer::EmitWindowsUnwindTables() { void MCStreamer::EmitWindowsUnwindTables() {
} }
void MCStreamer::Finish() { void MCStreamer::Finish() {
if (!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End) if (!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End)
report_fatal_error("Unfinished frame!"); report_fatal_error("Unfinished frame!");
if (!WinFrameInfos.empty() && !WinFrameInfos.back()->End)
report_fatal_error("Unfinished frame!");
MCTargetStreamer *TS = getTargetStreamer(); MCTargetStreamer *TS = getTargetStreamer();
if (TS) if (TS)
TS->finish(); TS->finish();
FinishImpl(); FinishImpl();
} }
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll

; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST
; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s
; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING ; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING
; CHECK-ENCODING-NOT: <unknown> ; CHECK-ENCODING-NOT: <unknown>
; CHECK-ENCODING: mov x16, #281470681743360 ; CHECK-ENCODING: mov x16, #281470681743360
; CHECK-ENCODING: movk x16, #57005, lsl #16 ; CHECK-ENCODING: movk x16, #57005, lsl #16
; CHECK-ENCODING: movk x16, #48879 ; CHECK-ENCODING: movk x16, #48879
; One argument will be passed in register, the other will be pushed on the stack. ; One argument will be passed in register, the other will be pushed on the stack.
; Return value in x0. ; Return value in x0.
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen: ; CHECK-LABEL: jscall_patchpoint_codegen:
; CHECK: Lcfi
; CHECK: str x{{.+}}, [sp] ; CHECK: str x{{.+}}, [sp]
; CHECK-NEXT: mov x0, x{{.+}} ; CHECK-NEXT: mov x0, x{{.+}}
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: mov x16, #281470681743360 ; CHECK-NEXT: mov x16, #281470681743360
; CHECK: movk x16, #57005, lsl #16 ; CHECK: movk x16, #57005, lsl #16
; CHECK: movk x16, #48879 ; CHECK: movk x16, #48879
; CHECK-NEXT: blr x16 ; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen: ; FAST-LABEL: jscall_patchpoint_codegen:
; FAST: Lcfi
; FAST: str x{{.+}}, [sp] ; FAST: str x{{.+}}, [sp]
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: mov x16, #281470681743360 ; FAST-NEXT: mov x16, #281470681743360
; FAST-NEXT: movk x16, #57005, lsl #16 ; FAST-NEXT: movk x16, #57005, lsl #16
; FAST-NEXT: movk x16, #48879 ; FAST-NEXT: movk x16, #48879
; FAST-NEXT: blr x16 ; FAST-NEXT: blr x16
%resolveCall2 = inttoptr i64 281474417671919 to i8* %resolveCall2 = inttoptr i64 281474417671919 to i8*
%result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
%resolveCall3 = inttoptr i64 244837814038255 to i8* %resolveCall3 = inttoptr i64 244837814038255 to i8*
tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result) tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
ret void ret void
} }
; Test if the arguments are properly aligned and that we don't store undef arguments. ; Test if the arguments are properly aligned and that we don't store undef arguments.
define i64 @jscall_patchpoint_codegen2(i64 %callee) { define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen2: ; CHECK-LABEL: jscall_patchpoint_codegen2:
; CHECK: Lcfi
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK-NEXT: str x[[REG]], [sp, #24] ; CHECK-NEXT: str x[[REG]], [sp, #24]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK-NEXT: str w[[REG]], [sp, #16] ; CHECK-NEXT: str w[[REG]], [sp, #16]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
; CHECK-NEXT: str x[[REG]], [sp] ; CHECK-NEXT: str x[[REG]], [sp]
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: mov x16, #281470681743360 ; CHECK-NEXT: mov x16, #281470681743360
; CHECK-NEXT: movk x16, #57005, lsl #16 ; CHECK-NEXT: movk x16, #57005, lsl #16
; CHECK-NEXT: movk x16, #48879 ; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16 ; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen2: ; FAST-LABEL: jscall_patchpoint_codegen2:
; FAST: Lcfi
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: str [[REG1]], [sp]
; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: str [[REG2]], [sp, #16]
; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST-NEXT: str [[REG3]], [sp, #24]
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: mov x16, #281470681743360 ; FAST-NEXT: mov x16, #281470681743360
; FAST-NEXT: movk x16, #57005, lsl #16 ; FAST-NEXT: movk x16, #57005, lsl #16
; FAST-NEXT: movk x16, #48879 ; FAST-NEXT: movk x16, #48879
; FAST-NEXT: blr x16 ; FAST-NEXT: blr x16
%call = inttoptr i64 281474417671919 to i8* %call = inttoptr i64 281474417671919 to i8*
%result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
ret i64 %result ret i64 %result
} }
; Test if the arguments are properly aligned and that we don't store undef arguments. ; Test if the arguments are properly aligned and that we don't store undef arguments.
define i64 @jscall_patchpoint_codegen3(i64 %callee) { define i64 @jscall_patchpoint_codegen3(i64 %callee) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen3: ; CHECK-LABEL: jscall_patchpoint_codegen3:
; CHECK: Lcfi
; CHECK: mov w[[REG:[0-9]+]], #10 ; CHECK: mov w[[REG:[0-9]+]], #10
; CHECK-NEXT: str x[[REG]], [sp, #48] ; CHECK-NEXT: str x[[REG]], [sp, #48]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
; CHECK-NEXT: str w[[REG]], [sp, #36] ; CHECK-NEXT: str w[[REG]], [sp, #36]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK-NEXT: str x[[REG]], [sp, #24] ; CHECK-NEXT: str x[[REG]], [sp, #24]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK-NEXT: str w[[REG]], [sp, #16] ; CHECK-NEXT: str w[[REG]], [sp, #16]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
; CHECK-NEXT: str x[[REG]], [sp] ; CHECK-NEXT: str x[[REG]], [sp]
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: mov x16, #281470681743360 ; CHECK-NEXT: mov x16, #281470681743360
; CHECK-NEXT: movk x16, #57005, lsl #16 ; CHECK-NEXT: movk x16, #57005, lsl #16
; CHECK-NEXT: movk x16, #48879 ; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16 ; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen3: ; FAST-LABEL: jscall_patchpoint_codegen3:
; FAST: Lcfi
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8 ; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8
; FAST-NEXT: mov [[REG5:x[0-9]+]], #10 ; FAST-NEXT: mov [[REG5:x[0-9]+]], #10
; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: str [[REG1]], [sp]
; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: str [[REG2]], [sp, #16]
; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST-NEXT: str [[REG3]], [sp, #24]
Show All 22 Lines

llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll

Show All 25 Lines
; A cfi directive cannot point to the end of a function. ; A cfi directive cannot point to the end of a function.
; LINUX-FP: func: ; LINUX-FP: func:
; LINUX-FP-NEXT: {{^}}.L[[BEGIN:.*]]:{{$}} ; LINUX-FP-NEXT: {{^}}.L[[BEGIN:.*]]:{{$}}
; LINUX-FP-NEXT: .cfi_startproc ; LINUX-FP-NEXT: .cfi_startproc
; LINUX-FP-NEXT: {{^}}# ; LINUX-FP-NEXT: {{^}}#
; LINUX-FP-NEXT: stwu 1, -16(1) ; LINUX-FP-NEXT: stwu 1, -16(1)
; LINUX-FP-NEXT: stw 31, 12(1) ; LINUX-FP-NEXT: stw 31, 12(1)
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .cfi_def_cfa_offset 16 ; LINUX-FP-NEXT: .cfi_def_cfa_offset 16
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .cfi_offset r31, -4 ; LINUX-FP-NEXT: .cfi_offset r31, -4
; LINUX-FP-NEXT: mr 31, 1 ; LINUX-FP-NEXT: mr 31, 1
; LINUX-FP-NEXT: {{^}}.L[[END:.*]]:{{$}} ; LINUX-FP-NEXT: {{^}}.L[[END:.*]]:{{$}}
; LINUX-FP-NEXT: .size func, .L[[END]]-.L[[BEGIN]] ; LINUX-FP-NEXT: .size func, .L[[END]]-.L[[BEGIN]]
; LINUX-FP-NEXT: .cfi_endproc ; LINUX-FP-NEXT: .cfi_endproc

llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
} }
define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) { define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) {
; CHECK-LABEL: length2_eq_nobuiltin_attr: ; CHECK-LABEL: length2_eq_nobuiltin_attr:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: bl memcmp ; CHECK-NEXT: bl memcmp
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin %m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin
%c = icmp eq i32 %m, 0 %c = icmp eq i32 %m, 0
ret i1 %c ret i1 %c
} }

llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesentry:
store <2 x float> %0, <2 x float>* undef store <2 x float> %0, <2 x float>* undef
ret void ret void
} }
define void @full_test() { define void @full_test() {
; X32-LABEL: full_test: ; X32-LABEL: full_test:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; X32-NEXT: cvttps2dq %xmm2, %xmm0 ; X32-NEXT: cvttps2dq %xmm2, %xmm0
; X32-NEXT: cvtdq2ps %xmm0, %xmm1 ; X32-NEXT: cvtdq2ps %xmm0, %xmm1
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: cmpltps %xmm2, %xmm0 ; X32-NEXT: cmpltps %xmm2, %xmm0
; X32-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u> ; X32-NEXT: movaps {{.*#+}} xmm3 = <1,1,u,u>
; X32-NEXT: addps %xmm1, %xmm3 ; X32-NEXT: addps %xmm1, %xmm3
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llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
; RUN: llc -mtriple=i386-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 ; RUN: llc -mtriple=i386-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
define i64 @test_add_i64(i64 %arg1, i64 %arg2) { define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
; X64-LABEL: test_add_i64: ; X64-LABEL: test_add_i64:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: leaq (%rsi,%rdi), %rax ; X64-NEXT: leaq (%rsi,%rdi), %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: test_add_i64: ; X32-LABEL: test_add_i64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: movl 16(%ebp), %eax ; X32-NEXT: movl 16(%ebp), %eax
; X32-NEXT: movl 20(%ebp), %edx ; X32-NEXT: movl 20(%ebp), %edx
; X32-NEXT: addl 8(%ebp), %eax ; X32-NEXT: addl 8(%ebp), %eax
; X32-NEXT: adcl 12(%ebp), %edx ; X32-NEXT: adcl 12(%ebp), %edx
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: retl ; X32-NEXT: retl
%ret = add i64 %arg1, %arg2 %ret = add i64 %arg1, %arg2
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llvm/trunk/test/CodeGen/X86/GlobalISel/brcond.ll

Show All 15 Lines
; X64-NEXT: .LBB0_2: # %if.else ; X64-NEXT: .LBB0_2: # %if.else
; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) ; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: test_1: ; X32-LABEL: test_1:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; X32-NEXT: cmpl %eax, {{[0-9]+}}(%esp)
; X32-NEXT: setl %al ; X32-NEXT: setl %al
; X32-NEXT: testb $1, %al ; X32-NEXT: testb $1, %al
; X32-NEXT: je .LBB0_2 ; X32-NEXT: je .LBB0_2
; X32-NEXT: # BB#1: # %if.then ; X32-NEXT: # BB#1: # %if.then
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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llvm/trunk/test/CodeGen/X86/GlobalISel/callingconv.ll

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
ret <4 x i32> %arg2 ret <4 x i32> %arg2
} }
define <8 x i32> @test_v8i32_args(<8 x i32> %arg1, <8 x i32> %arg2) { define <8 x i32> @test_v8i32_args(<8 x i32> %arg1, <8 x i32> %arg2) {
; X32-LABEL: test_v8i32_args: ; X32-LABEL: test_v8i32_args:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movups 16(%esp), %xmm1 ; X32-NEXT: movups 16(%esp), %xmm1
; X32-NEXT: movaps %xmm2, %xmm0 ; X32-NEXT: movaps %xmm2, %xmm0
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_v8i32_args: ; X64-LABEL: test_v8i32_args:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: movaps %xmm2, %xmm0 ; X64-NEXT: movaps %xmm2, %xmm0
; X64-NEXT: movaps %xmm3, %xmm1 ; X64-NEXT: movaps %xmm3, %xmm1
; X64-NEXT: retq ; X64-NEXT: retq
ret <8 x i32> %arg2 ret <8 x i32> %arg2
} }
declare void @trivial_callee() declare void @trivial_callee()
define void @test_trivial_call() { define void @test_trivial_call() {
; X32-LABEL: test_trivial_call: ; X32-LABEL: test_trivial_call:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: calll trivial_callee ; X32-NEXT: calll trivial_callee
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_trivial_call: ; X64-LABEL: test_trivial_call:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi0:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: callq trivial_callee ; X64-NEXT: callq trivial_callee
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
call void @trivial_callee() call void @trivial_callee()
ret void ret void
} }
declare void @simple_arg_callee(i32 %in0, i32 %in1) declare void @simple_arg_callee(i32 %in0, i32 %in1)
define void @test_simple_arg_call(i32 %in0, i32 %in1) { define void @test_simple_arg_call(i32 %in0, i32 %in1) {
; X32-LABEL: test_simple_arg_call: ; X32-LABEL: test_simple_arg_call:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movl 16(%esp), %eax ; X32-NEXT: movl 16(%esp), %eax
; X32-NEXT: movl 20(%esp), %ecx ; X32-NEXT: movl 20(%esp), %ecx
; X32-NEXT: movl %ecx, (%esp) ; X32-NEXT: movl %ecx, (%esp)
; X32-NEXT: movl %eax, 4(%esp) ; X32-NEXT: movl %eax, 4(%esp)
; X32-NEXT: calll simple_arg_callee ; X32-NEXT: calll simple_arg_callee
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_simple_arg_call: ; X64-LABEL: test_simple_arg_call:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi1:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: movl %esi, %edi ; X64-NEXT: movl %esi, %edi
; X64-NEXT: movl %eax, %esi ; X64-NEXT: movl %eax, %esi
; X64-NEXT: callq simple_arg_callee ; X64-NEXT: callq simple_arg_callee
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
call void @simple_arg_callee(i32 %in1, i32 %in0) call void @simple_arg_callee(i32 %in1, i32 %in0)
ret void ret void
} }
declare void @simple_arg8_callee(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) declare void @simple_arg8_callee(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8)
define void @test_simple_arg8_call(i32 %in0) { define void @test_simple_arg8_call(i32 %in0) {
; X32-LABEL: test_simple_arg8_call: ; X32-LABEL: test_simple_arg8_call:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $44, %esp ; X32-NEXT: subl $44, %esp
; X32-NEXT: .Lcfi3:
; X32-NEXT: .cfi_def_cfa_offset 48 ; X32-NEXT: .cfi_def_cfa_offset 48
; X32-NEXT: movl 48(%esp), %eax ; X32-NEXT: movl 48(%esp), %eax
; X32-NEXT: movl %eax, (%esp) ; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: movl %eax, 4(%esp) ; X32-NEXT: movl %eax, 4(%esp)
; X32-NEXT: movl %eax, 8(%esp) ; X32-NEXT: movl %eax, 8(%esp)
; X32-NEXT: movl %eax, 12(%esp) ; X32-NEXT: movl %eax, 12(%esp)
; X32-NEXT: movl %eax, 16(%esp) ; X32-NEXT: movl %eax, 16(%esp)
; X32-NEXT: movl %eax, 20(%esp) ; X32-NEXT: movl %eax, 20(%esp)
; X32-NEXT: movl %eax, 24(%esp) ; X32-NEXT: movl %eax, 24(%esp)
; X32-NEXT: movl %eax, 28(%esp) ; X32-NEXT: movl %eax, 28(%esp)
; X32-NEXT: calll simple_arg8_callee ; X32-NEXT: calll simple_arg8_callee
; X32-NEXT: addl $44, %esp ; X32-NEXT: addl $44, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_simple_arg8_call: ; X64-LABEL: test_simple_arg8_call:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .Lcfi2:
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
; X64-NEXT: movl %edi, (%rsp) ; X64-NEXT: movl %edi, (%rsp)
; X64-NEXT: movl %edi, 8(%rsp) ; X64-NEXT: movl %edi, 8(%rsp)
; X64-NEXT: movl %edi, %esi ; X64-NEXT: movl %edi, %esi
; X64-NEXT: movl %edi, %edx ; X64-NEXT: movl %edi, %edx
; X64-NEXT: movl %edi, %ecx ; X64-NEXT: movl %edi, %ecx
; X64-NEXT: movl %edi, %r8d ; X64-NEXT: movl %edi, %r8d
; X64-NEXT: movl %edi, %r9d ; X64-NEXT: movl %edi, %r9d
; X64-NEXT: callq simple_arg8_callee ; X64-NEXT: callq simple_arg8_callee
; X64-NEXT: addq $24, %rsp ; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq ; X64-NEXT: retq
call void @simple_arg8_callee(i32 %in0, i32 %in0, i32 %in0, i32 %in0,i32 %in0, i32 %in0, i32 %in0, i32 %in0) call void @simple_arg8_callee(i32 %in0, i32 %in0, i32 %in0, i32 %in0,i32 %in0, i32 %in0, i32 %in0, i32 %in0)
ret void ret void
} }
declare i32 @simple_return_callee(i32 %in0) declare i32 @simple_return_callee(i32 %in0)
define i32 @test_simple_return_callee() { define i32 @test_simple_return_callee() {
; X32-LABEL: test_simple_return_callee: ; X32-LABEL: test_simple_return_callee:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi4:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movl $5, %eax ; X32-NEXT: movl $5, %eax
; X32-NEXT: movl %eax, (%esp) ; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: calll simple_return_callee ; X32-NEXT: calll simple_return_callee
; X32-NEXT: addl %eax, %eax ; X32-NEXT: addl %eax, %eax
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_simple_return_callee: ; X64-LABEL: test_simple_return_callee:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi3:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movl $5, %edi ; X64-NEXT: movl $5, %edi
; X64-NEXT: callq simple_return_callee ; X64-NEXT: callq simple_return_callee
; X64-NEXT: addl %eax, %eax ; X64-NEXT: addl %eax, %eax
; X64-NEXT: popq %rcx ; X64-NEXT: popq %rcx
; X64-NEXT: retq ; X64-NEXT: retq
%call = call i32 @simple_return_callee(i32 5) %call = call i32 @simple_return_callee(i32 5)
%r = add i32 %call, %call %r = add i32 %call, %call
ret i32 %r ret i32 %r
} }
declare <8 x i32> @split_return_callee(<8 x i32> %in0) declare <8 x i32> @split_return_callee(<8 x i32> %in0)
define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) { define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) {
; X32-LABEL: test_split_return_callee: ; X32-LABEL: test_split_return_callee:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $44, %esp ; X32-NEXT: subl $44, %esp
; X32-NEXT: .Lcfi5:
; X32-NEXT: .cfi_def_cfa_offset 48 ; X32-NEXT: .cfi_def_cfa_offset 48
; X32-NEXT: movaps %xmm0, (%esp) # 16-byte Spill ; X32-NEXT: movaps %xmm0, (%esp) # 16-byte Spill
; X32-NEXT: movaps %xmm1, 16(%esp) # 16-byte Spill ; X32-NEXT: movaps %xmm1, 16(%esp) # 16-byte Spill
; X32-NEXT: movdqu 48(%esp), %xmm1 ; X32-NEXT: movdqu 48(%esp), %xmm1
; X32-NEXT: movdqa %xmm2, %xmm0 ; X32-NEXT: movdqa %xmm2, %xmm0
; X32-NEXT: calll split_return_callee ; X32-NEXT: calll split_return_callee
; X32-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload ; X32-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload
; X32-NEXT: paddd 16(%esp), %xmm1 # 16-byte Folded Reload ; X32-NEXT: paddd 16(%esp), %xmm1 # 16-byte Folded Reload
; X32-NEXT: addl $44, %esp ; X32-NEXT: addl $44, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_split_return_callee: ; X64-LABEL: test_split_return_callee:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: subq $40, %rsp ; X64-NEXT: subq $40, %rsp
; X64-NEXT: .Lcfi4:
; X64-NEXT: .cfi_def_cfa_offset 48 ; X64-NEXT: .cfi_def_cfa_offset 48
; X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; X64-NEXT: movaps %xmm1, 16(%rsp) # 16-byte Spill ; X64-NEXT: movaps %xmm1, 16(%rsp) # 16-byte Spill
; X64-NEXT: movdqa %xmm2, %xmm0 ; X64-NEXT: movdqa %xmm2, %xmm0
; X64-NEXT: movdqa %xmm3, %xmm1 ; X64-NEXT: movdqa %xmm3, %xmm1
; X64-NEXT: callq split_return_callee ; X64-NEXT: callq split_return_callee
; X64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload
; X64-NEXT: paddd 16(%rsp), %xmm1 # 16-byte Folded Reload ; X64-NEXT: paddd 16(%rsp), %xmm1 # 16-byte Folded Reload
; X64-NEXT: addq $40, %rsp ; X64-NEXT: addq $40, %rsp
; X64-NEXT: retq ; X64-NEXT: retq
%call = call <8 x i32> @split_return_callee(<8 x i32> %arg2) %call = call <8 x i32> @split_return_callee(<8 x i32> %arg2)
%r = add <8 x i32> %arg1, %call %r = add <8 x i32> %arg1, %call
ret <8 x i32> %r ret <8 x i32> %r
} }
define void @test_indirect_call(void()* %func) { define void @test_indirect_call(void()* %func) {
; X32-LABEL: test_indirect_call: ; X32-LABEL: test_indirect_call:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi6:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: calll *16(%esp) ; X32-NEXT: calll *16(%esp)
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_indirect_call: ; X64-LABEL: test_indirect_call:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi5:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: callq *%rdi ; X64-NEXT: callq *%rdi
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
call void %func() call void %func()
ret void ret void
} }
declare void @take_char(i8) declare void @take_char(i8)
define void @test_abi_exts_call(i8* %addr) { define void @test_abi_exts_call(i8* %addr) {
; X32-LABEL: test_abi_exts_call: ; X32-LABEL: test_abi_exts_call:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: .Lcfi7:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .Lcfi8:
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: .cfi_def_cfa_offset 12
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi9:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: .Lcfi10:
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: .cfi_offset %esi, -12
; X32-NEXT: .Lcfi11:
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %ebx, -8
; X32-NEXT: movl 16(%esp), %eax ; X32-NEXT: movl 16(%esp), %eax
; X32-NEXT: movb (%eax), %bl ; X32-NEXT: movb (%eax), %bl
; X32-NEXT: movzbl %bl, %esi ; X32-NEXT: movzbl %bl, %esi
; X32-NEXT: movl %esi, (%esp) ; X32-NEXT: movl %esi, (%esp)
; X32-NEXT: calll take_char ; X32-NEXT: calll take_char
; X32-NEXT: movsbl %bl, %eax ; X32-NEXT: movsbl %bl, %eax
; X32-NEXT: movl %eax, (%esp) ; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: calll take_char ; X32-NEXT: calll take_char
; X32-NEXT: movl %esi, (%esp) ; X32-NEXT: movl %esi, (%esp)
; X32-NEXT: calll take_char ; X32-NEXT: calll take_char
; X32-NEXT: addl $4, %esp ; X32-NEXT: addl $4, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_abi_exts_call: ; X64-LABEL: test_abi_exts_call:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: .Lcfi6:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .Lcfi7:
; X64-NEXT: .cfi_offset %rbx, -16 ; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: movb (%rdi), %al ; X64-NEXT: movb (%rdi), %al
; X64-NEXT: movzbl %al, %ebx ; X64-NEXT: movzbl %al, %ebx
; X64-NEXT: movl %ebx, %edi ; X64-NEXT: movl %ebx, %edi
; X64-NEXT: callq take_char ; X64-NEXT: callq take_char
; X64-NEXT: movsbl %bl, %edi ; X64-NEXT: movsbl %bl, %edi
; X64-NEXT: callq take_char ; X64-NEXT: callq take_char
; X64-NEXT: movl %ebx, %edi ; X64-NEXT: movl %ebx, %edi
; X64-NEXT: callq take_char ; X64-NEXT: callq take_char
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: retq ; X64-NEXT: retq
%val = load i8, i8* %addr %val = load i8, i8* %addr
call void @take_char(i8 %val) call void @take_char(i8 %val)
call void @take_char(i8 signext %val) call void @take_char(i8 signext %val)
call void @take_char(i8 zeroext %val) call void @take_char(i8 zeroext %val)
ret void ret void
} }
declare void @variadic_callee(i8*, ...) declare void @variadic_callee(i8*, ...)
define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) { define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) {
; X32-LABEL: test_variadic_call_1: ; X32-LABEL: test_variadic_call_1:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi12:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movl 16(%esp), %eax ; X32-NEXT: movl 16(%esp), %eax
; X32-NEXT: movl 20(%esp), %ecx ; X32-NEXT: movl 20(%esp), %ecx
; X32-NEXT: movl (%eax), %eax ; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl (%ecx), %ecx ; X32-NEXT: movl (%ecx), %ecx
; X32-NEXT: movl %eax, (%esp) ; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: movl %ecx, 4(%esp) ; X32-NEXT: movl %ecx, 4(%esp)
; X32-NEXT: calll variadic_callee ; X32-NEXT: calll variadic_callee
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_variadic_call_1: ; X64-LABEL: test_variadic_call_1:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi8:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movq (%rdi), %rdi ; X64-NEXT: movq (%rdi), %rdi
; X64-NEXT: movl (%rsi), %esi ; X64-NEXT: movl (%rsi), %esi
; X64-NEXT: movb $0, %al ; X64-NEXT: movb $0, %al
; X64-NEXT: callq variadic_callee ; X64-NEXT: callq variadic_callee
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
%addr = load i8*, i8** %addr_ptr %addr = load i8*, i8** %addr_ptr
%val = load i32, i32* %val_ptr %val = load i32, i32* %val_ptr
call void (i8*, ...) @variadic_callee(i8* %addr, i32 %val) call void (i8*, ...) @variadic_callee(i8* %addr, i32 %val)
ret void ret void
} }
define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) { define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) {
; X32-LABEL: test_variadic_call_2: ; X32-LABEL: test_variadic_call_2:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: subl $12, %esp ; X32-NEXT: subl $12, %esp
; X32-NEXT: .Lcfi13:
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movl 16(%esp), %eax ; X32-NEXT: movl 16(%esp), %eax
; X32-NEXT: movl 20(%esp), %ecx ; X32-NEXT: movl 20(%esp), %ecx
; X32-NEXT: movl (%eax), %eax ; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl (%ecx), %edx ; X32-NEXT: movl (%ecx), %edx
; X32-NEXT: movl 4(%ecx), %ecx ; X32-NEXT: movl 4(%ecx), %ecx
; X32-NEXT: movl %eax, (%esp) ; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: movl $4, %eax ; X32-NEXT: movl $4, %eax
; X32-NEXT: leal (%esp,%eax), %eax ; X32-NEXT: leal (%esp,%eax), %eax
; X32-NEXT: movl %edx, 4(%esp) ; X32-NEXT: movl %edx, 4(%esp)
; X32-NEXT: movl %ecx, 4(%eax) ; X32-NEXT: movl %ecx, 4(%eax)
; X32-NEXT: calll variadic_callee ; X32-NEXT: calll variadic_callee
; X32-NEXT: addl $12, %esp ; X32-NEXT: addl $12, %esp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_variadic_call_2: ; X64-LABEL: test_variadic_call_2:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi9:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movq (%rdi), %rdi ; X64-NEXT: movq (%rdi), %rdi
; X64-NEXT: movq (%rsi), %rcx ; X64-NEXT: movq (%rsi), %rcx
; X64-NEXT: movb $1, %al ; X64-NEXT: movb $1, %al
; X64-NEXT: movq %rcx, %xmm0 ; X64-NEXT: movq %rcx, %xmm0
; X64-NEXT: callq variadic_callee ; X64-NEXT: callq variadic_callee
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
%addr = load i8*, i8** %addr_ptr %addr = load i8*, i8** %addr_ptr
%val = load double, double* %val_ptr %val = load double, double* %val_ptr
call void (i8*, ...) @variadic_callee(i8* %addr, double %val) call void (i8*, ...) @variadic_callee(i8* %addr, double %val)
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/GlobalISel/frameIndex.ll

Show All 9 Lines
; X64-LABEL: allocai32: ; X64-LABEL: allocai32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: leaq -4(%rsp), %rax ; X64-NEXT: leaq -4(%rsp), %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: allocai32: ; X32-LABEL: allocai32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movl %esp, %eax ; X32-NEXT: movl %esp, %eax
; X32-NEXT: popl %ecx ; X32-NEXT: popl %ecx
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32ABI-LABEL: allocai32: ; X32ABI-LABEL: allocai32:
; X32ABI: # BB#0: ; X32ABI: # BB#0:
; X32ABI-NEXT: leal -4(%rsp), %eax ; X32ABI-NEXT: leal -4(%rsp), %eax
; X32ABI-NEXT: retq ; X32ABI-NEXT: retq
%ptr1 = alloca i32 %ptr1 = alloca i32
ret i32* %ptr1 ret i32* %ptr1
} }

llvm/trunk/test/CodeGen/X86/TruncAssertZext.ll

Show All 10 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
ret i64 -1 ret i64 -1
} }
define i64 @main() { define i64 @main() {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq foo ; CHECK-NEXT: callq foo
; CHECK-NEXT: movabsq $-4294967041, %rcx # imm = 0xFFFFFFFF000000FF ; CHECK-NEXT: movabsq $-4294967041, %rcx # imm = 0xFFFFFFFF000000FF
; CHECK-NEXT: andq %rax, %rcx ; CHECK-NEXT: andq %rax, %rcx
; CHECK-NEXT: movl %ecx, %ecx ; CHECK-NEXT: movl %ecx, %ecx
; CHECK-NEXT: leaq (,%rcx,8), %rax ; CHECK-NEXT: leaq (,%rcx,8), %rax
; CHECK-NEXT: subq %rcx, %rax ; CHECK-NEXT: subq %rcx, %rax
; CHECK-NEXT: shrq $32, %rax ; CHECK-NEXT: shrq $32, %rax
Show All 15 Lines

llvm/trunk/test/CodeGen/X86/atomic128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
@var = global i128 0 @var = global i128 0
; Due to the scheduling right after isel for cmpxchg and given the ; Due to the scheduling right after isel for cmpxchg and given the
; machine scheduler and copy coalescer do not mess up with physical ; machine scheduler and copy coalescer do not mess up with physical
; register live-ranges, we end up with a useless copy. ; register live-ranges, we end up with a useless copy.
define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) { define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
; CHECK-LABEL: val_compare_and_swap: ; CHECK-LABEL: val_compare_and_swap:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rcx, %r9 ; CHECK-NEXT: movq %rcx, %r9
; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: movq %r8, %rcx ; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: movq %r9, %rbx ; CHECK-NEXT: movq %r9, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
ret i128 %val ret i128 %val
} }
define void @fetch_and_nand(i128* %p, i128 %bits) { define void @fetch_and_nand(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_nand: ; CHECK-LABEL: fetch_and_nand:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi3:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_1: ## %atomicrmw.start ; CHECK-NEXT: LBB1_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
Show All 13 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_or(i128* %p, i128 %bits) { define void @fetch_and_or(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_or: ; CHECK-LABEL: fetch_and_or:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi4:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi5:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB2_1: ## %atomicrmw.start ; CHECK-NEXT: LBB2_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
Show All 11 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_add(i128* %p, i128 %bits) { define void @fetch_and_add(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_add: ; CHECK-LABEL: fetch_and_add:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi6:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi7:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB3_1: ## %atomicrmw.start ; CHECK-NEXT: LBB3_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
Show All 11 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_sub(i128* %p, i128 %bits) { define void @fetch_and_sub(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_sub: ; CHECK-LABEL: fetch_and_sub:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi8:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi9:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB4_1: ## %atomicrmw.start ; CHECK-NEXT: LBB4_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
Show All 11 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_min(i128* %p, i128 %bits) { define void @fetch_and_min(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_min: ; CHECK-LABEL: fetch_and_min:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi10:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi11:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB5_1: ## %atomicrmw.start ; CHECK-NEXT: LBB5_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi ; CHECK-NEXT: cmpq %rax, %rsi
Show All 14 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_max(i128* %p, i128 %bits) { define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_max: ; CHECK-LABEL: fetch_and_max:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi12:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi13:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB6_1: ## %atomicrmw.start ; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rsi, %rax ; CHECK-NEXT: cmpq %rsi, %rax
Show All 14 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_umin(i128* %p, i128 %bits) { define void @fetch_and_umin(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umin: ; CHECK-LABEL: fetch_and_umin:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi14:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi15:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB7_1: ## %atomicrmw.start ; CHECK-NEXT: LBB7_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi ; CHECK-NEXT: cmpq %rax, %rsi
Show All 14 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define void @fetch_and_umax(i128* %p, i128 %bits) { define void @fetch_and_umax(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umax: ; CHECK-LABEL: fetch_and_umax:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi16:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi17:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8 ; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB8_1: ## %atomicrmw.start ; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi ; CHECK-NEXT: cmpq %rax, %rsi
Show All 14 Lines; CHECK-NEXT: retq
store i128 %val, i128* @var, align 16 store i128 %val, i128* @var, align 16
ret void ret void
} }
define i128 @atomic_load_seq_cst(i128* %p) { define i128 @atomic_load_seq_cst(i128* %p) {
; CHECK-LABEL: atomic_load_seq_cst: ; CHECK-LABEL: atomic_load_seq_cst:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi18:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi19:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = load atomic i128, i128* %p seq_cst, align 16 %r = load atomic i128, i128* %p seq_cst, align 16
ret i128 %r ret i128 %r
} }
define i128 @atomic_load_relaxed(i128* %p) { define i128 @atomic_load_relaxed(i128* %p) {
; CHECK-LABEL: atomic_load_relaxed: ; CHECK-LABEL: atomic_load_relaxed:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi20:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi21:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = load atomic i128, i128* %p monotonic, align 16 %r = load atomic i128, i128* %p monotonic, align 16
ret i128 %r ret i128 %r
} }
define void @atomic_store_seq_cst(i128* %p, i128 %in) { define void @atomic_store_seq_cst(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_seq_cst: ; CHECK-LABEL: atomic_store_seq_cst:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi22:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi23:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB11_1: ## %atomicrmw.start ; CHECK-NEXT: LBB11_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB11_1 ; CHECK-NEXT: jne LBB11_1
; CHECK-NEXT: ## BB#2: ## %atomicrmw.end ; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
store atomic i128 %in, i128* %p seq_cst, align 16 store atomic i128 %in, i128* %p seq_cst, align 16
ret void ret void
} }
define void @atomic_store_release(i128* %p, i128 %in) { define void @atomic_store_release(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_release: ; CHECK-LABEL: atomic_store_release:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi24:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi25:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB12_1: ## %atomicrmw.start ; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB12_1 ; CHECK-NEXT: jne LBB12_1
; CHECK-NEXT: ## BB#2: ## %atomicrmw.end ; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
store atomic i128 %in, i128* %p release, align 16 store atomic i128 %in, i128* %p release, align 16
ret void ret void
} }
define void @atomic_store_relaxed(i128* %p, i128 %in) { define void @atomic_store_relaxed(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_relaxed: ; CHECK-LABEL: atomic_store_relaxed:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi26:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Lcfi27:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx ; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB13_1: ## %atomicrmw.start ; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi) ; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB13_1 ; CHECK-NEXT: jne LBB13_1
; CHECK-NEXT: ## BB#2: ## %atomicrmw.end ; CHECK-NEXT: ## BB#2: ## %atomicrmw.end
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
store atomic i128 %in, i128* %p unordered, align 16 store atomic i128 %in, i128* %p unordered, align 16
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll

Show First 20 Lines • Show All 1,088 Lines • ▼ Show 20 Lines
; created later, or if selection DAG cannot prove that folding the ; created later, or if selection DAG cannot prove that folding the
; load will not create a cycle in the DAG. ; load will not create a cycle in the DAG.
; Those test cases exerce the latter. ; Those test cases exerce the latter.
define void @isel_crash_16b(i8* %cV_R.addr) { define void @isel_crash_16b(i8* %cV_R.addr) {
; X32-LABEL: isel_crash_16b: ; X32-LABEL: isel_crash_16b:
; X32: ## BB#0: ## %eintry ; X32: ## BB#0: ## %eintry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %xmm0, (%esp) ; X32-NEXT: vmovaps %xmm0, (%esp)
; X32-NEXT: vpbroadcastb (%eax), %xmm1 ; X32-NEXT: vpbroadcastb (%eax), %xmm1
; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp)
; X32-NEXT: addl $60, %esp ; X32-NEXT: addl $60, %esp
Show All 23 Lineseintry:
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_32b(i8* %cV_R.addr) { define void @isel_crash_32b(i8* %cV_R.addr) {
; X32-LABEL: isel_crash_32b: ; X32-LABEL: isel_crash_32b:
; X32: ## BB#0: ## %eintry ; X32: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi2:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi3:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vpbroadcastb (%eax), %ymm1 ; X32-NEXT: vpbroadcastb (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: isel_crash_32b: ; X64-LABEL: isel_crash_32b:
; X64: ## BB#0: ## %eintry ; X64: ## BB#0: ## %eintry
; X64-NEXT: pushq %rbp ; X64-NEXT: pushq %rbp
; X64-NEXT: Lcfi0:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: Lcfi1:
; X64-NEXT: .cfi_offset %rbp, -16 ; X64-NEXT: .cfi_offset %rbp, -16
; X64-NEXT: movq %rsp, %rbp ; X64-NEXT: movq %rsp, %rbp
; X64-NEXT: Lcfi2:
; X64-NEXT: .cfi_def_cfa_register %rbp ; X64-NEXT: .cfi_def_cfa_register %rbp
; X64-NEXT: andq $-32, %rsp ; X64-NEXT: andq $-32, %rsp
; X64-NEXT: subq $128, %rsp ; X64-NEXT: subq $128, %rsp
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %ymm0, (%rsp) ; X64-NEXT: vmovaps %ymm0, (%rsp)
; X64-NEXT: movb (%rdi), %al ; X64-NEXT: movb (%rdi), %al
; X64-NEXT: vmovd %eax, %xmm1 ; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastb %xmm1, %ymm1 ; X64-NEXT: vpbroadcastb %xmm1, %ymm1
Show All 17 Lineseintry:
store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_8w(i16* %cV_R.addr) { define void @isel_crash_8w(i16* %cV_R.addr) {
; X32-LABEL: isel_crash_8w: ; X32-LABEL: isel_crash_8w:
; X32: ## BB#0: ## %entry ; X32: ## BB#0: ## %entry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: Lcfi4:
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %xmm0, (%esp) ; X32-NEXT: vmovaps %xmm0, (%esp)
; X32-NEXT: vpbroadcastw (%eax), %xmm1 ; X32-NEXT: vpbroadcastw (%eax), %xmm1
; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp)
; X32-NEXT: addl $60, %esp ; X32-NEXT: addl $60, %esp
Show All 23 Linesentry:
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_16w(i16* %cV_R.addr) { define void @isel_crash_16w(i16* %cV_R.addr) {
; X32-LABEL: isel_crash_16w: ; X32-LABEL: isel_crash_16w:
; X32: ## BB#0: ## %eintry ; X32: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: Lcfi5:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi6:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi7:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vpbroadcastw (%eax), %ymm1 ; X32-NEXT: vpbroadcastw (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: isel_crash_16w: ; X64-LABEL: isel_crash_16w:
; X64: ## BB#0: ## %eintry ; X64: ## BB#0: ## %eintry
; X64-NEXT: pushq %rbp ; X64-NEXT: pushq %rbp
; X64-NEXT: Lcfi3:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: Lcfi4:
; X64-NEXT: .cfi_offset %rbp, -16 ; X64-NEXT: .cfi_offset %rbp, -16
; X64-NEXT: movq %rsp, %rbp ; X64-NEXT: movq %rsp, %rbp
; X64-NEXT: Lcfi5:
; X64-NEXT: .cfi_def_cfa_register %rbp ; X64-NEXT: .cfi_def_cfa_register %rbp
; X64-NEXT: andq $-32, %rsp ; X64-NEXT: andq $-32, %rsp
; X64-NEXT: subq $128, %rsp ; X64-NEXT: subq $128, %rsp
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vmovaps %ymm0, (%rsp) ; X64-NEXT: vmovaps %ymm0, (%rsp)
; X64-NEXT: movzwl (%rdi), %eax ; X64-NEXT: movzwl (%rdi), %eax
; X64-NEXT: vmovd %eax, %xmm1 ; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpbroadcastw %xmm1, %ymm1 ; X64-NEXT: vpbroadcastw %xmm1, %ymm1
Show All 17 Lineseintry:
store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_4d(i32* %cV_R.addr) { define void @isel_crash_4d(i32* %cV_R.addr) {
; X32-LABEL: isel_crash_4d: ; X32-LABEL: isel_crash_4d:
; X32: ## BB#0: ## %entry ; X32: ## BB#0: ## %entry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: Lcfi8:
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %xmm0, (%esp) ; X32-NEXT: vmovaps %xmm0, (%esp)
; X32-NEXT: vbroadcastss (%eax), %xmm1 ; X32-NEXT: vbroadcastss (%eax), %xmm1
; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovaps %xmm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %xmm1, {{[0-9]+}}(%esp)
; X32-NEXT: addl $60, %esp ; X32-NEXT: addl $60, %esp
Show All 33 Linesentry:
store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_8d(i32* %cV_R.addr) { define void @isel_crash_8d(i32* %cV_R.addr) {
; X32-LABEL: isel_crash_8d: ; X32-LABEL: isel_crash_8d:
; X32: ## BB#0: ## %eintry ; X32: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: Lcfi9:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi10:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi11:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: vbroadcastss (%eax), %ymm1 ; X32-NEXT: vbroadcastss (%eax), %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-AVX2-LABEL: isel_crash_8d: ; X64-AVX2-LABEL: isel_crash_8d:
; X64-AVX2: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-AVX2-NEXT: Lcfi6:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-AVX2-NEXT: Lcfi7:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-AVX2-NEXT: Lcfi8:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX2-NEXT: movl (%rdi), %eax ; X64-AVX2-NEXT: movl (%rdi), %eax
; X64-AVX2-NEXT: vmovd %eax, %xmm1 ; X64-AVX2-NEXT: vmovd %eax, %xmm1
; X64-AVX2-NEXT: vpbroadcastd %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastd %xmm1, %ymm1
; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-AVX2-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512VL-LABEL: isel_crash_8d: ; X64-AVX512VL-LABEL: isel_crash_8d:
; X64-AVX512VL: ## BB#0: ## %eintry ; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp ; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi6:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi7:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16 ; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp ; X64-AVX512VL-NEXT: movq %rsp, %rbp
; X64-AVX512VL-NEXT: Lcfi8:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp ; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp ; X64-AVX512VL-NEXT: subq $128, %rsp
; X64-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX512VL-NEXT: movl (%rdi), %eax ; X64-AVX512VL-NEXT: movl (%rdi), %eax
; X64-AVX512VL-NEXT: vpbroadcastd %eax, %ymm1 ; X64-AVX512VL-NEXT: vpbroadcastd %eax, %ymm1
; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
Show All 16 Lineseintry:
store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_2q(i64* %cV_R.addr) { define void @isel_crash_2q(i64* %cV_R.addr) {
; X32-LABEL: isel_crash_2q: ; X32-LABEL: isel_crash_2q:
; X32: ## BB#0: ## %entry ; X32: ## BB#0: ## %entry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: Lcfi12:
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %xmm0, (%esp) ; X32-NEXT: vmovaps %xmm0, (%esp)
; X32-NEXT: movl (%eax), %ecx ; X32-NEXT: movl (%eax), %ecx
; X32-NEXT: movl 4(%eax), %eax ; X32-NEXT: movl 4(%eax), %eax
; X32-NEXT: vmovd %ecx, %xmm1 ; X32-NEXT: vmovd %ecx, %xmm1
; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
Show All 37 Linesentry:
store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16 store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
ret void ret void
} }
define void @isel_crash_4q(i64* %cV_R.addr) { define void @isel_crash_4q(i64* %cV_R.addr) {
; X32-LABEL: isel_crash_4q: ; X32-LABEL: isel_crash_4q:
; X32: ## BB#0: ## %eintry ; X32: ## BB#0: ## %eintry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: Lcfi13:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: Lcfi14:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: Lcfi15:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-32, %esp ; X32-NEXT: andl $-32, %esp
; X32-NEXT: subl $128, %esp ; X32-NEXT: subl $128, %esp
; X32-NEXT: movl 8(%ebp), %eax ; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vmovaps %ymm0, (%esp) ; X32-NEXT: vmovaps %ymm0, (%esp)
; X32-NEXT: movl (%eax), %ecx ; X32-NEXT: movl (%eax), %ecx
; X32-NEXT: movl 4(%eax), %eax ; X32-NEXT: movl 4(%eax), %eax
; X32-NEXT: vmovd %ecx, %xmm1 ; X32-NEXT: vmovd %ecx, %xmm1
; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1 ; X32-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
; X32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
; X32-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1 ; X32-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp) ; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp) ; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-AVX2-LABEL: isel_crash_4q: ; X64-AVX2-LABEL: isel_crash_4q:
; X64-AVX2: ## BB#0: ## %eintry ; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp ; X64-AVX2-NEXT: pushq %rbp
; X64-AVX2-NEXT: Lcfi9:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
; X64-AVX2-NEXT: Lcfi10:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16 ; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp ; X64-AVX2-NEXT: movq %rsp, %rbp
; X64-AVX2-NEXT: Lcfi11:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp ; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp ; X64-AVX2-NEXT: subq $128, %rsp
; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX2-NEXT: movq (%rdi), %rax ; X64-AVX2-NEXT: movq (%rdi), %rax
; X64-AVX2-NEXT: vmovq %rax, %xmm1 ; X64-AVX2-NEXT: vmovq %rax, %xmm1
; X64-AVX2-NEXT: vpbroadcastq %xmm1, %ymm1 ; X64-AVX2-NEXT: vpbroadcastq %xmm1, %ymm1
; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp) ; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
; X64-AVX2-NEXT: movq %rbp, %rsp ; X64-AVX2-NEXT: movq %rbp, %rsp
; X64-AVX2-NEXT: popq %rbp ; X64-AVX2-NEXT: popq %rbp
; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512VL-LABEL: isel_crash_4q: ; X64-AVX512VL-LABEL: isel_crash_4q:
; X64-AVX512VL: ## BB#0: ## %eintry ; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp ; X64-AVX512VL-NEXT: pushq %rbp
; X64-AVX512VL-NEXT: Lcfi9:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16 ; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
; X64-AVX512VL-NEXT: Lcfi10:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16 ; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp ; X64-AVX512VL-NEXT: movq %rsp, %rbp
; X64-AVX512VL-NEXT: Lcfi11:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp ; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp ; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp ; X64-AVX512VL-NEXT: subq $128, %rsp
; X64-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp) ; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
; X64-AVX512VL-NEXT: movq (%rdi), %rax ; X64-AVX512VL-NEXT: movq (%rdi), %rax
; X64-AVX512VL-NEXT: vpbroadcastq %rax, %ymm1 ; X64-AVX512VL-NEXT: vpbroadcastq %rax, %ymm1
; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) ; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
Show All 18 Lines

llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
} }
declare <8 x i1> @func8xi1(<8 x i1> %a) declare <8 x i1> @func8xi1(<8 x i1> %a)
define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) { define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
; KNL-LABEL: test5: ; KNL-LABEL: test5:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rax ; KNL-NEXT: pushq %rax
; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL-NEXT: callq _func8xi1 ; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpslld $31, %ymm0, %ymm0 ; KNL-NEXT: vpslld $31, %ymm0, %ymm0
; KNL-NEXT: vpsrad $31, %ymm0, %ymm0 ; KNL-NEXT: vpsrad $31, %ymm0, %ymm0
; KNL-NEXT: popq %rax ; KNL-NEXT: popq %rax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test5: ; SKX-LABEL: test5:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rax ; SKX-NEXT: pushq %rax
; SKX-NEXT: Lcfi0:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0 ; SKX-NEXT: vpmovm2w %k0, %xmm0
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: callq _func8xi1 ; SKX-NEXT: callq _func8xi1
; SKX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; SKX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SKX-NEXT: vpslld $31, %ymm0, %ymm0 ; SKX-NEXT: vpslld $31, %ymm0, %ymm0
; SKX-NEXT: vpsrad $31, %ymm0, %ymm0 ; SKX-NEXT: vpsrad $31, %ymm0, %ymm0
; SKX-NEXT: popq %rax ; SKX-NEXT: popq %rax
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; KNL_X32-LABEL: test5: ; KNL_X32-LABEL: test5:
; KNL_X32: ## BB#0: ; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp ; KNL_X32-NEXT: subl $12, %esp
; KNL_X32-NEXT: Lcfi0:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0 ; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL_X32-NEXT: calll _func8xi1 ; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL_X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL_X32-NEXT: vpslld $31, %ymm0, %ymm0 ; KNL_X32-NEXT: vpslld $31, %ymm0, %ymm0
; KNL_X32-NEXT: vpsrad $31, %ymm0, %ymm0 ; KNL_X32-NEXT: vpsrad $31, %ymm0, %ymm0
; KNL_X32-NEXT: addl $12, %esp ; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl ; KNL_X32-NEXT: retl
%cmpRes = icmp sgt <8 x i32>%a, %b %cmpRes = icmp sgt <8 x i32>%a, %b
%resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes) %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
%res = sext <8 x i1>%resi to <8 x i32> %res = sext <8 x i1>%resi to <8 x i32>
ret <8 x i32> %res ret <8 x i32> %res
} }
declare <16 x i1> @func16xi1(<16 x i1> %a) declare <16 x i1> @func16xi1(<16 x i1> %a)
define <16 x i32> @test6(<16 x i32>%a, <16 x i32>%b) { define <16 x i32> @test6(<16 x i32>%a, <16 x i32>%b) {
; KNL-LABEL: test6: ; KNL-LABEL: test6:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rax ; KNL-NEXT: pushq %rax
; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; KNL-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovdb %zmm0, %xmm0 ; KNL-NEXT: vpmovdb %zmm0, %xmm0
; KNL-NEXT: callq _func16xi1 ; KNL-NEXT: callq _func16xi1
; KNL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vpsrad $31, %zmm0, %zmm0 ; KNL-NEXT: vpsrad $31, %zmm0, %zmm0
; KNL-NEXT: popq %rax ; KNL-NEXT: popq %rax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test6: ; SKX-LABEL: test6:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rax ; SKX-NEXT: pushq %rax
; SKX-NEXT: Lcfi1:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; SKX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %xmm0 ; SKX-NEXT: vpmovm2b %k0, %xmm0
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: callq _func16xi1 ; SKX-NEXT: callq _func16xi1
; SKX-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; SKX-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; SKX-NEXT: vpslld $31, %zmm0, %zmm0 ; SKX-NEXT: vpslld $31, %zmm0, %zmm0
; SKX-NEXT: vpsrad $31, %zmm0, %zmm0 ; SKX-NEXT: vpsrad $31, %zmm0, %zmm0
; SKX-NEXT: popq %rax ; SKX-NEXT: popq %rax
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; KNL_X32-LABEL: test6: ; KNL_X32-LABEL: test6:
; KNL_X32: ## BB#0: ; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp ; KNL_X32-NEXT: subl $12, %esp
; KNL_X32-NEXT: Lcfi1:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; KNL_X32-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; KNL_X32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL_X32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL_X32-NEXT: vpmovdb %zmm0, %xmm0 ; KNL_X32-NEXT: vpmovdb %zmm0, %xmm0
; KNL_X32-NEXT: calll _func16xi1 ; KNL_X32-NEXT: calll _func16xi1
; KNL_X32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL_X32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL_X32-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL_X32-NEXT: vpslld $31, %zmm0, %zmm0
; KNL_X32-NEXT: vpsrad $31, %zmm0, %zmm0 ; KNL_X32-NEXT: vpsrad $31, %zmm0, %zmm0
; KNL_X32-NEXT: addl $12, %esp ; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl ; KNL_X32-NEXT: retl
%cmpRes = icmp sgt <16 x i32>%a, %b %cmpRes = icmp sgt <16 x i32>%a, %b
%resi = call <16 x i1> @func16xi1(<16 x i1> %cmpRes) %resi = call <16 x i1> @func16xi1(<16 x i1> %cmpRes)
%res = sext <16 x i1>%resi to <16 x i32> %res = sext <16 x i1>%resi to <16 x i32>
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <4 x i1> @func4xi1(<4 x i1> %a) declare <4 x i1> @func4xi1(<4 x i1> %a)
define <4 x i32> @test7(<4 x i32>%a, <4 x i32>%b) { define <4 x i32> @test7(<4 x i32>%a, <4 x i32>%b) {
; KNL-LABEL: test7: ; KNL-LABEL: test7:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rax ; KNL-NEXT: pushq %rax
; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; KNL-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; KNL-NEXT: callq _func4xi1 ; KNL-NEXT: callq _func4xi1
; KNL-NEXT: vpslld $31, %xmm0, %xmm0 ; KNL-NEXT: vpslld $31, %xmm0, %xmm0
; KNL-NEXT: vpsrad $31, %xmm0, %xmm0 ; KNL-NEXT: vpsrad $31, %xmm0, %xmm0
; KNL-NEXT: popq %rax ; KNL-NEXT: popq %rax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test7: ; SKX-LABEL: test7:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rax ; SKX-NEXT: pushq %rax
; SKX-NEXT: Lcfi2:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ; SKX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %xmm0 ; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: callq _func4xi1 ; SKX-NEXT: callq _func4xi1
; SKX-NEXT: vpslld $31, %xmm0, %xmm0 ; SKX-NEXT: vpslld $31, %xmm0, %xmm0
; SKX-NEXT: vpsrad $31, %xmm0, %xmm0 ; SKX-NEXT: vpsrad $31, %xmm0, %xmm0
; SKX-NEXT: popq %rax ; SKX-NEXT: popq %rax
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; KNL_X32-LABEL: test7: ; KNL_X32-LABEL: test7:
; KNL_X32: ## BB#0: ; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp ; KNL_X32-NEXT: subl $12, %esp
; KNL_X32-NEXT: Lcfi2:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; KNL_X32-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; KNL_X32-NEXT: calll _func4xi1 ; KNL_X32-NEXT: calll _func4xi1
; KNL_X32-NEXT: vpslld $31, %xmm0, %xmm0 ; KNL_X32-NEXT: vpslld $31, %xmm0, %xmm0
; KNL_X32-NEXT: vpsrad $31, %xmm0, %xmm0 ; KNL_X32-NEXT: vpsrad $31, %xmm0, %xmm0
; KNL_X32-NEXT: addl $12, %esp ; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl ; KNL_X32-NEXT: retl
%cmpRes = icmp sgt <4 x i32>%a, %b %cmpRes = icmp sgt <4 x i32>%a, %b
%resi = call <4 x i1> @func4xi1(<4 x i1> %cmpRes) %resi = call <4 x i1> @func4xi1(<4 x i1> %cmpRes)
%res = sext <4 x i1>%resi to <4 x i32> %res = sext <4 x i1>%resi to <4 x i32>
ret <4 x i32> %res ret <4 x i32> %res
} }
define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) { define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL-LABEL: test7a: ; KNL-LABEL: test7a:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rax ; KNL-NEXT: pushq %rax
; KNL-NEXT: Lcfi3:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL-NEXT: callq _func8xi1 ; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: movb $85, %al ; KNL-NEXT: movb $85, %al
; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1} ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1}
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovqw %zmm0, %xmm0 ; KNL-NEXT: vpmovqw %zmm0, %xmm0
; KNL-NEXT: popq %rax ; KNL-NEXT: popq %rax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test7a: ; SKX-LABEL: test7a:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rax ; SKX-NEXT: pushq %rax
; SKX-NEXT: Lcfi3:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0 ; SKX-NEXT: vpmovm2w %k0, %xmm0
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: callq _func8xi1 ; SKX-NEXT: callq _func8xi1
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k0 ; SKX-NEXT: vpmovw2m %xmm0, %k0
; SKX-NEXT: movb $85, %al ; SKX-NEXT: movb $85, %al
; SKX-NEXT: kmovd %eax, %k1 ; SKX-NEXT: kmovd %eax, %k1
; SKX-NEXT: kandb %k1, %k0, %k0 ; SKX-NEXT: kandb %k1, %k0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0 ; SKX-NEXT: vpmovm2w %k0, %xmm0
; SKX-NEXT: popq %rax ; SKX-NEXT: popq %rax
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; KNL_X32-LABEL: test7a: ; KNL_X32-LABEL: test7a:
; KNL_X32: ## BB#0: ; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp ; KNL_X32-NEXT: subl $12, %esp
; KNL_X32-NEXT: Lcfi3:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0 ; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; KNL_X32-NEXT: calll _func8xi1 ; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL_X32-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL_X32-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL_X32-NEXT: movb $85, %al ; KNL_X32-NEXT: movb $85, %al
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines; KNL_X32-NEXT: retl
%c = icmp sgt i32 %a, %b %c = icmp sgt i32 %a, %b
ret i1 %c ret i1 %c
} }
define i32 @test12(i32 %a1, i32 %a2, i32 %b1) { define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
; ALL_X64-LABEL: test12: ; ALL_X64-LABEL: test12:
; ALL_X64: ## BB#0: ; ALL_X64: ## BB#0:
; ALL_X64-NEXT: pushq %rbp ; ALL_X64-NEXT: pushq %rbp
; ALL_X64-NEXT: Lcfi4:
; ALL_X64-NEXT: .cfi_def_cfa_offset 16 ; ALL_X64-NEXT: .cfi_def_cfa_offset 16
; ALL_X64-NEXT: pushq %r14 ; ALL_X64-NEXT: pushq %r14
; ALL_X64-NEXT: Lcfi5:
; ALL_X64-NEXT: .cfi_def_cfa_offset 24 ; ALL_X64-NEXT: .cfi_def_cfa_offset 24
; ALL_X64-NEXT: pushq %rbx ; ALL_X64-NEXT: pushq %rbx
; ALL_X64-NEXT: Lcfi6:
; ALL_X64-NEXT: .cfi_def_cfa_offset 32 ; ALL_X64-NEXT: .cfi_def_cfa_offset 32
; ALL_X64-NEXT: Lcfi7:
; ALL_X64-NEXT: .cfi_offset %rbx, -32 ; ALL_X64-NEXT: .cfi_offset %rbx, -32
; ALL_X64-NEXT: Lcfi8:
; ALL_X64-NEXT: .cfi_offset %r14, -24 ; ALL_X64-NEXT: .cfi_offset %r14, -24
; ALL_X64-NEXT: Lcfi9:
; ALL_X64-NEXT: .cfi_offset %rbp, -16 ; ALL_X64-NEXT: .cfi_offset %rbp, -16
; ALL_X64-NEXT: movl %esi, %r14d ; ALL_X64-NEXT: movl %esi, %r14d
; ALL_X64-NEXT: movl %edi, %ebp ; ALL_X64-NEXT: movl %edi, %ebp
; ALL_X64-NEXT: movl %edx, %esi ; ALL_X64-NEXT: movl %edx, %esi
; ALL_X64-NEXT: callq _test11 ; ALL_X64-NEXT: callq _test11
; ALL_X64-NEXT: movzbl %al, %ebx ; ALL_X64-NEXT: movzbl %al, %ebx
; ALL_X64-NEXT: movl %ebp, %edi ; ALL_X64-NEXT: movl %ebp, %edi
; ALL_X64-NEXT: movl %r14d, %esi ; ALL_X64-NEXT: movl %r14d, %esi
; ALL_X64-NEXT: movl %ebx, %edx ; ALL_X64-NEXT: movl %ebx, %edx
; ALL_X64-NEXT: callq _test10 ; ALL_X64-NEXT: callq _test10
; ALL_X64-NEXT: xorl %ecx, %ecx ; ALL_X64-NEXT: xorl %ecx, %ecx
; ALL_X64-NEXT: testb $1, %bl ; ALL_X64-NEXT: testb $1, %bl
; ALL_X64-NEXT: cmovel %ecx, %eax ; ALL_X64-NEXT: cmovel %ecx, %eax
; ALL_X64-NEXT: popq %rbx ; ALL_X64-NEXT: popq %rbx
; ALL_X64-NEXT: popq %r14 ; ALL_X64-NEXT: popq %r14
; ALL_X64-NEXT: popq %rbp ; ALL_X64-NEXT: popq %rbp
; ALL_X64-NEXT: retq ; ALL_X64-NEXT: retq
; ;
; KNL_X32-LABEL: test12: ; KNL_X32-LABEL: test12:
; KNL_X32: ## BB#0: ; KNL_X32: ## BB#0:
; KNL_X32-NEXT: pushl %ebx ; KNL_X32-NEXT: pushl %ebx
; KNL_X32-NEXT: Lcfi4:
; KNL_X32-NEXT: .cfi_def_cfa_offset 8 ; KNL_X32-NEXT: .cfi_def_cfa_offset 8
; KNL_X32-NEXT: pushl %edi ; KNL_X32-NEXT: pushl %edi
; KNL_X32-NEXT: Lcfi5:
; KNL_X32-NEXT: .cfi_def_cfa_offset 12 ; KNL_X32-NEXT: .cfi_def_cfa_offset 12
; KNL_X32-NEXT: pushl %esi ; KNL_X32-NEXT: pushl %esi
; KNL_X32-NEXT: Lcfi6:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: subl $16, %esp ; KNL_X32-NEXT: subl $16, %esp
; KNL_X32-NEXT: Lcfi7:
; KNL_X32-NEXT: .cfi_def_cfa_offset 32 ; KNL_X32-NEXT: .cfi_def_cfa_offset 32
; KNL_X32-NEXT: Lcfi8:
; KNL_X32-NEXT: .cfi_offset %esi, -16 ; KNL_X32-NEXT: .cfi_offset %esi, -16
; KNL_X32-NEXT: Lcfi9:
; KNL_X32-NEXT: .cfi_offset %edi, -12 ; KNL_X32-NEXT: .cfi_offset %edi, -12
; KNL_X32-NEXT: Lcfi10:
; KNL_X32-NEXT: .cfi_offset %ebx, -8 ; KNL_X32-NEXT: .cfi_offset %ebx, -8
; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %edi ; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_X32-NEXT: movl %eax, {{[0-9]+}}(%esp) ; KNL_X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; KNL_X32-NEXT: movl %edi, (%esp) ; KNL_X32-NEXT: movl %edi, (%esp)
; KNL_X32-NEXT: calll _test11 ; KNL_X32-NEXT: calll _test11
; KNL_X32-NEXT: movl %eax, %ebx ; KNL_X32-NEXT: movl %eax, %ebx
Show All 18 Lines

llvm/trunk/test/CodeGen/X86/avx512-fsel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mattr=+avx512f < %s | FileCheck %s ; RUN: llc -O0 -mattr=+avx512f < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
define i32 @test(float %a, float %b) { define i32 @test(float %a, float %b) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vcmpeqss %xmm1, %xmm0, %k0 ; CHECK-NEXT: vcmpeqss %xmm1, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: movb %al, %cl ; CHECK-NEXT: movb %al, %cl
; CHECK-NEXT: xorb $-1, %cl ; CHECK-NEXT: xorb $-1, %cl
; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne LBB0_1 ; CHECK-NEXT: jne LBB0_1
; CHECK-NEXT: jmp LBB0_2 ; CHECK-NEXT: jmp LBB0_2
Show All 21 Lines

llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll

Show First 20 Lines • Show All 793 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%r = insertelement <32 x i8> %x, i8 %y, i32 20 %r = insertelement <32 x i8> %x, i8 %y, i32 20
ret <32 x i8> %r ret <32 x i8> %r
} }
define i32 @test_insertelement_v32i1(i32 %a, i32 %b, <32 x i32> %x , <32 x i32> %y) { define i32 @test_insertelement_v32i1(i32 %a, i32 %b, <32 x i32> %x , <32 x i32> %y) {
; KNL-LABEL: test_insertelement_v32i1: ; KNL-LABEL: test_insertelement_v32i1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $32, %rsp ; KNL-NEXT: subq $32, %rsp
; KNL-NEXT: xorl %eax, %eax ; KNL-NEXT: xorl %eax, %eax
; KNL-NEXT: cmpl %esi, %edi ; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: setb %al ; KNL-NEXT: setb %al
; KNL-NEXT: vpcmpltud %zmm3, %zmm1, %k0 ; KNL-NEXT: vpcmpltud %zmm3, %zmm1, %k0
; KNL-NEXT: kshiftlw $14, %k0, %k1 ; KNL-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%t2 = extractelement <2 x i64> %t1, i32 %index %t2 = extractelement <2 x i64> %t1, i32 %index
ret i64 %t2 ret i64 %t2
} }
define i64 @test_extractelement_variable_v4i64(<4 x i64> %t1, i32 %index) { define i64 @test_extractelement_variable_v4i64(<4 x i64> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v4i64: ; KNL-LABEL: test_extractelement_variable_v4i64:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi3:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi4:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi5:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $3, %edi ; KNL-NEXT: andl $3, %edi
; KNL-NEXT: movq (%rsp,%rdi,8), %rax ; KNL-NEXT: movq (%rsp,%rdi,8), %rax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v4i64: ; SKX-LABEL: test_extractelement_variable_v4i64:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi0:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi1:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi2:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $3, %edi ; SKX-NEXT: andl $3, %edi
; SKX-NEXT: movq (%rsp,%rdi,8), %rax ; SKX-NEXT: movq (%rsp,%rdi,8), %rax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <4 x i64> %t1, i32 %index %t2 = extractelement <4 x i64> %t1, i32 %index
ret i64 %t2 ret i64 %t2
} }
define i64 @test_extractelement_variable_v8i64(<8 x i64> %t1, i32 %index) { define i64 @test_extractelement_variable_v8i64(<8 x i64> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v8i64: ; KNL-LABEL: test_extractelement_variable_v8i64:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi6:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi7:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi8:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %zmm0, (%rsp) ; KNL-NEXT: vmovaps %zmm0, (%rsp)
; KNL-NEXT: andl $7, %edi ; KNL-NEXT: andl $7, %edi
; KNL-NEXT: movq (%rsp,%rdi,8), %rax ; KNL-NEXT: movq (%rsp,%rdi,8), %rax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v8i64: ; SKX-LABEL: test_extractelement_variable_v8i64:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi3:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi4:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi5:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $7, %edi ; SKX-NEXT: andl $7, %edi
; SKX-NEXT: movq (%rsp,%rdi,8), %rax ; SKX-NEXT: movq (%rsp,%rdi,8), %rax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
Show All 15 Lines; CHECK-NEXT: retq
%t2 = extractelement <2 x double> %t1, i32 %index %t2 = extractelement <2 x double> %t1, i32 %index
ret double %t2 ret double %t2
} }
define double @test_extractelement_variable_v4f64(<4 x double> %t1, i32 %index) { define double @test_extractelement_variable_v4f64(<4 x double> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v4f64: ; KNL-LABEL: test_extractelement_variable_v4f64:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi9:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi10:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi11:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $3, %edi ; KNL-NEXT: andl $3, %edi
; KNL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; KNL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v4f64: ; SKX-LABEL: test_extractelement_variable_v4f64:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi6:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi7:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi8:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $3, %edi ; SKX-NEXT: andl $3, %edi
; SKX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; SKX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <4 x double> %t1, i32 %index %t2 = extractelement <4 x double> %t1, i32 %index
ret double %t2 ret double %t2
} }
define double @test_extractelement_variable_v8f64(<8 x double> %t1, i32 %index) { define double @test_extractelement_variable_v8f64(<8 x double> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v8f64: ; KNL-LABEL: test_extractelement_variable_v8f64:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi12:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi13:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi14:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %zmm0, (%rsp) ; KNL-NEXT: vmovaps %zmm0, (%rsp)
; KNL-NEXT: andl $7, %edi ; KNL-NEXT: andl $7, %edi
; KNL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; KNL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v8f64: ; SKX-LABEL: test_extractelement_variable_v8f64:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi9:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi10:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi11:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $7, %edi ; SKX-NEXT: andl $7, %edi
; SKX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; SKX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
Show All 15 Lines; CHECK-NEXT: retq
%t2 = extractelement <4 x i32> %t1, i32 %index %t2 = extractelement <4 x i32> %t1, i32 %index
ret i32 %t2 ret i32 %t2
} }
define i32 @test_extractelement_variable_v8i32(<8 x i32> %t1, i32 %index) { define i32 @test_extractelement_variable_v8i32(<8 x i32> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v8i32: ; KNL-LABEL: test_extractelement_variable_v8i32:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi15:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi16:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi17:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $7, %edi ; KNL-NEXT: andl $7, %edi
; KNL-NEXT: movl (%rsp,%rdi,4), %eax ; KNL-NEXT: movl (%rsp,%rdi,4), %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v8i32: ; SKX-LABEL: test_extractelement_variable_v8i32:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi12:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi13:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi14:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $7, %edi ; SKX-NEXT: andl $7, %edi
; SKX-NEXT: movl (%rsp,%rdi,4), %eax ; SKX-NEXT: movl (%rsp,%rdi,4), %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <8 x i32> %t1, i32 %index %t2 = extractelement <8 x i32> %t1, i32 %index
ret i32 %t2 ret i32 %t2
} }
define i32 @test_extractelement_variable_v16i32(<16 x i32> %t1, i32 %index) { define i32 @test_extractelement_variable_v16i32(<16 x i32> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v16i32: ; KNL-LABEL: test_extractelement_variable_v16i32:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi18:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi19:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi20:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %zmm0, (%rsp) ; KNL-NEXT: vmovaps %zmm0, (%rsp)
; KNL-NEXT: andl $15, %edi ; KNL-NEXT: andl $15, %edi
; KNL-NEXT: movl (%rsp,%rdi,4), %eax ; KNL-NEXT: movl (%rsp,%rdi,4), %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v16i32: ; SKX-LABEL: test_extractelement_variable_v16i32:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi15:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi16:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi17:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $15, %edi ; SKX-NEXT: andl $15, %edi
; SKX-NEXT: movl (%rsp,%rdi,4), %eax ; SKX-NEXT: movl (%rsp,%rdi,4), %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
Show All 15 Lines; CHECK-NEXT: retq
%t2 = extractelement <4 x float> %t1, i32 %index %t2 = extractelement <4 x float> %t1, i32 %index
ret float %t2 ret float %t2
} }
define float @test_extractelement_variable_v8f32(<8 x float> %t1, i32 %index) { define float @test_extractelement_variable_v8f32(<8 x float> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v8f32: ; KNL-LABEL: test_extractelement_variable_v8f32:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi21:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi22:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi23:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $7, %edi ; KNL-NEXT: andl $7, %edi
; KNL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; KNL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v8f32: ; SKX-LABEL: test_extractelement_variable_v8f32:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi18:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi19:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi20:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $7, %edi ; SKX-NEXT: andl $7, %edi
; SKX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SKX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <8 x float> %t1, i32 %index %t2 = extractelement <8 x float> %t1, i32 %index
ret float %t2 ret float %t2
} }
define float @test_extractelement_variable_v16f32(<16 x float> %t1, i32 %index) { define float @test_extractelement_variable_v16f32(<16 x float> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v16f32: ; KNL-LABEL: test_extractelement_variable_v16f32:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi24:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi25:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi26:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %zmm0, (%rsp) ; KNL-NEXT: vmovaps %zmm0, (%rsp)
; KNL-NEXT: andl $15, %edi ; KNL-NEXT: andl $15, %edi
; KNL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; KNL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v16f32: ; SKX-LABEL: test_extractelement_variable_v16f32:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi21:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi22:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi23:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $15, %edi ; SKX-NEXT: andl $15, %edi
; SKX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SKX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
Show All 15 Lines; CHECK-NEXT: retq
%t2 = extractelement <8 x i16> %t1, i32 %index %t2 = extractelement <8 x i16> %t1, i32 %index
ret i16 %t2 ret i16 %t2
} }
define i16 @test_extractelement_variable_v16i16(<16 x i16> %t1, i32 %index) { define i16 @test_extractelement_variable_v16i16(<16 x i16> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v16i16: ; KNL-LABEL: test_extractelement_variable_v16i16:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi27:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi28:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi29:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $15, %edi ; KNL-NEXT: andl $15, %edi
; KNL-NEXT: movzwl (%rsp,%rdi,2), %eax ; KNL-NEXT: movzwl (%rsp,%rdi,2), %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v16i16: ; SKX-LABEL: test_extractelement_variable_v16i16:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi24:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi25:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi26:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $15, %edi ; SKX-NEXT: andl $15, %edi
; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax ; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <16 x i16> %t1, i32 %index %t2 = extractelement <16 x i16> %t1, i32 %index
ret i16 %t2 ret i16 %t2
} }
define i16 @test_extractelement_variable_v32i16(<32 x i16> %t1, i32 %index) { define i16 @test_extractelement_variable_v32i16(<32 x i16> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v32i16: ; KNL-LABEL: test_extractelement_variable_v32i16:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi30:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi31:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi32:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) ; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $31, %edi ; KNL-NEXT: andl $31, %edi
; KNL-NEXT: movzwl (%rsp,%rdi,2), %eax ; KNL-NEXT: movzwl (%rsp,%rdi,2), %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v32i16: ; SKX-LABEL: test_extractelement_variable_v32i16:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi27:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi28:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi29:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $31, %edi ; SKX-NEXT: andl $31, %edi
; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax ; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
Show All 16 Lines; CHECK-NEXT: retq
%t2 = extractelement <16 x i8> %t1, i32 %index %t2 = extractelement <16 x i8> %t1, i32 %index
ret i8 %t2 ret i8 %t2
} }
define i8 @test_extractelement_variable_v32i8(<32 x i8> %t1, i32 %index) { define i8 @test_extractelement_variable_v32i8(<32 x i8> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v32i8: ; KNL-LABEL: test_extractelement_variable_v32i8:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi33:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi34:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi35:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $31, %edi ; KNL-NEXT: andl $31, %edi
; KNL-NEXT: movq %rsp, %rax ; KNL-NEXT: movq %rsp, %rax
; KNL-NEXT: movb (%rdi,%rax), %al ; KNL-NEXT: movb (%rdi,%rax), %al
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v32i8: ; SKX-LABEL: test_extractelement_variable_v32i8:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi30:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi31:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi32:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-32, %rsp ; SKX-NEXT: andq $-32, %rsp
; SKX-NEXT: subq $64, %rsp ; SKX-NEXT: subq $64, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %ymm0, (%rsp) ; SKX-NEXT: vmovaps %ymm0, (%rsp)
; SKX-NEXT: andl $31, %edi ; SKX-NEXT: andl $31, %edi
; SKX-NEXT: movq %rsp, %rax ; SKX-NEXT: movq %rsp, %rax
; SKX-NEXT: movb (%rdi,%rax), %al ; SKX-NEXT: movb (%rdi,%rax), %al
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <32 x i8> %t1, i32 %index %t2 = extractelement <32 x i8> %t1, i32 %index
ret i8 %t2 ret i8 %t2
} }
define i8 @test_extractelement_variable_v64i8(<64 x i8> %t1, i32 %index) { define i8 @test_extractelement_variable_v64i8(<64 x i8> %t1, i32 %index) {
; KNL-LABEL: test_extractelement_variable_v64i8: ; KNL-LABEL: test_extractelement_variable_v64i8:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi36:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi37:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi38:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) ; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: andl $63, %edi ; KNL-NEXT: andl $63, %edi
; KNL-NEXT: movq %rsp, %rax ; KNL-NEXT: movq %rsp, %rax
; KNL-NEXT: movb (%rdi,%rax), %al ; KNL-NEXT: movb (%rdi,%rax), %al
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v64i8: ; SKX-LABEL: test_extractelement_variable_v64i8:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi33:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi34:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi35:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: andl $63, %edi ; SKX-NEXT: andl $63, %edi
; SKX-NEXT: movq %rsp, %rax ; SKX-NEXT: movq %rsp, %rax
; SKX-NEXT: movb (%rdi,%rax), %al ; SKX-NEXT: movb (%rdi,%rax), %al
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t2 = extractelement <64 x i8> %t1, i32 %index %t2 = extractelement <64 x i8> %t1, i32 %index
ret i8 %t2 ret i8 %t2
} }
define i8 @test_extractelement_variable_v64i8_indexi8(<64 x i8> %t1, i8 %index) { define i8 @test_extractelement_variable_v64i8_indexi8(<64 x i8> %t1, i8 %index) {
; KNL-LABEL: test_extractelement_variable_v64i8_indexi8: ; KNL-LABEL: test_extractelement_variable_v64i8_indexi8:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi39:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi40:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi41:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: addb %dil, %dil ; KNL-NEXT: addb %dil, %dil
; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) ; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp)
; KNL-NEXT: movzbl %dil, %eax ; KNL-NEXT: movzbl %dil, %eax
; KNL-NEXT: andl $63, %eax ; KNL-NEXT: andl $63, %eax
; KNL-NEXT: movq %rsp, %rcx ; KNL-NEXT: movq %rsp, %rcx
; KNL-NEXT: movb (%rax,%rcx), %al ; KNL-NEXT: movb (%rax,%rcx), %al
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_variable_v64i8_indexi8: ; SKX-LABEL: test_extractelement_variable_v64i8_indexi8:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi36:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi37:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi38:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: addb %dil, %dil ; SKX-NEXT: addb %dil, %dil
; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: vmovaps %zmm0, (%rsp)
; SKX-NEXT: movzbl %dil, %eax ; SKX-NEXT: movzbl %dil, %eax
; SKX-NEXT: andl $63, %eax ; SKX-NEXT: andl $63, %eax
; SKX-NEXT: movq %rsp, %rcx ; SKX-NEXT: movq %rsp, %rcx
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%res = zext i1 %t2 to i8 %res = zext i1 %t2 to i8
ret i8 %res ret i8 %res
} }
define zeroext i8 @test_extractelement_varible_v8i1(<8 x i32> %a, <8 x i32> %b, i32 %index) { define zeroext i8 @test_extractelement_varible_v8i1(<8 x i32> %a, <8 x i32> %b, i32 %index) {
; KNL-LABEL: test_extractelement_varible_v8i1: ; KNL-LABEL: test_extractelement_varible_v8i1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi42:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi43:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi44:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1 ; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa64 %zmm0, (%rsp) ; KNL-NEXT: vmovdqa64 %zmm0, (%rsp)
; KNL-NEXT: andl $7, %edi ; KNL-NEXT: andl $7, %edi
; KNL-NEXT: movzbl (%rsp,%rdi,8), %eax ; KNL-NEXT: movzbl (%rsp,%rdi,8), %eax
; KNL-NEXT: andl $1, %eax ; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_varible_v8i1: ; SKX-LABEL: test_extractelement_varible_v8i1:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi39:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi40:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi41:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0 ; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2q %k0, %zmm0 ; SKX-NEXT: vpmovm2q %k0, %zmm0
; SKX-NEXT: vmovdqa64 %zmm0, (%rsp) ; SKX-NEXT: vmovdqa64 %zmm0, (%rsp)
; SKX-NEXT: andl $7, %edi ; SKX-NEXT: andl $7, %edi
; SKX-NEXT: movzbl (%rsp,%rdi,8), %eax ; SKX-NEXT: movzbl (%rsp,%rdi,8), %eax
; SKX-NEXT: andl $1, %eax ; SKX-NEXT: andl $1, %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t1 = icmp ugt <8 x i32> %a, %b %t1 = icmp ugt <8 x i32> %a, %b
%t2 = extractelement <8 x i1> %t1, i32 %index %t2 = extractelement <8 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8 %res = zext i1 %t2 to i8
ret i8 %res ret i8 %res
} }
define zeroext i8 @test_extractelement_varible_v16i1(<16 x i32> %a, <16 x i32> %b, i32 %index) { define zeroext i8 @test_extractelement_varible_v16i1(<16 x i32> %a, <16 x i32> %b, i32 %index) {
; KNL-LABEL: test_extractelement_varible_v16i1: ; KNL-LABEL: test_extractelement_varible_v16i1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi45:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi46:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi47:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: andq $-64, %rsp
; KNL-NEXT: subq $128, %rsp ; KNL-NEXT: subq $128, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1 ; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vmovdqa32 %zmm0, (%rsp) ; KNL-NEXT: vmovdqa32 %zmm0, (%rsp)
; KNL-NEXT: andl $15, %edi ; KNL-NEXT: andl $15, %edi
; KNL-NEXT: movzbl (%rsp,%rdi,4), %eax ; KNL-NEXT: movzbl (%rsp,%rdi,4), %eax
; KNL-NEXT: andl $1, %eax ; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_varible_v16i1: ; SKX-LABEL: test_extractelement_varible_v16i1:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi42:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi43:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi44:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0 ; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %zmm0 ; SKX-NEXT: vpmovm2d %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
; SKX-NEXT: andl $15, %edi ; SKX-NEXT: andl $15, %edi
; SKX-NEXT: movzbl (%rsp,%rdi,4), %eax ; SKX-NEXT: movzbl (%rsp,%rdi,4), %eax
; SKX-NEXT: andl $1, %eax ; SKX-NEXT: andl $1, %eax
; SKX-NEXT: movq %rbp, %rsp ; SKX-NEXT: movq %rbp, %rsp
; SKX-NEXT: popq %rbp ; SKX-NEXT: popq %rbp
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
%t1 = icmp ugt <16 x i32> %a, %b %t1 = icmp ugt <16 x i32> %a, %b
%t2 = extractelement <16 x i1> %t1, i32 %index %t2 = extractelement <16 x i1> %t1, i32 %index
%res = zext i1 %t2 to i8 %res = zext i1 %t2 to i8
ret i8 %res ret i8 %res
} }
define zeroext i8 @test_extractelement_varible_v32i1(<32 x i8> %a, <32 x i8> %b, i32 %index) { define zeroext i8 @test_extractelement_varible_v32i1(<32 x i8> %a, <32 x i8> %b, i32 %index) {
; KNL-LABEL: test_extractelement_varible_v32i1: ; KNL-LABEL: test_extractelement_varible_v32i1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi48:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi49:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi50:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1
; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0
; KNL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; KNL-NEXT: vmovdqa %ymm0, (%rsp) ; KNL-NEXT: vmovdqa %ymm0, (%rsp)
; KNL-NEXT: andl $31, %edi ; KNL-NEXT: andl $31, %edi
; KNL-NEXT: movq %rsp, %rax ; KNL-NEXT: movq %rsp, %rax
; KNL-NEXT: movzbl (%rdi,%rax), %eax ; KNL-NEXT: movzbl (%rdi,%rax), %eax
; KNL-NEXT: andl $1, %eax ; KNL-NEXT: andl $1, %eax
; KNL-NEXT: movq %rbp, %rsp ; KNL-NEXT: movq %rbp, %rsp
; KNL-NEXT: popq %rbp ; KNL-NEXT: popq %rbp
; KNL-NEXT: vzeroupper ; KNL-NEXT: vzeroupper
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test_extractelement_varible_v32i1: ; SKX-LABEL: test_extractelement_varible_v32i1:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi45:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi46:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi47:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0 ; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %zmm0 ; SKX-NEXT: vpmovm2w %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
; SKX-NEXT: andl $31, %edi ; SKX-NEXT: andl $31, %edi
Show All 23 Lines

llvm/trunk/test/CodeGen/X86/avx512-insert-extract_i1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX --check-prefix=SKX_ONLY %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX --check-prefix=SKX_ONLY %s
; TODO - fix fail on KNL and move this test to avx512-insert-extract.ll ; TODO - fix fail on KNL and move this test to avx512-insert-extract.ll
define zeroext i8 @test_extractelement_varible_v64i1(<64 x i8> %a, <64 x i8> %b, i32 %index) { define zeroext i8 @test_extractelement_varible_v64i1(<64 x i8> %a, <64 x i8> %b, i32 %index) {
; SKX-LABEL: test_extractelement_varible_v64i1: ; SKX-LABEL: test_extractelement_varible_v64i1:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: pushq %rbp ; SKX-NEXT: pushq %rbp
; SKX-NEXT: Lcfi0:
; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: Lcfi1:
; SKX-NEXT: .cfi_offset %rbp, -16 ; SKX-NEXT: .cfi_offset %rbp, -16
; SKX-NEXT: movq %rsp, %rbp ; SKX-NEXT: movq %rsp, %rbp
; SKX-NEXT: Lcfi2:
; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: .cfi_def_cfa_register %rbp
; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: andq $-64, %rsp
; SKX-NEXT: subq $128, %rsp ; SKX-NEXT: subq $128, %rsp
; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> ; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0 ; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %zmm0 ; SKX-NEXT: vpmovm2b %k0, %zmm0
; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp)
; SKX-NEXT: andl $63, %edi ; SKX-NEXT: andl $63, %edi
Show All 13 Lines

llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll

Show First 20 Lines • Show All 928 Lines • ▼ Show 20 Lines; AVX512DQ-NEXT: retq
ret <16 x i1> %c ret <16 x i1> %c
} }
define <64 x i8> @test16(i64 %x) { define <64 x i8> @test16(i64 %x) {
; ;
; KNL-LABEL: test16: ; KNL-LABEL: test16:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: movl %edi, (%rsp) ; KNL-NEXT: movl %edi, (%rsp)
; KNL-NEXT: shrq $32, %rdi ; KNL-NEXT: shrq $32, %rdi
; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; KNL-NEXT: kmovw (%rsp), %k1 ; KNL-NEXT: kmovw (%rsp), %k1
; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] ; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: test16: ; AVX512DQ-LABEL: test16:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: pushq %rbp ; AVX512DQ-NEXT: pushq %rbp
; AVX512DQ-NEXT: Lcfi0:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16
; AVX512DQ-NEXT: Lcfi1:
; AVX512DQ-NEXT: .cfi_offset %rbp, -16 ; AVX512DQ-NEXT: .cfi_offset %rbp, -16
; AVX512DQ-NEXT: movq %rsp, %rbp ; AVX512DQ-NEXT: movq %rsp, %rbp
; AVX512DQ-NEXT: Lcfi2:
; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp ; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp
; AVX512DQ-NEXT: andq $-32, %rsp ; AVX512DQ-NEXT: andq $-32, %rsp
; AVX512DQ-NEXT: subq $64, %rsp ; AVX512DQ-NEXT: subq $64, %rsp
; AVX512DQ-NEXT: movl %edi, (%rsp) ; AVX512DQ-NEXT: movl %edi, (%rsp)
; AVX512DQ-NEXT: shrq $32, %rdi ; AVX512DQ-NEXT: shrq $32, %rdi
; AVX512DQ-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX512DQ-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX512DQ-NEXT: kmovw (%rsp), %k0 ; AVX512DQ-NEXT: kmovw (%rsp), %k0
; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
Show All 24 Lines; AVX512DQ-NEXT: retq
ret <64 x i8>%c ret <64 x i8>%c
} }
define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) { define <64 x i8> @test17(i64 %x, i32 %y, i32 %z) {
; ;
; KNL-LABEL: test17: ; KNL-LABEL: test17:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi3:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi4:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi5:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp ; KNL-NEXT: subq $64, %rsp
; KNL-NEXT: movl %edi, (%rsp) ; KNL-NEXT: movl %edi, (%rsp)
; KNL-NEXT: shrq $32, %rdi ; KNL-NEXT: shrq $32, %rdi
; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; KNL-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; KNL-NEXT: kmovw (%rsp), %k1 ; KNL-NEXT: kmovw (%rsp), %k1
; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; KNL-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] ; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: test17: ; AVX512DQ-LABEL: test17:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: pushq %rbp ; AVX512DQ-NEXT: pushq %rbp
; AVX512DQ-NEXT: Lcfi3:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16
; AVX512DQ-NEXT: Lcfi4:
; AVX512DQ-NEXT: .cfi_offset %rbp, -16 ; AVX512DQ-NEXT: .cfi_offset %rbp, -16
; AVX512DQ-NEXT: movq %rsp, %rbp ; AVX512DQ-NEXT: movq %rsp, %rbp
; AVX512DQ-NEXT: Lcfi5:
; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp ; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp
; AVX512DQ-NEXT: andq $-32, %rsp ; AVX512DQ-NEXT: andq $-32, %rsp
; AVX512DQ-NEXT: subq $64, %rsp ; AVX512DQ-NEXT: subq $64, %rsp
; AVX512DQ-NEXT: movl %edi, (%rsp) ; AVX512DQ-NEXT: movl %edi, (%rsp)
; AVX512DQ-NEXT: shrq $32, %rdi ; AVX512DQ-NEXT: shrq $32, %rdi
; AVX512DQ-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX512DQ-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX512DQ-NEXT: kmovw (%rsp), %k0 ; AVX512DQ-NEXT: kmovw (%rsp), %k0
; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512DQ-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
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ret void ret void
} }
define void @ktest_2(<32 x float> %in, float * %base) { define void @ktest_2(<32 x float> %in, float * %base) {
; ;
; KNL-LABEL: ktest_2: ; KNL-LABEL: ktest_2:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi6:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: Lcfi7:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp ; KNL-NEXT: movq %rsp, %rbp
; KNL-NEXT: Lcfi8:
; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $32, %rsp ; KNL-NEXT: subq $32, %rsp
; KNL-NEXT: vmovups (%rdi), %zmm2 ; KNL-NEXT: vmovups (%rdi), %zmm2
; KNL-NEXT: vmovups 64(%rdi), %zmm3 ; KNL-NEXT: vmovups 64(%rdi), %zmm3
; KNL-NEXT: vcmpltps %zmm1, %zmm3, %k1 ; KNL-NEXT: vcmpltps %zmm1, %zmm3, %k1
; KNL-NEXT: kshiftlw $14, %k1, %k0 ; KNL-NEXT: kshiftlw $14, %k1, %k0
; KNL-NEXT: kshiftrw $15, %k0, %k0 ; KNL-NEXT: kshiftrw $15, %k0, %k0
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; AVX512BW-NEXT: vmovaps %zmm0, 4(%rdi) ; AVX512BW-NEXT: vmovaps %zmm0, 4(%rdi)
; AVX512BW-NEXT: vmovaps %zmm1, 68(%rdi) ; AVX512BW-NEXT: vmovaps %zmm1, 68(%rdi)
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: ktest_2: ; AVX512DQ-LABEL: ktest_2:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: pushq %rbp ; AVX512DQ-NEXT: pushq %rbp
; AVX512DQ-NEXT: Lcfi6:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16
; AVX512DQ-NEXT: Lcfi7:
; AVX512DQ-NEXT: .cfi_offset %rbp, -16 ; AVX512DQ-NEXT: .cfi_offset %rbp, -16
; AVX512DQ-NEXT: movq %rsp, %rbp ; AVX512DQ-NEXT: movq %rsp, %rbp
; AVX512DQ-NEXT: Lcfi8:
; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp ; AVX512DQ-NEXT: .cfi_def_cfa_register %rbp
; AVX512DQ-NEXT: andq $-32, %rsp ; AVX512DQ-NEXT: andq $-32, %rsp
; AVX512DQ-NEXT: subq $32, %rsp ; AVX512DQ-NEXT: subq $32, %rsp
; AVX512DQ-NEXT: vmovups (%rdi), %zmm2 ; AVX512DQ-NEXT: vmovups (%rdi), %zmm2
; AVX512DQ-NEXT: vmovups 64(%rdi), %zmm3 ; AVX512DQ-NEXT: vmovups 64(%rdi), %zmm3
; AVX512DQ-NEXT: vcmpltps %zmm1, %zmm3, %k1 ; AVX512DQ-NEXT: vcmpltps %zmm1, %zmm3, %k1
; AVX512DQ-NEXT: kshiftlw $14, %k1, %k0 ; AVX512DQ-NEXT: kshiftlw $14, %k1, %k0
; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0 ; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0
▲ Show 20 Lines • Show All 751 Lines • ▼ Show 20 Lines
} }
define void @store_64i1(<64 x i1>* %a, <64 x i1> %v) { define void @store_64i1(<64 x i1>* %a, <64 x i1> %v) {
; ;
; KNL-LABEL: store_64i1: ; KNL-LABEL: store_64i1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp ; KNL-NEXT: pushq %rbp
; KNL-NEXT: Lcfi9:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: pushq %r15 ; KNL-NEXT: pushq %r15
; KNL-NEXT: Lcfi10:
; KNL-NEXT: .cfi_def_cfa_offset 24 ; KNL-NEXT: .cfi_def_cfa_offset 24
; KNL-NEXT: pushq %r14 ; KNL-NEXT: pushq %r14
; KNL-NEXT: Lcfi11:
; KNL-NEXT: .cfi_def_cfa_offset 32 ; KNL-NEXT: .cfi_def_cfa_offset 32
; KNL-NEXT: pushq %r13 ; KNL-NEXT: pushq %r13
; KNL-NEXT: Lcfi12:
; KNL-NEXT: .cfi_def_cfa_offset 40 ; KNL-NEXT: .cfi_def_cfa_offset 40
; KNL-NEXT: pushq %r12 ; KNL-NEXT: pushq %r12
; KNL-NEXT: Lcfi13:
; KNL-NEXT: .cfi_def_cfa_offset 48 ; KNL-NEXT: .cfi_def_cfa_offset 48
; KNL-NEXT: pushq %rbx ; KNL-NEXT: pushq %rbx
; KNL-NEXT: Lcfi14:
; KNL-NEXT: .cfi_def_cfa_offset 56 ; KNL-NEXT: .cfi_def_cfa_offset 56
; KNL-NEXT: Lcfi15:
; KNL-NEXT: .cfi_offset %rbx, -56 ; KNL-NEXT: .cfi_offset %rbx, -56
; KNL-NEXT: Lcfi16:
; KNL-NEXT: .cfi_offset %r12, -48 ; KNL-NEXT: .cfi_offset %r12, -48
; KNL-NEXT: Lcfi17:
; KNL-NEXT: .cfi_offset %r13, -40 ; KNL-NEXT: .cfi_offset %r13, -40
; KNL-NEXT: Lcfi18:
; KNL-NEXT: .cfi_offset %r14, -32 ; KNL-NEXT: .cfi_offset %r14, -32
; KNL-NEXT: Lcfi19:
; KNL-NEXT: .cfi_offset %r15, -24 ; KNL-NEXT: .cfi_offset %r15, -24
; KNL-NEXT: Lcfi20:
; KNL-NEXT: .cfi_offset %rbp, -16 ; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 ; KNL-NEXT: vpmovsxbd %xmm0, %zmm0
; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL-NEXT: vpslld $31, %zmm1, %zmm1
; KNL-NEXT: vpmovsxbd %xmm2, %zmm2 ; KNL-NEXT: vpmovsxbd %xmm2, %zmm2
; KNL-NEXT: vpslld $31, %zmm2, %zmm2 ; KNL-NEXT: vpslld $31, %zmm2, %zmm2
; KNL-NEXT: vpmovsxbd %xmm3, %zmm3 ; KNL-NEXT: vpmovsxbd %xmm3, %zmm3
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; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, (%rdi) ; AVX512BW-NEXT: kmovq %k0, (%rdi)
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512DQ-LABEL: store_64i1: ; AVX512DQ-LABEL: store_64i1:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: pushq %rbp ; AVX512DQ-NEXT: pushq %rbp
; AVX512DQ-NEXT: Lcfi9:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16
; AVX512DQ-NEXT: pushq %r15 ; AVX512DQ-NEXT: pushq %r15
; AVX512DQ-NEXT: Lcfi10:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 24 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 24
; AVX512DQ-NEXT: pushq %r14 ; AVX512DQ-NEXT: pushq %r14
; AVX512DQ-NEXT: Lcfi11:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 32 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 32
; AVX512DQ-NEXT: pushq %r13 ; AVX512DQ-NEXT: pushq %r13
; AVX512DQ-NEXT: Lcfi12:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 40 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 40
; AVX512DQ-NEXT: pushq %r12 ; AVX512DQ-NEXT: pushq %r12
; AVX512DQ-NEXT: Lcfi13:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 48 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 48
; AVX512DQ-NEXT: pushq %rbx ; AVX512DQ-NEXT: pushq %rbx
; AVX512DQ-NEXT: Lcfi14:
; AVX512DQ-NEXT: .cfi_def_cfa_offset 56 ; AVX512DQ-NEXT: .cfi_def_cfa_offset 56
; AVX512DQ-NEXT: Lcfi15:
; AVX512DQ-NEXT: .cfi_offset %rbx, -56 ; AVX512DQ-NEXT: .cfi_offset %rbx, -56
; AVX512DQ-NEXT: Lcfi16:
; AVX512DQ-NEXT: .cfi_offset %r12, -48 ; AVX512DQ-NEXT: .cfi_offset %r12, -48
; AVX512DQ-NEXT: Lcfi17:
; AVX512DQ-NEXT: .cfi_offset %r13, -40 ; AVX512DQ-NEXT: .cfi_offset %r13, -40
; AVX512DQ-NEXT: Lcfi18:
; AVX512DQ-NEXT: .cfi_offset %r14, -32 ; AVX512DQ-NEXT: .cfi_offset %r14, -32
; AVX512DQ-NEXT: Lcfi19:
; AVX512DQ-NEXT: .cfi_offset %r15, -24 ; AVX512DQ-NEXT: .cfi_offset %r15, -24
; AVX512DQ-NEXT: Lcfi20:
; AVX512DQ-NEXT: .cfi_offset %rbp, -16 ; AVX512DQ-NEXT: .cfi_offset %rbp, -16
; AVX512DQ-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512DQ-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512DQ-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpslld $31, %zmm0, %zmm0
; AVX512DQ-NEXT: vpmovsxbd %xmm1, %zmm1 ; AVX512DQ-NEXT: vpmovsxbd %xmm1, %zmm1
; AVX512DQ-NEXT: vpslld $31, %zmm1, %zmm1 ; AVX512DQ-NEXT: vpslld $31, %zmm1, %zmm1
; AVX512DQ-NEXT: vpmovsxbd %xmm2, %zmm2 ; AVX512DQ-NEXT: vpmovsxbd %xmm2, %zmm2
; AVX512DQ-NEXT: vpslld $31, %zmm2, %zmm2 ; AVX512DQ-NEXT: vpslld $31, %zmm2, %zmm2
; AVX512DQ-NEXT: vpmovsxbd %xmm3, %zmm3 ; AVX512DQ-NEXT: vpmovsxbd %xmm3, %zmm3
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llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
declare void @f() declare void @f()
define <4 x i1> @test_4i1(<4 x i32> %a, <4 x i32> %b) { define <4 x i1> @test_4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_4i1: ; CHECK-LABEL: test_4i1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %xmm1, %xmm0, %k0 ; CHECK-NEXT: vpcmpnleud %xmm1, %xmm0, %k0
; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k1 ; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k1
; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
; CHECK-NEXT: callq _f ; CHECK-NEXT: callq _f
; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload ; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
; CHECK-NEXT: vpmovm2d %k0, %xmm0 ; CHECK-NEXT: vpmovm2d %k0, %xmm0
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp_res = icmp ugt <4 x i32> %a, %b %cmp_res = icmp ugt <4 x i32> %a, %b
%cmp_res2 = icmp sgt <4 x i32> %a, %b %cmp_res2 = icmp sgt <4 x i32> %a, %b
call void @f() call void @f()
%res = or <4 x i1> %cmp_res, %cmp_res2 %res = or <4 x i1> %cmp_res, %cmp_res2
ret <4 x i1> %res ret <4 x i1> %res
} }
define <8 x i1> @test_8i1(<8 x i32> %a, <8 x i32> %b) { define <8 x i1> @test_8i1(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: test_8i1: ; CHECK-LABEL: test_8i1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %ymm1, %ymm0, %k0 ; CHECK-NEXT: vpcmpnleud %ymm1, %ymm0, %k0
; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k1 ; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k1
; CHECK-NEXT: korb %k1, %k0, %k0 ; CHECK-NEXT: korb %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq _f ; CHECK-NEXT: callq _f
; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload ; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
; CHECK-NEXT: vpmovm2w %k0, %xmm0 ; CHECK-NEXT: vpmovm2w %k0, %xmm0
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp_res = icmp ugt <8 x i32> %a, %b %cmp_res = icmp ugt <8 x i32> %a, %b
%cmp_res2 = icmp sgt <8 x i32> %a, %b %cmp_res2 = icmp sgt <8 x i32> %a, %b
call void @f() call void @f()
%res = or <8 x i1> %cmp_res, %cmp_res2 %res = or <8 x i1> %cmp_res, %cmp_res2
ret <8 x i1> %res ret <8 x i1> %res
} }
define <16 x i1> @test_16i1(<16 x i32> %a, <16 x i32> %b) { define <16 x i1> @test_16i1(<16 x i32> %a, <16 x i32> %b) {
; CHECK-LABEL: test_16i1: ; CHECK-LABEL: test_16i1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %zmm1, %zmm0, %k0 ; CHECK-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq _f ; CHECK-NEXT: callq _f
; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload ; CHECK-NEXT: kmovw {{[0-9]+}}(%rsp), %k0 ## 2-byte Reload
; CHECK-NEXT: vpmovm2b %k0, %xmm0 ; CHECK-NEXT: vpmovm2b %k0, %xmm0
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp_res = icmp ugt <16 x i32> %a, %b %cmp_res = icmp ugt <16 x i32> %a, %b
%cmp_res2 = icmp sgt <16 x i32> %a, %b %cmp_res2 = icmp sgt <16 x i32> %a, %b
call void @f() call void @f()
%res = or <16 x i1> %cmp_res, %cmp_res2 %res = or <16 x i1> %cmp_res, %cmp_res2
ret <16 x i1> %res ret <16 x i1> %res
} }
define <32 x i1> @test_32i1(<32 x i16> %a, <32 x i16> %b) { define <32 x i1> @test_32i1(<32 x i16> %a, <32 x i16> %b) {
; CHECK-LABEL: test_32i1: ; CHECK-LABEL: test_32i1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleuw %zmm1, %zmm0, %k0 ; CHECK-NEXT: vpcmpnleuw %zmm1, %zmm0, %k0
; CHECK-NEXT: vpcmpgtw %zmm1, %zmm0, %k1 ; CHECK-NEXT: vpcmpgtw %zmm1, %zmm0, %k1
; CHECK-NEXT: kord %k1, %k0, %k0 ; CHECK-NEXT: kord %k1, %k0, %k0
; CHECK-NEXT: kmovd %k0, {{[0-9]+}}(%rsp) ## 4-byte Spill ; CHECK-NEXT: kmovd %k0, {{[0-9]+}}(%rsp) ## 4-byte Spill
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq _f ; CHECK-NEXT: callq _f
; CHECK-NEXT: kmovd {{[0-9]+}}(%rsp), %k0 ## 4-byte Reload ; CHECK-NEXT: kmovd {{[0-9]+}}(%rsp), %k0 ## 4-byte Reload
; CHECK-NEXT: vpmovm2b %k0, %ymm0 ; CHECK-NEXT: vpmovm2b %k0, %ymm0
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp_res = icmp ugt <32 x i16> %a, %b %cmp_res = icmp ugt <32 x i16> %a, %b
%cmp_res2 = icmp sgt <32 x i16> %a, %b %cmp_res2 = icmp sgt <32 x i16> %a, %b
call void @f() call void @f()
%res = or <32 x i1> %cmp_res, %cmp_res2 %res = or <32 x i1> %cmp_res, %cmp_res2
ret <32 x i1> %res ret <32 x i1> %res
} }
define <64 x i1> @test_64i1(<64 x i8> %a, <64 x i8> %b) { define <64 x i1> @test_64i1(<64 x i8> %a, <64 x i8> %b) {
; CHECK-LABEL: test_64i1: ; CHECK-LABEL: test_64i1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi4:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleub %zmm1, %zmm0, %k0 ; CHECK-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; CHECK-NEXT: vpcmpgtb %zmm1, %zmm0, %k1 ; CHECK-NEXT: vpcmpgtb %zmm1, %zmm0, %k1
; CHECK-NEXT: korq %k1, %k0, %k0 ; CHECK-NEXT: korq %k1, %k0, %k0
; CHECK-NEXT: kmovq %k0, (%rsp) ## 8-byte Spill ; CHECK-NEXT: kmovq %k0, (%rsp) ## 8-byte Spill
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq _f ; CHECK-NEXT: callq _f
; CHECK-NEXT: kmovq (%rsp), %k0 ## 8-byte Reload ; CHECK-NEXT: kmovq (%rsp), %k0 ## 8-byte Reload
Show All 10 Lines

llvm/trunk/test/CodeGen/X86/avx512-mask-zext-bugfix.ll

Show All 12 Lines
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
declare i32 @check_mask16(i16 zeroext %res_mask, i16 zeroext %exp_mask, i8* %fname, i8* %input) declare i32 @check_mask16(i16 zeroext %res_mask, i16 zeroext %exp_mask, i8* %fname, i8* %input)
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_xmm(i32 %shift, i32 %mulp, <2 x i64> %a,i8* %arraydecay,i8* %fname){ define void @test_xmm(i32 %shift, i32 %mulp, <2 x i64> %a,i8* %arraydecay,i8* %fname){
; CHECK-LABEL: test_xmm: ; CHECK-LABEL: test_xmm:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movl $2, %esi ; CHECK-NEXT: movl $2, %esi
; CHECK-NEXT: movl $8, %eax ; CHECK-NEXT: movl $8, %eax
; CHECK-NEXT: vpmovw2m %xmm0, %k0 ; CHECK-NEXT: vpmovw2m %xmm0, %k0
; CHECK-NEXT: kmovd %k0, %edi ; CHECK-NEXT: kmovd %k0, %edi
; CHECK-NEXT: movb %dil, %r8b ; CHECK-NEXT: movb %dil, %r8b
; CHECK-NEXT: movzbl %r8b, %edi ; CHECK-NEXT: movzbl %r8b, %edi
; CHECK-NEXT: movw %di, %r9w ; CHECK-NEXT: movw %di, %r9w
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llvm/trunk/test/CodeGen/X86/avx512-schedule.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,170 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq # sched: [7:1.00]
ret <8 x i64>%res ret <8 x i64>%res
} }
declare void @func_f32(float) declare void @func_f32(float)
define <16 x float> @broadcast_ss_spill(float %x) { define <16 x float> @broadcast_ss_spill(float %x) {
; CHECK-LABEL: broadcast_ss_spill: ; CHECK-LABEL: broadcast_ss_spill:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $24, %rsp # sched: [1:0.25] ; CHECK-NEXT: subq $24, %rsp # sched: [1:0.25]
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0 # sched: [4:0.33] ; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0 # sched: [4:0.33]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill sched: [1:1.00] ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill sched: [1:1.00]
; CHECK-NEXT: # sched: [1:1.00] ; CHECK-NEXT: # sched: [1:1.00]
; CHECK-NEXT: callq func_f32 ; CHECK-NEXT: callq func_f32
; CHECK-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50] ; CHECK-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50]
; CHECK-NEXT: # sched: [8:0.50] ; CHECK-NEXT: # sched: [8:0.50]
; CHECK-NEXT: addq $24, %rsp # sched: [1:0.25] ; CHECK-NEXT: addq $24, %rsp # sched: [1:0.25]
; CHECK-NEXT: retq # sched: [7:1.00] ; CHECK-NEXT: retq # sched: [7:1.00]
%a = fadd float %x, %x %a = fadd float %x, %x
call void @func_f32(float %a) call void @func_f32(float %a)
%b = insertelement <16 x float> undef, float %a, i32 0 %b = insertelement <16 x float> undef, float %a, i32 0
%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
ret <16 x float> %c ret <16 x float> %c
} }
declare void @func_f64(double) declare void @func_f64(double)
define <8 x double> @broadcast_sd_spill(double %x) { define <8 x double> @broadcast_sd_spill(double %x) {
; CHECK-LABEL: broadcast_sd_spill: ; CHECK-LABEL: broadcast_sd_spill:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $24, %rsp # sched: [1:0.25] ; CHECK-NEXT: subq $24, %rsp # sched: [1:0.25]
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [4:0.33] ; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [4:0.33]
; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill sched: [1:1.00] ; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill sched: [1:1.00]
; CHECK-NEXT: # sched: [1:1.00] ; CHECK-NEXT: # sched: [1:1.00]
; CHECK-NEXT: callq func_f64 ; CHECK-NEXT: callq func_f64
; CHECK-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50] ; CHECK-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload sched: [8:0.50]
; CHECK-NEXT: # sched: [8:0.50] ; CHECK-NEXT: # sched: [8:0.50]
; CHECK-NEXT: addq $24, %rsp # sched: [1:0.25] ; CHECK-NEXT: addq $24, %rsp # sched: [1:0.25]
; CHECK-NEXT: retq # sched: [7:1.00] ; CHECK-NEXT: retq # sched: [7:1.00]
%a = fadd double %x, %x %a = fadd double %x, %x
call void @func_f64(double %a) call void @func_f64(double %a)
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
ret <8 x double> %c ret <8 x double> %c
} }

llvm/trunk/test/CodeGen/X86/avx512-select.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%cond = select i1 %cmp, double %c, double %b %cond = select i1 %cmp, double %c, double %b
ret double %cond ret double %cond
} }
define <16 x double> @select04(<16 x double> %a, <16 x double> %b) { define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
; X86-LABEL: select04: ; X86-LABEL: select04:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %ebp, -8 ; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_register %ebp ; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-64, %esp ; X86-NEXT: andl $-64, %esp
; X86-NEXT: subl $64, %esp ; X86-NEXT: subl $64, %esp
; X86-NEXT: vmovaps 8(%ebp), %zmm1 ; X86-NEXT: vmovaps 8(%ebp), %zmm1
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
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llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll

Show First 20 Lines • Show All 401 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
ret <8 x i64>%res ret <8 x i64>%res
} }
declare void @func_f32(float) declare void @func_f32(float)
define <16 x float> @broadcast_ss_spill(float %x) { define <16 x float> @broadcast_ss_spill(float %x) {
; ALL-LABEL: broadcast_ss_spill: ; ALL-LABEL: broadcast_ss_spill:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: subq $24, %rsp ; ALL-NEXT: subq $24, %rsp
; ALL-NEXT: .Lcfi0:
; ALL-NEXT: .cfi_def_cfa_offset 32 ; ALL-NEXT: .cfi_def_cfa_offset 32
; ALL-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; ALL-NEXT: vaddss %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; ALL-NEXT: callq func_f32 ; ALL-NEXT: callq func_f32
; ALL-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload ; ALL-NEXT: vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload
; ALL-NEXT: addq $24, %rsp ; ALL-NEXT: addq $24, %rsp
; ALL-NEXT: retq ; ALL-NEXT: retq
%a = fadd float %x, %x %a = fadd float %x, %x
call void @func_f32(float %a) call void @func_f32(float %a)
%b = insertelement <16 x float> undef, float %a, i32 0 %b = insertelement <16 x float> undef, float %a, i32 0
%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
ret <16 x float> %c ret <16 x float> %c
} }
declare void @func_f64(double) declare void @func_f64(double)
define <8 x double> @broadcast_sd_spill(double %x) { define <8 x double> @broadcast_sd_spill(double %x) {
; ALL-LABEL: broadcast_sd_spill: ; ALL-LABEL: broadcast_sd_spill:
; ALL: # BB#0: ; ALL: # BB#0:
; ALL-NEXT: subq $24, %rsp ; ALL-NEXT: subq $24, %rsp
; ALL-NEXT: .Lcfi1:
; ALL-NEXT: .cfi_def_cfa_offset 32 ; ALL-NEXT: .cfi_def_cfa_offset 32
; ALL-NEXT: vaddsd %xmm0, %xmm0, %xmm0 ; ALL-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; ALL-NEXT: callq func_f64 ; ALL-NEXT: callq func_f64
; ALL-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload ; ALL-NEXT: vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload
; ALL-NEXT: addq $24, %rsp ; ALL-NEXT: addq $24, %rsp
; ALL-NEXT: retq ; ALL-NEXT: retq
%a = fadd double %x, %x %a = fadd double %x, %x
call void @func_f64(double %a) call void @func_f64(double %a)
%b = insertelement <8 x double> undef, double %a, i32 0 %b = insertelement <8 x double> undef, double %a, i32 0
%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
ret <8 x double> %c ret <8 x double> %c
} }

llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=X32 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=X32
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=X64
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512bw-builtins.c ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512bw-builtins.c
define <8 x i64> @test_mm512_mask_set1_epi8(<8 x i64> %__O, i64 %__M, i8 signext %__A) { define <8 x i64> @test_mm512_mask_set1_epi8(<8 x i64> %__O, i64 %__M, i8 signext %__A) {
; X32-LABEL: test_mm512_mask_set1_epi8: ; X32-LABEL: test_mm512_mask_set1_epi8:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %ebx, -8
; X32-NEXT: vmovdqa64 %zmm0, %zmm3 ; X32-NEXT: vmovdqa64 %zmm0, %zmm3
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %eax, %ecx ; X32-NEXT: movl %eax, %ecx
; X32-NEXT: andb $2, %cl ; X32-NEXT: andb $2, %cl
; X32-NEXT: shrb %cl ; X32-NEXT: shrb %cl
; X32-NEXT: kmovd %ecx, %k0 ; X32-NEXT: kmovd %ecx, %k0
; X32-NEXT: vpmovm2b %k0, %zmm1 ; X32-NEXT: vpmovm2b %k0, %zmm1
▲ Show 20 Lines • Show All 713 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%3 = bitcast <64 x i8> %2 to <8 x i64> %3 = bitcast <64 x i8> %2 to <8 x i64>
ret <8 x i64> %3 ret <8 x i64> %3
} }
define <8 x i64> @test_mm512_maskz_set1_epi8(i64 %__M, i8 signext %__A) { define <8 x i64> @test_mm512_maskz_set1_epi8(i64 %__M, i8 signext %__A) {
; X32-LABEL: test_mm512_maskz_set1_epi8: ; X32-LABEL: test_mm512_maskz_set1_epi8:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .Lcfi3:
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %ebx, -8
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %eax, %ecx ; X32-NEXT: movl %eax, %ecx
; X32-NEXT: andb $2, %cl ; X32-NEXT: andb $2, %cl
; X32-NEXT: shrb %cl ; X32-NEXT: shrb %cl
; X32-NEXT: kmovd %ecx, %k0 ; X32-NEXT: kmovd %ecx, %k0
; X32-NEXT: vpmovm2b %k0, %zmm0 ; X32-NEXT: vpmovm2b %k0, %zmm0
; X32-NEXT: vpsllw $8, %xmm0, %xmm0 ; X32-NEXT: vpsllw $8, %xmm0, %xmm0
▲ Show 20 Lines • Show All 1,167 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

Show First 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_pcmpeq_b: ; AVX512F-32-LABEL: test_pcmpeq_b:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi0:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
; AVX512F-32-NEXT: vzeroupper ; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl ; AVX512F-32-NEXT: retl
%res = call i64 @llvm.x86.avx512.mask.pcmpeq.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1) %res = call i64 @llvm.x86.avx512.mask.pcmpeq.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
ret i64 %res ret i64 %res
} }
define i64 @test_mask_pcmpeq_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) { define i64 @test_mask_pcmpeq_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) {
; AVX512BW-LABEL: test_mask_pcmpeq_b: ; AVX512BW-LABEL: test_mask_pcmpeq_b:
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: kmovq %rdi, %k1 ; AVX512BW-NEXT: kmovq %rdi, %k1
; AVX512BW-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 {%k1} ; AVX512BW-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_mask_pcmpeq_b: ; AVX512F-32-LABEL: test_mask_pcmpeq_b:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi1:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 {%k1} ; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
; AVX512F-32-NEXT: vzeroupper ; AVX512F-32-NEXT: vzeroupper
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_pcmpgt_b: ; AVX512F-32-LABEL: test_pcmpgt_b:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi2:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
; AVX512F-32-NEXT: vzeroupper ; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl ; AVX512F-32-NEXT: retl
%res = call i64 @llvm.x86.avx512.mask.pcmpgt.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1) %res = call i64 @llvm.x86.avx512.mask.pcmpgt.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
ret i64 %res ret i64 %res
} }
define i64 @test_mask_pcmpgt_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) { define i64 @test_mask_pcmpgt_b(<64 x i8> %a, <64 x i8> %b, i64 %mask) {
; AVX512BW-LABEL: test_mask_pcmpgt_b: ; AVX512BW-LABEL: test_mask_pcmpgt_b:
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: kmovq %rdi, %k1 ; AVX512BW-NEXT: kmovq %rdi, %k1
; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 {%k1} ; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_mask_pcmpgt_b: ; AVX512F-32-LABEL: test_mask_pcmpgt_b:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi3:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 {%k1} ; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
; AVX512F-32-NEXT: vzeroupper ; AVX512F-32-NEXT: vzeroupper
▲ Show 20 Lines • Show All 1,193 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_cmp_b_512: ; AVX512F-32-LABEL: test_cmp_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi4:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 64 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 64
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: vpcmpgtb %zmm0, %zmm1, %k0 ; AVX512F-32-NEXT: vpcmpgtb %zmm0, %zmm1, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax ; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: addq %rdi, %rax ; AVX512BW-NEXT: addq %rdi, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_mask_cmp_b_512: ; AVX512F-32-LABEL: test_mask_cmp_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: pushl %ebx ; AVX512F-32-NEXT: pushl %ebx
; AVX512F-32-NEXT: .Lcfi5:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 8 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 8
; AVX512F-32-NEXT: pushl %esi ; AVX512F-32-NEXT: pushl %esi
; AVX512F-32-NEXT: .Lcfi6:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 12 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 12
; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi7:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: .Lcfi8:
; AVX512F-32-NEXT: .cfi_offset %esi, -12 ; AVX512F-32-NEXT: .cfi_offset %esi, -12
; AVX512F-32-NEXT: .Lcfi9:
; AVX512F-32-NEXT: .cfi_offset %ebx, -8 ; AVX512F-32-NEXT: .cfi_offset %ebx, -8
; AVX512F-32-NEXT: vmovdqa64 %zmm1, %zmm6 ; AVX512F-32-NEXT: vmovdqa64 %zmm1, %zmm6
; AVX512F-32-NEXT: vmovdqa64 %zmm0, %zmm5 ; AVX512F-32-NEXT: vmovdqa64 %zmm0, %zmm5
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: movl %ecx, %eax ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: movl %ecx, %ebx ; AVX512F-32-NEXT: movl %ecx, %ebx
▲ Show 20 Lines • Show All 781 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_ucmp_b_512: ; AVX512F-32-LABEL: test_ucmp_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi10:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 64 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 64
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: vpcmpltub %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vpcmpltub %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax ; AVX512F-32-NEXT: addl {{[0-9]+}}(%esp), %eax
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: addq %rdi, %rax ; AVX512BW-NEXT: addq %rdi, %rax
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_mask_x86_avx512_ucmp_b_512: ; AVX512F-32-LABEL: test_mask_x86_avx512_ucmp_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: pushl %ebx ; AVX512F-32-NEXT: pushl %ebx
; AVX512F-32-NEXT: .Lcfi11:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 8 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 8
; AVX512F-32-NEXT: pushl %esi ; AVX512F-32-NEXT: pushl %esi
; AVX512F-32-NEXT: .Lcfi12:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 12 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 12
; AVX512F-32-NEXT: subl $60, %esp ; AVX512F-32-NEXT: subl $60, %esp
; AVX512F-32-NEXT: .Lcfi13:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: .Lcfi14:
; AVX512F-32-NEXT: .cfi_offset %esi, -12 ; AVX512F-32-NEXT: .cfi_offset %esi, -12
; AVX512F-32-NEXT: .Lcfi15:
; AVX512F-32-NEXT: .cfi_offset %ebx, -8 ; AVX512F-32-NEXT: .cfi_offset %ebx, -8
; AVX512F-32-NEXT: vmovdqa64 %zmm1, %zmm6 ; AVX512F-32-NEXT: vmovdqa64 %zmm1, %zmm6
; AVX512F-32-NEXT: vmovdqa64 %zmm0, %zmm5 ; AVX512F-32-NEXT: vmovdqa64 %zmm0, %zmm5
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; AVX512F-32-NEXT: movl %ecx, %eax ; AVX512F-32-NEXT: movl %ecx, %eax
; AVX512F-32-NEXT: shrb $5, %al ; AVX512F-32-NEXT: shrb $5, %al
; AVX512F-32-NEXT: andb $1, %al ; AVX512F-32-NEXT: andb $1, %al
; AVX512F-32-NEXT: movl %ecx, %ebx ; AVX512F-32-NEXT: movl %ecx, %ebx
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll

Show First 20 Lines • Show All 1,485 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: kmovq %rsi, %k1 ; AVX512BW-NEXT: kmovq %rsi, %k1
; AVX512BW-NEXT: kunpckdq %k1, %k0, %k0 ; AVX512BW-NEXT: kunpckdq %k1, %k0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_qd: ; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_qd:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi0:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k0 ; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
Show All 9 Lines
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_int_x86_avx512_cvtb2mask_512: ; AVX512F-32-LABEL: test_int_x86_avx512_cvtb2mask_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp ; AVX512F-32-NEXT: subl $12, %esp
; AVX512F-32-NEXT: .Lcfi1:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0 ; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: movl (%esp), %eax ; AVX512F-32-NEXT: movl (%esp), %eax
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %edx
; AVX512F-32-NEXT: addl $12, %esp ; AVX512F-32-NEXT: addl $12, %esp
; AVX512F-32-NEXT: retl ; AVX512F-32-NEXT: retl
%res = call i64 @llvm.x86.avx512.cvtb2mask.512(<64 x i8> %x0) %res = call i64 @llvm.x86.avx512.cvtb2mask.512(<64 x i8> %x0)
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vptestmb %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vptestmb %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_int_x86_avx512_ptestm_b_512: ; AVX512F-32-LABEL: test_int_x86_avx512_ptestm_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $20, %esp ; AVX512F-32-NEXT: subl $20, %esp
; AVX512F-32-NEXT: .Lcfi2:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 24 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 24
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k1 ; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k1
; AVX512F-32-NEXT: vptestmb %zmm1, %zmm0, %k0 {%k1} ; AVX512F-32-NEXT: vptestmb %zmm1, %zmm0, %k0 {%k1}
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: vptestmb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vptestmb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: vptestnmb %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vptestnmb %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kmovq %k0, %rax ; AVX512BW-NEXT: kmovq %k0, %rax
; AVX512BW-NEXT: addq %rcx, %rax ; AVX512BW-NEXT: addq %rcx, %rax
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512F-32-LABEL: test_int_x86_avx512_ptestnm_b_512: ; AVX512F-32-LABEL: test_int_x86_avx512_ptestnm_b_512:
; AVX512F-32: # BB#0: ; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $20, %esp ; AVX512F-32-NEXT: subl $20, %esp
; AVX512F-32-NEXT: .Lcfi3:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 24 ; AVX512F-32-NEXT: .cfi_def_cfa_offset 24
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1 ; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k1 ; AVX512F-32-NEXT: kunpckdq %k0, %k1, %k1
; AVX512F-32-NEXT: vptestnmb %zmm1, %zmm0, %k0 {%k1} ; AVX512F-32-NEXT: vptestnmb %zmm1, %zmm0, %k0 {%k1}
; AVX512F-32-NEXT: kmovq %k0, (%esp) ; AVX512F-32-NEXT: kmovq %k0, (%esp)
; AVX512F-32-NEXT: vptestnmb %zmm1, %zmm0, %k0 ; AVX512F-32-NEXT: vptestnmb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp) ; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
▲ Show 20 Lines • Show All 350 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res1 = bitcast <4 x i32> %res0 to <2 x i64> %res1 = bitcast <4 x i32> %res0 to <2 x i64>
ret <2 x i64> %res1 ret <2 x i64> %res1
} }
define <2 x i64> @test_mm_mask_broadcastd_epi32(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) { define <2 x i64> @test_mm_mask_broadcastd_epi32(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm_mask_broadcastd_epi32: ; X32-LABEL: test_mm_mask_broadcastd_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastd %xmm1, %xmm0 {%k1} ; X32-NEXT: vpbroadcastd %xmm1, %xmm0 {%k1}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 16 Lines; X64-NEXT: retq
%res2 = bitcast <4 x i32> %res1 to <2 x i64> %res2 = bitcast <4 x i32> %res1 to <2 x i64>
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
define <2 x i64> @test_mm_maskz_broadcastd_epi32(i8 %a0, <2 x i64> %a1) { define <2 x i64> @test_mm_maskz_broadcastd_epi32(i8 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm_maskz_broadcastd_epi32: ; X32-LABEL: test_mm_maskz_broadcastd_epi32:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastd %xmm0, %xmm0 {%k1} {z} ; X32-NEXT: vpbroadcastd %xmm0, %xmm0 {%k1} {z}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer %res = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_mm_mask_broadcastq_epi64(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) { define <2 x i64> @test_mm_mask_broadcastq_epi64(<2 x i64> %a0, i8 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm_mask_broadcastq_epi64: ; X32-LABEL: test_mm_mask_broadcastq_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastq %xmm1, %xmm0 {%k1} ; X32-NEXT: vpbroadcastq %xmm1, %xmm0 {%k1}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <2 x i1> %arg1, <2 x i64> %res0, <2 x i64> %a0 %res1 = select <2 x i1> %arg1, <2 x i64> %res0, <2 x i64> %a0
ret <2 x i64> %res1 ret <2 x i64> %res1
} }
define <2 x i64> @test_mm_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) { define <2 x i64> @test_mm_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm_maskz_broadcastq_epi64: ; X32-LABEL: test_mm_maskz_broadcastq_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi3:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastq %xmm0, %xmm0 {%k1} {z} ; X32-NEXT: vpbroadcastq %xmm0, %xmm0 {%k1} {z}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> zeroinitializer %res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> zeroinitializer
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_mm256_mask_broadcastq_epi64(<4 x i64> %a0, i8 %a1, <2 x i64> %a2) { define <4 x i64> @test_mm256_mask_broadcastq_epi64(<4 x i64> %a0, i8 %a1, <2 x i64> %a2) {
; X32-LABEL: test_mm256_mask_broadcastq_epi64: ; X32-LABEL: test_mm256_mask_broadcastq_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi4:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastq %xmm1, %ymm0 {%k1} ; X32-NEXT: vpbroadcastq %xmm1, %ymm0 {%k1}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0 %res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0
ret <4 x i64> %res1 ret <4 x i64> %res1
} }
define <4 x i64> @test_mm256_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) { define <4 x i64> @test_mm256_maskz_broadcastq_epi64(i8 %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm256_maskz_broadcastq_epi64: ; X32-LABEL: test_mm256_maskz_broadcastq_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi5:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpbroadcastq %xmm0, %ymm0 {%k1} {z} ; X32-NEXT: vpbroadcastq %xmm0, %ymm0 {%k1} {z}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer %res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @test_mm_mask_broadcastsd_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) { define <2 x double> @test_mm_mask_broadcastsd_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) {
; X32-LABEL: test_mm_mask_broadcastsd_pd: ; X32-LABEL: test_mm_mask_broadcastsd_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi6:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0 %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
ret <2 x double> %res1 ret <2 x double> %res1
} }
define <2 x double> @test_mm_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) { define <2 x double> @test_mm_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) {
; X32-LABEL: test_mm_maskz_broadcastsd_pd: ; X32-LABEL: test_mm_maskz_broadcastsd_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi7:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> undef, <4 x i32> zeroinitializer %res = shufflevector <2 x double> %a0, <2 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %res ret <4 x double> %res
} }
define <4 x double> @test_mm256_mask_broadcastsd_pd(<4 x double> %a0, i8 %a1, <2 x double> %a2) { define <4 x double> @test_mm256_mask_broadcastsd_pd(<4 x double> %a0, i8 %a1, <2 x double> %a2) {
; X32-LABEL: test_mm256_mask_broadcastsd_pd: ; X32-LABEL: test_mm256_mask_broadcastsd_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi8:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastsd %xmm1, %ymm0 {%k1} ; X32-NEXT: vbroadcastsd %xmm1, %ymm0 {%k1}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0 %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
ret <4 x double> %res1 ret <4 x double> %res1
} }
define <4 x double> @test_mm256_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) { define <4 x double> @test_mm256_maskz_broadcastsd_pd(i8 %a0, <2 x double> %a1) {
; X32-LABEL: test_mm256_maskz_broadcastsd_pd: ; X32-LABEL: test_mm256_maskz_broadcastsd_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi9:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastsd %xmm0, %ymm0 {%k1} {z} ; X32-NEXT: vbroadcastsd %xmm0, %ymm0 {%k1} {z}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> zeroinitializer %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %res ret <4 x float> %res
} }
define <4 x float> @test_mm_mask_broadcastss_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) { define <4 x float> @test_mm_mask_broadcastss_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
; X32-LABEL: test_mm_mask_broadcastss_ps: ; X32-LABEL: test_mm_mask_broadcastss_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi10:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastss %xmm1, %xmm0 {%k1} ; X32-NEXT: vbroadcastss %xmm1, %xmm0 {%k1}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0 %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
ret <4 x float> %res1 ret <4 x float> %res1
} }
define <4 x float> @test_mm_maskz_broadcastss_ps(i8 %a0, <4 x float> %a1) { define <4 x float> @test_mm_maskz_broadcastss_ps(i8 %a0, <4 x float> %a1) {
; X32-LABEL: test_mm_maskz_broadcastss_ps: ; X32-LABEL: test_mm_maskz_broadcastss_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi11:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vbroadcastss %xmm0, %xmm0 {%k1} {z} ; X32-NEXT: vbroadcastss %xmm0, %xmm0 {%k1} {z}
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer %res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @test_mm_mask_movddup_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) { define <2 x double> @test_mm_mask_movddup_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2) {
; X32-LABEL: test_mm_mask_movddup_pd: ; X32-LABEL: test_mm_mask_movddup_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi12:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0 %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
ret <2 x double> %res1 ret <2 x double> %res1
} }
define <2 x double> @test_mm_maskz_movddup_pd(i8 %a0, <2 x double> %a1) { define <2 x double> @test_mm_maskz_movddup_pd(i8 %a0, <2 x double> %a1) {
; X32-LABEL: test_mm_maskz_movddup_pd: ; X32-LABEL: test_mm_maskz_movddup_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi13:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0] ; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x double> %res ret <4 x double> %res
} }
define <4 x double> @test_mm256_mask_movddup_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) { define <4 x double> @test_mm256_mask_movddup_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) {
; X32-LABEL: test_mm256_mask_movddup_pd: ; X32-LABEL: test_mm256_mask_movddup_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi14:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2] ; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0 %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
ret <4 x double> %res1 ret <4 x double> %res1
} }
define <4 x double> @test_mm256_maskz_movddup_pd(i8 %a0, <4 x double> %a1) { define <4 x double> @test_mm256_maskz_movddup_pd(i8 %a0, <4 x double> %a1) {
; X32-LABEL: test_mm256_maskz_movddup_pd: ; X32-LABEL: test_mm256_maskz_movddup_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi15:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2] ; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
ret <4 x float> %res ret <4 x float> %res
} }
define <4 x float> @test_mm_mask_movehdup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) { define <4 x float> @test_mm_mask_movehdup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
; X32-LABEL: test_mm_mask_movehdup_ps: ; X32-LABEL: test_mm_mask_movehdup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi16:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3] ; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0 %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
ret <4 x float> %res1 ret <4 x float> %res1
} }
define <4 x float> @test_mm_maskz_movehdup_ps(i8 %a0, <4 x float> %a1) { define <4 x float> @test_mm_maskz_movehdup_ps(i8 %a0, <4 x float> %a1) {
; X32-LABEL: test_mm_maskz_movehdup_ps: ; X32-LABEL: test_mm_maskz_movehdup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi17:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3] ; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x float> %res ret <4 x float> %res
} }
define <4 x float> @test_mm_mask_moveldup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) { define <4 x float> @test_mm_mask_moveldup_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2) {
; X32-LABEL: test_mm_mask_moveldup_ps: ; X32-LABEL: test_mm_mask_moveldup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi18:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2] ; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0 %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
ret <4 x float> %res1 ret <4 x float> %res1
} }
define <4 x float> @test_mm_maskz_moveldup_ps(i8 %a0, <4 x float> %a1) { define <4 x float> @test_mm_maskz_moveldup_ps(i8 %a0, <4 x float> %a1) {
; X32-LABEL: test_mm_maskz_moveldup_ps: ; X32-LABEL: test_mm_maskz_moveldup_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi19:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2] ; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0> %res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0>
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_mm256_mask_permutex_epi64(<4 x i64> %a0, i8 %a1, <4 x i64> %a2) { define <4 x i64> @test_mm256_mask_permutex_epi64(<4 x i64> %a0, i8 %a1, <4 x i64> %a2) {
; X32-LABEL: test_mm256_mask_permutex_epi64: ; X32-LABEL: test_mm256_mask_permutex_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi20:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermq {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0] ; X32-NEXT: vpermq {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0 %res1 = select <4 x i1> %arg1, <4 x i64> %res0, <4 x i64> %a0
ret <4 x i64> %res1 ret <4 x i64> %res1
} }
define <4 x i64> @test_mm256_maskz_permutex_epi64(i8 %a0, <4 x i64> %a1) { define <4 x i64> @test_mm256_maskz_permutex_epi64(i8 %a0, <4 x i64> %a1) {
; X32-LABEL: test_mm256_maskz_permutex_epi64: ; X32-LABEL: test_mm256_maskz_permutex_epi64:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi21:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0] ; X32-NEXT: vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0> %res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 3, i32 0, i32 0, i32 0>
ret <4 x double> %res ret <4 x double> %res
} }
define <4 x double> @test_mm256_mask_permutex_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) { define <4 x double> @test_mm256_mask_permutex_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2) {
; X32-LABEL: test_mm256_mask_permutex_pd: ; X32-LABEL: test_mm256_mask_permutex_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi22:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermpd {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0] ; X32-NEXT: vpermpd {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0 %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
ret <4 x double> %res1 ret <4 x double> %res1
} }
define <4 x double> @test_mm256_maskz_permutex_pd(i8 %a0, <4 x double> %a1) { define <4 x double> @test_mm256_maskz_permutex_pd(i8 %a0, <4 x double> %a1) {
; X32-LABEL: test_mm256_maskz_permutex_pd: ; X32-LABEL: test_mm256_maskz_permutex_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi23:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vpermpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0] ; X32-NEXT: vpermpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 3> %res = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 1, i32 3>
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @test_mm_mask_shuffle_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2, <2 x double> %a3) { define <2 x double> @test_mm_mask_shuffle_pd(<2 x double> %a0, i8 %a1, <2 x double> %a2, <2 x double> %a3) {
; X32-LABEL: test_mm_mask_shuffle_pd: ; X32-LABEL: test_mm_mask_shuffle_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi24:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpckhpd {{.*#+}} xmm0 {%k1} = xmm1[1],xmm2[1] ; X32-NEXT: vunpckhpd {{.*#+}} xmm0 {%k1} = xmm1[1],xmm2[1]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0 %res1 = select <2 x i1> %arg1, <2 x double> %res0, <2 x double> %a0
ret <2 x double> %res1 ret <2 x double> %res1
} }
define <2 x double> @test_mm_maskz_shuffle_pd(i8 %a0, <2 x double> %a1, <2 x double> %a2) { define <2 x double> @test_mm_maskz_shuffle_pd(i8 %a0, <2 x double> %a1, <2 x double> %a2) {
; X32-LABEL: test_mm_maskz_shuffle_pd: ; X32-LABEL: test_mm_maskz_shuffle_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi25:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al ; X32-NEXT: andb $3, %al
; X32-NEXT: movb %al, {{[0-9]+}}(%esp) ; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vunpckhpd {{.*#+}} xmm0 {%k1} {z} = xmm0[1],xmm1[1] ; X32-NEXT: vunpckhpd {{.*#+}} xmm0 {%k1} {z} = xmm0[1],xmm1[1]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 1, i32 5, i32 2, i32 6> %res = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 1, i32 5, i32 2, i32 6>
ret <4 x double> %res ret <4 x double> %res
} }
define <4 x double> @test_mm256_mask_shuffle_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2, <4 x double> %a3) { define <4 x double> @test_mm256_mask_shuffle_pd(<4 x double> %a0, i8 %a1, <4 x double> %a2, <4 x double> %a3) {
; X32-LABEL: test_mm256_mask_shuffle_pd: ; X32-LABEL: test_mm256_mask_shuffle_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi26:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vshufpd {{.*#+}} ymm0 {%k1} = ymm1[1],ymm2[1],ymm1[2],ymm2[2] ; X32-NEXT: vshufpd {{.*#+}} ymm0 {%k1} = ymm1[1],ymm2[1],ymm1[2],ymm2[2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0 %res1 = select <4 x i1> %arg1, <4 x double> %res0, <4 x double> %a0
ret <4 x double> %res1 ret <4 x double> %res1
} }
define <4 x double> @test_mm256_maskz_shuffle_pd(i8 %a0, <4 x double> %a1, <4 x double> %a2) { define <4 x double> @test_mm256_maskz_shuffle_pd(i8 %a0, <4 x double> %a1, <4 x double> %a2) {
; X32-LABEL: test_mm256_maskz_shuffle_pd: ; X32-LABEL: test_mm256_maskz_shuffle_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi27:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vshufpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1],ymm1[1],ymm0[2],ymm1[2] ; X32-NEXT: vshufpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1],ymm1[1],ymm0[2],ymm1[2]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 27 Lines; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 4> %res = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 4>
ret <4 x float> %res ret <4 x float> %res
} }
define <4 x float> @test_mm_mask_shuffle_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2, <4 x float> %a3) { define <4 x float> @test_mm_mask_shuffle_ps(<4 x float> %a0, i8 %a1, <4 x float> %a2, <4 x float> %a3) {
; X32-LABEL: test_mm_mask_shuffle_ps: ; X32-LABEL: test_mm_mask_shuffle_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi28:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vshufps {{.*#+}} xmm0 {%k1} = xmm1[0,1],xmm2[0,0] ; X32-NEXT: vshufps {{.*#+}} xmm0 {%k1} = xmm1[0,1],xmm2[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
Show All 13 Lines; X64-NEXT: retq
%res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0 %res1 = select <4 x i1> %arg1, <4 x float> %res0, <4 x float> %a0
ret <4 x float> %res1 ret <4 x float> %res1
} }
define <4 x float> @test_mm_maskz_shuffle_ps(i8 %a0, <4 x float> %a1, <4 x float> %a2) { define <4 x float> @test_mm_maskz_shuffle_ps(i8 %a0, <4 x float> %a1, <4 x float> %a2) {
; X32-LABEL: test_mm_maskz_shuffle_ps: ; X32-LABEL: test_mm_maskz_shuffle_ps:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .Lcfi29:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al ; X32-NEXT: andb $15, %al
; X32-NEXT: movb %al, (%esp) ; X32-NEXT: movb %al, (%esp)
; X32-NEXT: movzbl (%esp), %eax ; X32-NEXT: movzbl (%esp), %eax
; X32-NEXT: kmovw %eax, %k1 ; X32-NEXT: kmovw %eax, %k1
; X32-NEXT: vshufps {{.*#+}} xmm0 {%k1} {z} = xmm0[0,1],xmm1[0,0] ; X32-NEXT: vshufps {{.*#+}} xmm0 {%k1} {z} = xmm0[0,1],xmm1[0,0]
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll

; NOTE: Assertions have been autogenerated by update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f -mattr=+avx512vl| FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f -mattr=+avx512vl| FileCheck %s
declare void @func_f32(float) declare void @func_f32(float)
define <8 x float> @_256_broadcast_ss_spill(float %x) { define <8 x float> @_256_broadcast_ss_spill(float %x) {
; CHECK-LABEL: _256_broadcast_ss_spill: ; CHECK-LABEL: _256_broadcast_ss_spill:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq func_f32 ; CHECK-NEXT: callq func_f32
; CHECK-NEXT: vbroadcastss (%rsp), %ymm0 # 16-byte Folded Reload ; CHECK-NEXT: vbroadcastss (%rsp), %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%a = fadd float %x, %x %a = fadd float %x, %x
call void @func_f32(float %a) call void @func_f32(float %a)
%b = insertelement <8 x float> undef, float %a, i32 0 %b = insertelement <8 x float> undef, float %a, i32 0
%c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x float> %b, <8 x float> undef, <8 x i32> zeroinitializer
ret <8 x float> %c ret <8 x float> %c
} }
define <4 x float> @_128_broadcast_ss_spill(float %x) { define <4 x float> @_128_broadcast_ss_spill(float %x) {
; CHECK-LABEL: _128_broadcast_ss_spill: ; CHECK-LABEL: _128_broadcast_ss_spill:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq func_f32 ; CHECK-NEXT: callq func_f32
; CHECK-NEXT: vbroadcastss (%rsp), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vbroadcastss (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%a = fadd float %x, %x %a = fadd float %x, %x
call void @func_f32(float %a) call void @func_f32(float %a)
%b = insertelement <4 x float> undef, float %a, i32 0 %b = insertelement <4 x float> undef, float %a, i32 0
%c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %c ret <4 x float> %c
} }
declare void @func_f64(double) declare void @func_f64(double)
define <4 x double> @_256_broadcast_sd_spill(double %x) { define <4 x double> @_256_broadcast_sd_spill(double %x) {
; CHECK-LABEL: _256_broadcast_sd_spill: ; CHECK-LABEL: _256_broadcast_sd_spill:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq func_f64 ; CHECK-NEXT: callq func_f64
; CHECK-NEXT: vbroadcastsd (%rsp), %ymm0 # 16-byte Folded Reload ; CHECK-NEXT: vbroadcastsd (%rsp), %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%a = fadd double %x, %x %a = fadd double %x, %x
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llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=VLX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=VLX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=NoVLX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=NoVLX
define zeroext i32 @test_vpcmpeqb_v16i1_v32i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr { define zeroext i32 @test_vpcmpeqb_v16i1_v32i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask: ; VLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask:
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi0:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi3:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi4:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi5:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi6:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi7:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
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; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi8:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi9:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi10:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi11:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi12:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi13:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi14:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi15:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
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; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi16:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi17:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi18:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi19:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi20:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi21:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi22:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi23:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
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; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi24:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi25:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi26:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi27:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi28:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi29:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi30:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi31:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
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; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi32:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi33:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi34:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi35:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi36:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi37:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi38:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi39:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi40:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi41:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi42:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi43:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi44:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi45:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi46:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi47:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi48:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi49:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi50:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi51:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi52:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi53:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi54:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi55:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi56:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi57:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi58:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi59:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi60:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi61:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi62:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi63:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqb (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqb (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqb %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi64:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi65:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi66:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0 ; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0
Show All 28 Lines
; VLX-NEXT: vpcmpeqb (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqb (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi67:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi68:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi69:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0 ; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0
Show All 30 Lines
; VLX-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi70:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi71:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi72:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm2, %xmm2 ; NoVLX-NEXT: vpmovdb %zmm2, %xmm2
Show All 40 Lines
; VLX-NEXT: vpcmpeqb (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqb (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi73:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi74:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi75:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm1, %xmm1 ; NoVLX-NEXT: vpmovdb %zmm1, %xmm1
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi76:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi77:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi78:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi79:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi80:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi81:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi82:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi83:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi84:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi85:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi86:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi87:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqw (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi88:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi89:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi90:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi91:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi92:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi93:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi94:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi95:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi96:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi97:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi98:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi99:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqw (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqw (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi100:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi101:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi102:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi103:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi104:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi105:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi106:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi107:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi108:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi109:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi110:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi111:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi112:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi113:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi114:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi115:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi116:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi117:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi118:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi119:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi120:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi121:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi122:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi123:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi124:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi125:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi126:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi127:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi128:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi129:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi130:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi131:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi132:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi133:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi134:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi135:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi136:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi137:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi138:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi139:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi140:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi141:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi142:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi143:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi144:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi145:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi146:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi147:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi148:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi149:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi150:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi151:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi152:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi153:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi154:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi155:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi156:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi157:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi158:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi159:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi160:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi161:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi162:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi163:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqw (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqw (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpeqw %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi164:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi165:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi166:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3
; NoVLX-NEXT: vmovq %xmm3, %rax ; NoVLX-NEXT: vmovq %xmm3, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm2 ; NoVLX-NEXT: vmovd %eax, %xmm2
▲ Show 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpeqw (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi167:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi168:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi169:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm1 ; NoVLX-NEXT: vmovd %eax, %xmm1
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqw %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi170:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi171:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi172:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
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; VLX-NEXT: vpcmpeqw (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqw (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi173:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi174:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi175:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; NoVLX-NEXT: vmovq %xmm1, %rax ; NoVLX-NEXT: vmovq %xmm1, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 1,075 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi176:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi177:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi178:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi179:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi180:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi181:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi182:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi183:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi184:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
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; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi185:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi186:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi187:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi188:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi189:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi190:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi191:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi192:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi193:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi194:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi195:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi196:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi197:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi198:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi199:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 30 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi200:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi201:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi202:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi203:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi204:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi205:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi206:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi207:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi208:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi209:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi210:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi211:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi212:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi213:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi214:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi215:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi216:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi217:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi218:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi219:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi220:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi221:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi222:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi223:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi224:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi225:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi226:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi227:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi228:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi229:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi230:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi231:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi232:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi233:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi234:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi235:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi236:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi237:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi238:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi239:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi240:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi241:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi242:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi243:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi244:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi245:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi246:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi247:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi248:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi249:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi250:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi251:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi252:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi253:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi254:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi255:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi256:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi257:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi258:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi259:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi260:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi261:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi262:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi263:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi264:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi265:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi266:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi267:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi268:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi269:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi270:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi271:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi272:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi273:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi274:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi275:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi276:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi277:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi278:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi279:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi280:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi281:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi282:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi283:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi284:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi285:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi286:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi287:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi288:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi289:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi290:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi291:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi292:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi293:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi294:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi295:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi296:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi297:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi298:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi299:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi300:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi301:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi302:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi303:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi304:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi305:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi306:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi307:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi308:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi309:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi310:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi311:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi312:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi313:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi314:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi315:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi316:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi317:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi318:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi319:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi320:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi321:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi322:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi323:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi324:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi325:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi326:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi327:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi328:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi329:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi330:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi331:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi332:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi333:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi334:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi335:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqd (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi336:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi337:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi338:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi339:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi340:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi341:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi342:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi343:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqd (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 893 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi344:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi345:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi346:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi347:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi348:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi349:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi350:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi351:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi352:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
Show All 36 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi353:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi354:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi355:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
Show All 37 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi356:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi357:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi358:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi359:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi360:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi361:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
Show All 39 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi362:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi363:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi364:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi365:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi366:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi367:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 30 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi368:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi369:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi370:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi371:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi372:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi373:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi374:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi375:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi376:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi377:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi378:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi379:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 888 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi380:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi381:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi382:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi383:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi384:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi385:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi386:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi387:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi388:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi389:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi390:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi391:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi392:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi393:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi394:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 28 Lines
; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi395:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi396:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi397:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi398:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi399:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi400:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 30 Lines
; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi401:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi402:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi403:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi404:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi405:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi406:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi407:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi408:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi409:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi410:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi411:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi412:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 34 Lines
; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi413:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi414:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi415:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi416:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi417:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi418:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi419:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi420:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi421:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi422:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi423:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi424:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi425:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi426:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi427:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi428:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi429:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi430:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi431:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi432:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi433:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi434:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi435:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi436:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi437:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi438:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi439:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi440:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi441:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi442:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi443:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi444:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi445:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi446:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi447:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi448:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpeqq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi449:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi450:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi451:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi452:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi453:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi454:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi455:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi456:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi457:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi458:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi459:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi460:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi461:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi462:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi463:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi464:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi465:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi466:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi467:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi468:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi469:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi470:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi471:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi472:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi473:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi474:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi475:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi476:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi477:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi478:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi479:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi480:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi481:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi482:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi483:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi484:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi485:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi486:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi487:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi488:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi489:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi490:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi491:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi492:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi493:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi494:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi495:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi496:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi497:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi498:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi499:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi500:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi501:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi502:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi503:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi504:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi505:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi506:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi507:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi508:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi509:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi510:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi511:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi512:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi513:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi514:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi515:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtb (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtb %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtb %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi516:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi517:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi518:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0 ; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0
Show All 28 Lines
; VLX-NEXT: vpcmpgtb (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtb (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi519:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi520:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi521:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0 ; NoVLX-NEXT: vptestmd %zmm1, %zmm1, %k0
Show All 30 Lines
; VLX-NEXT: vpcmpgtb %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi522:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi523:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi524:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm2, %xmm2 ; NoVLX-NEXT: vpmovdb %zmm2, %xmm2
Show All 40 Lines
; VLX-NEXT: vpcmpgtb (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtb (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi525:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi526:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi527:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm1, %xmm1 ; NoVLX-NEXT: vpmovdb %zmm1, %xmm1
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi528:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi529:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi530:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi531:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi532:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi533:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi534:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi535:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi536:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi537:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi538:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi539:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi540:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi541:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi542:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi543:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi544:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi545:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi546:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi547:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi548:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi549:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi550:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi551:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtw (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi552:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi553:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi554:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi555:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi556:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi557:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi558:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi559:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi560:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi561:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi562:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi563:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi564:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi565:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi566:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi567:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi568:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi569:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi570:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi571:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi572:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi573:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi574:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi575:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi576:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi577:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi578:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi579:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi580:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi581:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi582:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi583:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi584:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi585:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi586:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi587:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi588:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi589:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi590:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi591:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi592:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi593:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi594:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi595:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi596:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi597:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi598:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi599:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi600:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi601:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi602:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi603:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi604:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi605:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi606:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi607:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi608:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi609:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi610:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi611:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi612:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi613:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi614:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi615:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtw (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpgtw %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi616:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi617:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi618:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3
; NoVLX-NEXT: vmovq %xmm3, %rax ; NoVLX-NEXT: vmovq %xmm3, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm2 ; NoVLX-NEXT: vmovd %eax, %xmm2
▲ Show 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpgtw (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi619:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi620:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi621:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm1 ; NoVLX-NEXT: vmovd %eax, %xmm1
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi622:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi623:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi624:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtw (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtw (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi625:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi626:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi627:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; NoVLX-NEXT: vmovq %xmm1, %rax ; NoVLX-NEXT: vmovq %xmm1, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 1,075 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi628:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi629:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi630:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi631:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi632:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi633:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi634:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi635:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi636:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi637:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi638:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi639:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi640:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi641:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi642:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi643:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi644:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi645:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi646:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi647:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi648:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi649:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi650:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi651:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 30 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi652:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi653:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi654:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi655:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi656:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi657:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi658:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi659:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi660:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi661:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi662:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi663:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi664:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi665:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi666:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi667:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi668:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi669:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi670:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi671:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi672:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi673:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi674:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi675:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi676:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi677:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi678:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi679:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi680:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi681:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi682:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi683:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi684:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi685:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi686:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi687:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi688:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi689:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi690:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi691:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi692:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi693:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi694:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi695:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi696:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi697:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi698:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi699:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi700:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi701:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi702:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi703:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi704:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi705:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi706:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi707:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi708:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi709:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi710:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi711:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi712:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi713:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi714:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi715:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi716:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi717:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi718:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi719:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi720:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi721:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi722:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi723:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi724:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi725:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi726:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi727:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi728:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi729:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi730:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi731:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi732:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi733:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi734:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi735:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi736:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi737:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi738:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi739:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi740:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi741:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi742:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi743:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi744:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi745:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi746:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi747:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi748:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi749:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi750:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi751:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi752:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi753:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi754:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi755:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi756:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi757:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi758:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi759:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi760:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi761:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi762:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi763:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi764:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi765:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi766:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi767:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi768:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi769:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi770:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi771:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi772:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi773:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi774:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi775:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi776:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi777:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi778:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi779:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi780:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi781:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi782:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi783:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi784:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi785:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi786:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi787:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi788:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi789:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi790:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi791:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi792:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi793:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi794:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi795:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtd (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 893 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi796:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi797:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi798:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi799:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi800:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi801:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi802:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi803:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi804:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
Show All 36 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi805:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi806:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi807:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
Show All 37 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi808:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi809:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi810:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi811:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi812:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi813:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
Show All 39 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi814:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi815:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi816:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi817:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi818:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi819:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 30 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi820:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi821:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi822:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi823:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi824:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi825:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq (%rsi), %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi826:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi827:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi828:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi829:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi830:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi831:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 888 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi832:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi833:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi834:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi835:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi836:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi837:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 26 Lines
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi838:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi839:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi840:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi841:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi842:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi843:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi844:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi845:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi846:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 28 Lines
; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi847:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi848:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi849:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi850:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi851:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi852:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 30 Lines
; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi853:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi854:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi855:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 32 Lines
; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi856:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi857:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi858:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi859:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi860:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi861:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rsi), %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq (%rsi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi862:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi863:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi864:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 34 Lines
; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi865:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi866:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi867:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi868:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi869:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi870:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi871:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi872:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi873:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi874:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi875:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi876:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi877:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi878:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi879:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi880:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi881:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi882:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi883:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi884:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi885:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi886:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi887:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi888:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi889:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi890:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi891:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi892:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi893:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi894:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi895:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi896:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi897:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi898:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi899:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi900:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgtq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi901:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi902:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi903:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi904:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi905:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi906:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi907:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi908:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi909:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi910:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi911:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi912:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi913:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi914:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi915:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi916:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi917:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi918:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi919:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi920:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi921:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi922:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi923:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi924:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi925:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi926:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi927:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi928:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi929:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi930:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi931:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi932:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi933:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi934:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi935:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi936:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi937:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi938:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi939:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi940:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi941:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi942:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi943:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltb (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltb (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi944:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi945:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi946:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi947:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi948:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi949:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi950:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi951:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleb %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi952:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi953:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi954:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi955:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi956:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi957:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi958:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi959:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltb (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltb (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi960:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi961:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi962:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi963:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi964:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi965:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi966:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi967:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleb %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpleb %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgeb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi968:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi969:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi970:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 30 Lines
; VLX-NEXT: vpcmpnltb (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltb (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi971:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi972:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi973:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 33 Lines
; VLX-NEXT: vpcmpleb %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpleb %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi974:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi975:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi976:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm2, %xmm2 ; NoVLX-NEXT: vpmovdb %zmm2, %xmm2
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltb (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltb (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi977:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi978:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi979:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm1, %xmm1 ; NoVLX-NEXT: vpmovdb %zmm1, %xmm1
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; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi980:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi981:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi982:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi983:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi984:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi985:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi986:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi987:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi988:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi989:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi990:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi991:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi992:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi993:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi994:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi995:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi996:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi997:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi998:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi999:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1000:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1001:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1002:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1003:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgew_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1004:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1005:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1006:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1007:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1008:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1009:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1010:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1011:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgew_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1012:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1013:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1014:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1015:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1016:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1017:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1018:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1019:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1020:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1021:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1022:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1023:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1024:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1025:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1026:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1027:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1028:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1029:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1030:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1031:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1032:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1033:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1034:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1035:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgew_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1036:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1037:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1038:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1039:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1040:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1041:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1042:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1043:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgew_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1044:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1045:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1046:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1047:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1048:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1049:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1050:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1051:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmplew %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1052:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1053:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1054:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1055:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1056:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1057:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1058:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1059:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1}
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgew_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1060:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1061:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1062:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1063:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1064:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1065:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1066:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1067:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmplew %zmm0, %zmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgew_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1068:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1069:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1070:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3
; NoVLX-NEXT: vmovq %xmm3, %rax ; NoVLX-NEXT: vmovq %xmm3, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm2 ; NoVLX-NEXT: vmovd %eax, %xmm2
▲ Show 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpnltw (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgew_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgew_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1071:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1072:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1073:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm1 ; NoVLX-NEXT: vmovd %eax, %xmm1
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmplew %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmplew %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgew_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1074:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1075:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1076:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltw (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltw (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgew_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgew_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1077:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1078:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1079:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; NoVLX-NEXT: vmovq %xmm1, %rax ; NoVLX-NEXT: vmovq %xmm1, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 1,100 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1080:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1081:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1082:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 24 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1083:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1084:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1085:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 27 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1086:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1087:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1088:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1089:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1090:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1091:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; VLX-NEXT: vpbroadcastd (%rdi), %xmm1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1092:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1093:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1094:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 29 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1095:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1096:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1097:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1098:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1099:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1100:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 30 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1101:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1102:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1103:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 33 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1104:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1105:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1106:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $13, %k0, %k2 ; NoVLX-NEXT: kshiftlw $13, %k0, %k2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1107:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1108:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1109:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; VLX-NEXT: vpbroadcastd (%rdi), %xmm1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1110:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1111:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1112:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 35 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1113:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1114:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1115:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $12, %k0, %k1 ; NoVLX-NEXT: kshiftlw $12, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1116:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1117:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1118:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1119:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1120:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1121:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1122:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1123:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1124:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1125:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1126:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1127:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1128:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1129:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1130:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1131:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1132:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1133:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1134:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1135:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1136:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1137:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1138:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1139:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1140:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1141:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1142:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1143:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1144:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1145:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1146:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1147:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1148:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1149:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1150:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1151:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1152:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1153:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1154:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1155:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1156:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1157:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1158:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1159:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1160:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1161:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1162:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1163:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1164:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1165:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1166:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1167:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1168:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1169:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1170:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1171:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1172:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1173:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1174:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1175:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1176:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1177:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1178:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1179:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1180:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1181:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1182:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1183:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1184:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1185:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1186:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1187:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1188:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1189:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1190:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1191:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpbroadcastd (%rdi), %zmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %zmm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1192:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1193:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1194:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1195:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1196:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1197:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1198:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1199:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpbroadcastd (%rsi), %zmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %zmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1200:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1201:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1202:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1203:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1204:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1205:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1206:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1207:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1208:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1209:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1210:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1211:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1212:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1213:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1214:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1215:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpnltd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1216:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1217:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1218:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1219:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1220:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1221:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1222:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1223:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1224:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1225:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1226:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1227:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1228:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1229:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1230:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1231:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpnltd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsged_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1232:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1233:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1234:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1235:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1236:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1237:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1238:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1239:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpbroadcastd (%rdi), %zmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %zmm1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsged_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1240:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1241:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1242:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1243:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1244:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1245:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1246:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1247:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpbroadcastd (%rsi), %zmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %zmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 924 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1248:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1249:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1250:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 24 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1251:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1252:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1253:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 27 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1254:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1255:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1256:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
Show All 36 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1257:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1258:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1259:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
Show All 39 Lines
; VLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; VLX-NEXT: vpbroadcastq (%rdi), %xmm1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1260:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1261:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1262:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 29 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1263:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1264:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1265:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
Show All 39 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1266:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1267:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1268:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 30 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1269:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1270:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1271:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 33 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1272:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1273:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1274:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1275:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1276:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1277:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; VLX-NEXT: vpbroadcastq (%rdi), %xmm1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1278:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1279:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1280:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; NoVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 35 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1281:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1282:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1283:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 920 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1284:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1285:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1286:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 26 Lines
; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1287:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1288:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1289:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 29 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1290:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1291:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1292:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1293:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1294:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1295:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1296:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1297:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1298:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 31 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1299:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1300:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1301:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1302:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1303:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1304:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 32 Lines
; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1305:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1306:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1307:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 35 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1308:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1309:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1310:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1311:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1312:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1313:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1314:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1315:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1316:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 37 Lines
; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1317:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1318:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1319:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; NoVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1320:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1321:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1322:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1323:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1324:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1325:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1326:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1327:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1328:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1329:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1330:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1331:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1332:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1333:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1334:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %zmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %zmm1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1335:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1336:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1337:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %zmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %zmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1338:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1339:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1340:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1341:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1342:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1343:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1344:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1345:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1346:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1347:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1348:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1349:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1350:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1351:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1352:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %zmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %zmm1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpsgeq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1353:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1354:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1355:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %zmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %zmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1356:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1357:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1358:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1359:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1360:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1361:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1362:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1363:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltub (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltub (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1364:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1365:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1366:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1367:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1368:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1369:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1370:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1371:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1372:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1373:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1374:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1375:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1376:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1377:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1378:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1379:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltub (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1380:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1381:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1382:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1383:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1384:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1385:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1386:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1387:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1388:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1389:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1390:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1391:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1392:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1393:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1394:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1395:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltub (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltub (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1396:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1397:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1398:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1399:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1400:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1401:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1402:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1403:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1404:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1405:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1406:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1407:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1408:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1409:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1410:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1411:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
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; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltub (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultb_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1412:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1413:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1414:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1415:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1416:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1417:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1418:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1419:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxbd %xmm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltub %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltub %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1420:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1421:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1422:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 31 Lines
; VLX-NEXT: vpcmpltub (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltub (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1423:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1424:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1425:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 33 Lines
; VLX-NEXT: vpcmpltub %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultb_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1426:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1427:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1428:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm2, %xmm2 ; NoVLX-NEXT: vpmovdb %zmm2, %xmm2
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltub (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltub (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultb_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultb_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1429:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1430:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1431:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2 ; NoVLX-NEXT: kmovw {{[0-9]+}}(%rsp), %k2
; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovdb %zmm1, %xmm1 ; NoVLX-NEXT: vpmovdb %zmm1, %xmm1
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1432:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1433:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1434:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1435:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1436:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1437:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1438:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1439:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1440:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1441:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1442:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1443:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1444:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1445:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1446:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1447:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1448:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1449:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1450:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1451:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1452:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1453:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1454:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1455:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0 ; NoVLX-NEXT: vpmovsxwq %xmm0, %zmm0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1456:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1457:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1458:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1459:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1460:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1461:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1462:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1463:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltuw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1464:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1465:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1466:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1467:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1468:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1469:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1470:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1471:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1472:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1473:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1474:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1475:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1476:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1477:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1478:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1479:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1480:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1481:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1482:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1483:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1484:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1485:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1486:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1487:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1488:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1489:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1490:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1491:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1492:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1493:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1494:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1495:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltuw (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1496:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1497:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1498:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1499:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1500:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1501:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1502:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1503:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1504:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1505:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1506:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1507:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1508:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1509:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1510:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1511:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm2 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultw_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1512:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1513:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1514:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1515:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1516:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1517:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1518:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1519:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768] ; NoVLX-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768,32768]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0 ; NoVLX-NEXT: vpmovsxwd %ymm0, %zmm0
; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0 ; NoVLX-NEXT: vpslld $31, %zmm0, %zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpltuw %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1520:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1521:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1522:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm3
; NoVLX-NEXT: vmovq %xmm3, %rax ; NoVLX-NEXT: vmovq %xmm3, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm2 ; NoVLX-NEXT: vmovd %eax, %xmm2
▲ Show 20 Lines • Show All 335 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpltuw (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1523:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1524:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1525:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
; NoVLX-NEXT: vmovd %eax, %xmm1 ; NoVLX-NEXT: vmovd %eax, %xmm1
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v32i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultw_v32i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1526:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1527:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1528:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NoVLX-NEXT: vmovq %xmm2, %rax ; NoVLX-NEXT: vmovq %xmm2, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 347 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuw (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuw (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultw_v32i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultw_v32i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1529:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1530:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1531:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NoVLX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; NoVLX-NEXT: vmovq %xmm1, %rax ; NoVLX-NEXT: vmovq %xmm1, %rax
; NoVLX-NEXT: movq %rax, %rcx ; NoVLX-NEXT: movq %rax, %rcx
; NoVLX-NEXT: movq %rax, %rdx ; NoVLX-NEXT: movq %rax, %rdx
▲ Show 20 Lines • Show All 1,116 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1532:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1533:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1534:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 25 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1535:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1536:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1537:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 27 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1538:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1539:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1540:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1541:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1542:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1543:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1544:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1545:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1546:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
Show All 29 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1547:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1548:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1549:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1550:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1551:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1552:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 31 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1553:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1554:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1555:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 33 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1556:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1557:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1558:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1559:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1560:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1561:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1562:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1563:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1564:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %xmm1
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
Show All 35 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1565:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1566:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1567:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %xmm1
; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; NoVLX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1568:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1569:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1570:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1571:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1572:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1573:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1574:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1575:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1576:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1577:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1578:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1579:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1580:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1581:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1582:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1583:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1584:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1585:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1586:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1587:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1588:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1589:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1590:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1591:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1592:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1593:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1594:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1595:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1596:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1597:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1598:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1599:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1600:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1601:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1602:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1603:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1604:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1605:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1606:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1607:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1608:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1609:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1610:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1611:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1612:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1613:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1614:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1615:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1616:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1617:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1618:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1619:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1620:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1621:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1622:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1623:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1624:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1625:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1626:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1627:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1628:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1629:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1630:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1631:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1632:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1633:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1634:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1635:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1636:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1637:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1638:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1639:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1640:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1641:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1642:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1643:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1644:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1645:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1646:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1647:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1648:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1649:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1650:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1651:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1652:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1653:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1654:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1655:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1656:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1657:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1658:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1659:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1660:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1661:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1662:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1663:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1664:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1665:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1666:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1667:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1668:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1669:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1670:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1671:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1672:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1673:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1674:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1675:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1676:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1677:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1678:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1679:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1680:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1681:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1682:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1683:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1684:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1685:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1686:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1687:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1688:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1689:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1690:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1691:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltud (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultd_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1692:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1693:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1694:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1695:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1696:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1697:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1698:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1699:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltud (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 947 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1700:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1701:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1702:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 25 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1703:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1704:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1705:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 27 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1706:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1707:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1708:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
Show All 39 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1709:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1710:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1711:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
Show All 40 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1712:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1713:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1714:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
Show All 29 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1715:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1716:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1717:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1718:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1719:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1720:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 31 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1721:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1722:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1723:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rdi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
Show All 33 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1724:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1725:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1726:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1727:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1728:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1729:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1 ; NoVLX-NEXT: vpxor (%rsi), %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
; NoVLX-NEXT: kmovw %edi, %k0 ; NoVLX-NEXT: kmovw %edi, %k0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1730:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1731:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1732:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
Show All 35 Lines
; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: kmovd %edi, %k1
; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1733:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1734:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1735:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; NoVLX-NEXT: vpxor %xmm2, %xmm0, %xmm0
; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; NoVLX-NEXT: vpxor %xmm2, %xmm1, %xmm1
; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 ; NoVLX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
▲ Show 20 Lines • Show All 927 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1736:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1737:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1738:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 27 Lines
; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1739:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1740:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1741:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 29 Lines
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1742:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1743:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1744:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1745:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1746:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1747:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1748:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1749:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1750:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
Show All 31 Lines
; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1751:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1752:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1753:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1754:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1755:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1756:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 33 Lines
; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1757:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1758:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1759:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rdi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
Show All 35 Lines
; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1760:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1761:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1762:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1763:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1764:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1765:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1 ; NoVLX-NEXT: vpxor (%rsi), %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1766:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1767:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1768:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %ymm1
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
Show All 37 Lines
; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1769:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1770:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1771:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %ymm1
; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; NoVLX-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; NoVLX-NEXT: vpxor %ymm2, %ymm0, %ymm0
; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; NoVLX-NEXT: vpxor %ymm2, %ymm1, %ymm1
; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 ; NoVLX-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1772:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1773:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1774:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1775:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1776:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1777:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1778:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1779:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1780:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1781:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1782:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1783:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1784:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1785:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1786:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1787:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1788:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1789:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1790:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1791:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1792:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1793:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1794:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1795:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1796:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1797:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1798:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1799:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1800:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1801:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1802:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1803:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1804:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vpcmpultq_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1805:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1806:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1807:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 809 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1808:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1809:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1810:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1811:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1812:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1813:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 23 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1814:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1815:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1816:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vbroadcastss (%rdi), %xmm1 ; NoVLX-NEXT: vbroadcastss (%rdi), %xmm1
; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 27 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1817:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1818:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1819:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm2, %ymm2 ; NoVLX-NEXT: vpmovqd %zmm2, %ymm2
Show All 32 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1820:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1821:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1822:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
Show All 33 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1823:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1824:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1825:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
Show All 35 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1826:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1827:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1828:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1829:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1830:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1831:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 29 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1832:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1833:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1834:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vbroadcastss (%rdi), %xmm1 ; NoVLX-NEXT: vbroadcastss (%rdi), %xmm1
; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqps %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 33 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1835:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1836:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1837:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm2, %ymm2 ; NoVLX-NEXT: vpmovqd %zmm2, %ymm2
Show All 38 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1838:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1839:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1840:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
Show All 39 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1841:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1842:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1843:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1844:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1845:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1846:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1847:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1848:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1849:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovaps (%rdi), %ymm1 ; NoVLX-NEXT: vmovaps (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1850:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1851:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1852:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1 ; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1853:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1854:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1855:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1856:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1857:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1858:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovaps (%rsi), %ymm1 ; NoVLX-NEXT: vmovaps (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1859:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1860:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1861:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1 ; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1862:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1863:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1864:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1865:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1866:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1867:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovaps (%rdi), %ymm1 ; NoVLX-NEXT: vmovaps (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1868:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1869:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1870:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1 ; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1871:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1872:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1873:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> ; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1874:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1875:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1876:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vmovaps (%rsi), %ymm1 ; NoVLX-NEXT: vmovaps (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1877:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1878:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1879:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1 ; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1880:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1881:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1882:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1883:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1884:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1885:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1886:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1887:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1888:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1889:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1890:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1891:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1892:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1893:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1894:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1895:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1896:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1897:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1898:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1899:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1900:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1901:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1902:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1903:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1904:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1905:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1906:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1907:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1908:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1909:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1910:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1911:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1912:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1913:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1914:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1915:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1916:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1917:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1918:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1919:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1920:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1921:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1922:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: .Lcfi1923:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1924:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1925:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1926:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1927:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
; NoVLX-NEXT: kmovw %k1, %r8d ; NoVLX-NEXT: kmovw %k1, %r8d
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1928:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1929:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1930:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1931:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1932:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1933:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1934:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1935:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1936:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1937:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1938:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1939:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1940:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1941:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1942:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1943:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0 ; VLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqps_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1944:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1945:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1946:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1947:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1948:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1949:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1950:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1951:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqps (%rdi){1to16}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1952:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1953:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1954:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1955:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1956:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1957:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1958:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1959:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1960:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1961:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1962:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1963:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1964:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1965:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1966:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1967:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1968:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1969:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1970:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: pushq %r15 ; NoVLX-NEXT: pushq %r15
; NoVLX-NEXT: pushq %r14 ; NoVLX-NEXT: pushq %r14
; NoVLX-NEXT: pushq %r13 ; NoVLX-NEXT: pushq %r13
; NoVLX-NEXT: pushq %r12 ; NoVLX-NEXT: pushq %r12
; NoVLX-NEXT: pushq %rbx ; NoVLX-NEXT: pushq %rbx
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: .Lcfi1971:
; NoVLX-NEXT: .cfi_offset %rbx, -56 ; NoVLX-NEXT: .cfi_offset %rbx, -56
; NoVLX-NEXT: .Lcfi1972:
; NoVLX-NEXT: .cfi_offset %r12, -48 ; NoVLX-NEXT: .cfi_offset %r12, -48
; NoVLX-NEXT: .Lcfi1973:
; NoVLX-NEXT: .cfi_offset %r13, -40 ; NoVLX-NEXT: .cfi_offset %r13, -40
; NoVLX-NEXT: .Lcfi1974:
; NoVLX-NEXT: .cfi_offset %r14, -32 ; NoVLX-NEXT: .cfi_offset %r14, -32
; NoVLX-NEXT: .Lcfi1975:
; NoVLX-NEXT: .cfi_offset %r15, -24 ; NoVLX-NEXT: .cfi_offset %r15, -24
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqps (%rsi){1to16}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $14, %k0, %k1 ; NoVLX-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 902 Lines • ▼ Show 20 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1976:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1977:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1978:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 22 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1979:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1980:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1981:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1 ; NoVLX-NEXT: vpslld $31, %zmm1, %zmm1
Show All 23 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1982:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1983:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1984:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 27 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1985:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1986:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1987:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
Show All 31 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1988:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1989:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1990:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vcmpeqpd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd (%rsi), %xmm0, %xmm0
Show All 32 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1991:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1992:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1993:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0]
Show All 34 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1994:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1995:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1996:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 28 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi1997:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi1998:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi1999:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
Show All 29 Lines
; VLX: # BB#0: # %entry ; VLX: # BB#0: # %entry
; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2000:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2001:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2002:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 33 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2003:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2004:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2005:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0
Show All 37 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2006:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2007:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2008:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vcmpeqpd (%rsi), %xmm0, %xmm0 ; NoVLX-NEXT: vcmpeqpd (%rsi), %xmm0, %xmm0
Show All 38 Lines
; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1
; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2009:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2010:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2011:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0]
▲ Show 20 Lines • Show All 811 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2012:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2013:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2014:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 24 Lines
; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2015:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2016:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2017:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1 ; NoVLX-NEXT: vpmovsxbd %xmm1, %zmm1
Show All 25 Lines
; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2018:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2019:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2020:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vbroadcastsd (%rdi), %ymm1 ; NoVLX-NEXT: vbroadcastsd (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; NoVLX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NoVLX-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 29 Lines
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2021:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2022:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2023:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm2, %ymm2 ; NoVLX-NEXT: vpmovqd %zmm2, %ymm2
Show All 34 Lines
; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2024:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2025:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2026:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
Show All 35 Lines
; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2027:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2028:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2029:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
Show All 37 Lines
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2030:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2031:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2032:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 30 Lines
; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2033:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2034:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2035:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 31 Lines
; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2036:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2037:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2038:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vbroadcastsd (%rdi), %ymm1 ; NoVLX-NEXT: vbroadcastsd (%rdi), %ymm1
; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 ; NoVLX-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
; NoVLX-NEXT: vpmovqd %zmm0, %ymm0 ; NoVLX-NEXT: vpmovqd %zmm0, %ymm0
; NoVLX-NEXT: kxorw %k0, %k0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k0
; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k0, {{[0-9]+}}(%rsp)
Show All 35 Lines
; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2039:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2040:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2041:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm2, %zmm2, %zmm2 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm2, %ymm2 ; NoVLX-NEXT: vpmovqd %zmm2, %ymm2
Show All 40 Lines
; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2042:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2043:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2044:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v4i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2045:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2046:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2047:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $96, %rsp ; NoVLX-NEXT: subq $96, %rsp
; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: movb %dil, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; NoVLX-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; NoVLX-NEXT: kmovw %eax, %k1 ; NoVLX-NEXT: kmovw %eax, %k1
; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z} ; NoVLX-NEXT: vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; NoVLX-NEXT: vpmovqd %zmm1, %ymm1 ; NoVLX-NEXT: vpmovqd %zmm1, %ymm1
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2048:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2049:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2050:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2051:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2052:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2053:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2054:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2055:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2056:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
; NoVLX-NEXT: kshiftrw $15, %k1, %k1 ; NoVLX-NEXT: kshiftrw $15, %k1, %k1
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2057:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2058:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2059:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2060:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2061:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2062:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2063:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2064:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2065:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $32, %rsp ; NoVLX-NEXT: subq $32, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kshiftlw $15, %k0, %k1 ; NoVLX-NEXT: kshiftlw $15, %k0, %k1
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2066:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2067:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2068:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2069:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2070:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2071:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2072:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2073:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2074:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2075:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2076:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2077:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask_mem: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask_mem:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2078:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2079:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2080:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; VLX-NEXT: kmovq %k0, %rax ; VLX-NEXT: kmovq %k0, %rax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask_mem_b: ; NoVLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_mask_mem_b:
; NoVLX: # BB#0: # %entry ; NoVLX: # BB#0: # %entry
; NoVLX-NEXT: pushq %rbp ; NoVLX-NEXT: pushq %rbp
; NoVLX-NEXT: .Lcfi2081:
; NoVLX-NEXT: .cfi_def_cfa_offset 16 ; NoVLX-NEXT: .cfi_def_cfa_offset 16
; NoVLX-NEXT: .Lcfi2082:
; NoVLX-NEXT: .cfi_offset %rbp, -16 ; NoVLX-NEXT: .cfi_offset %rbp, -16
; NoVLX-NEXT: movq %rsp, %rbp ; NoVLX-NEXT: movq %rsp, %rbp
; NoVLX-NEXT: .Lcfi2083:
; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: .cfi_def_cfa_register %rbp
; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: andq $-32, %rsp
; NoVLX-NEXT: subq $64, %rsp ; NoVLX-NEXT: subq $64, %rsp
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kxorw %k0, %k0, %k1
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp)
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll

Show First 20 Lines • Show All 306 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: v32i16: ; AVX512F-LABEL: v32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: .Lcfi0:
; AVX512F-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-NEXT: .cfi_def_cfa_offset 16
; AVX512F-NEXT: .Lcfi1:
; AVX512F-NEXT: .cfi_offset %rbp, -16 ; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp ; AVX512F-NEXT: movq %rsp, %rbp
; AVX512F-NEXT: .Lcfi2:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp ; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp ; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $32, %rsp ; AVX512F-NEXT: subq $32, %rsp
; AVX512F-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1 ; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1
; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1 ; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0 ; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k1 ; AVX512F-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 716 Lines • ▼ Show 20 Lines
; SSE-NEXT: orl %edx, %eax ; SSE-NEXT: orl %edx, %eax
; SSE-NEXT: shlq $32, %rax ; SSE-NEXT: shlq $32, %rax
; SSE-NEXT: orq %rcx, %rax ; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v64i8: ; AVX1-LABEL: v64i8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi0:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi1:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi2:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $64, %rsp ; AVX1-NEXT: subq $64, %rsp
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm8 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm8
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm9 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm9
; AVX1-NEXT: vpcmpgtb %xmm8, %xmm9, %xmm8 ; AVX1-NEXT: vpcmpgtb %xmm8, %xmm9, %xmm8
; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm8, %ymm1, %ymm8 ; AVX1-NEXT: vinsertf128 $1, %xmm8, %ymm1, %ymm8
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Lines
; AVX1-NEXT: movq %rbp, %rsp ; AVX1-NEXT: movq %rbp, %rsp
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: v64i8: ; AVX2-LABEL: v64i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi1:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi2:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $64, %rsp ; AVX2-NEXT: subq $64, %rsp
; AVX2-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm2
; AVX2-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm0 ; AVX2-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm0
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpcmpgtb %ymm6, %ymm4, %ymm1 ; AVX2-NEXT: vpcmpgtb %ymm6, %ymm4, %ymm1
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; AVX2-NEXT: movq %rbp, %rsp ; AVX2-NEXT: movq %rbp, %rsp
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: v64i8: ; AVX512F-LABEL: v64i8:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: .Lcfi3:
; AVX512F-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-NEXT: .cfi_def_cfa_offset 16
; AVX512F-NEXT: .Lcfi4:
; AVX512F-NEXT: .cfi_offset %rbp, -16 ; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp ; AVX512F-NEXT: movq %rsp, %rbp
; AVX512F-NEXT: .Lcfi5:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp ; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp ; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $64, %rsp ; AVX512F-NEXT: subq $64, %rsp
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm2 ; AVX512F-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm2
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpcmpgtb %ymm6, %ymm4, %ymm2 ; AVX512F-NEXT: vpcmpgtb %ymm6, %ymm4, %ymm2
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0 ; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0
; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i16_16i8: ; AVX512-LABEL: ext_i16_16i8:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: pushq %rbp ; AVX512-NEXT: pushq %rbp
; AVX512-NEXT: .Lcfi0:
; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: .cfi_def_cfa_offset 16
; AVX512-NEXT: pushq %r15 ; AVX512-NEXT: pushq %r15
; AVX512-NEXT: .Lcfi1:
; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: .cfi_def_cfa_offset 24
; AVX512-NEXT: pushq %r14 ; AVX512-NEXT: pushq %r14
; AVX512-NEXT: .Lcfi2:
; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: .cfi_def_cfa_offset 32
; AVX512-NEXT: pushq %r13 ; AVX512-NEXT: pushq %r13
; AVX512-NEXT: .Lcfi3:
; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: .cfi_def_cfa_offset 40
; AVX512-NEXT: pushq %r12 ; AVX512-NEXT: pushq %r12
; AVX512-NEXT: .Lcfi4:
; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: .cfi_def_cfa_offset 48
; AVX512-NEXT: pushq %rbx ; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: .Lcfi5:
; AVX512-NEXT: .cfi_def_cfa_offset 56 ; AVX512-NEXT: .cfi_def_cfa_offset 56
; AVX512-NEXT: .Lcfi6:
; AVX512-NEXT: .cfi_offset %rbx, -56 ; AVX512-NEXT: .cfi_offset %rbx, -56
; AVX512-NEXT: .Lcfi7:
; AVX512-NEXT: .cfi_offset %r12, -48 ; AVX512-NEXT: .cfi_offset %r12, -48
; AVX512-NEXT: .Lcfi8:
; AVX512-NEXT: .cfi_offset %r13, -40 ; AVX512-NEXT: .cfi_offset %r13, -40
; AVX512-NEXT: .Lcfi9:
; AVX512-NEXT: .cfi_offset %r14, -32 ; AVX512-NEXT: .cfi_offset %r14, -32
; AVX512-NEXT: .Lcfi10:
; AVX512-NEXT: .cfi_offset %r15, -24 ; AVX512-NEXT: .cfi_offset %r15, -24
; AVX512-NEXT: .Lcfi11:
; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: .cfi_offset %rbp, -16
; AVX512-NEXT: kmovd %edi, %k0 ; AVX512-NEXT: kmovd %edi, %k0
; AVX512-NEXT: kshiftlw $14, %k0, %k1 ; AVX512-NEXT: kshiftlw $14, %k0, %k1
; AVX512-NEXT: kshiftrw $15, %k1, %k1 ; AVX512-NEXT: kshiftrw $15, %k1, %k1
; AVX512-NEXT: kmovd %k1, %r8d ; AVX512-NEXT: kmovd %k1, %r8d
; AVX512-NEXT: kshiftlw $15, %k0, %k1 ; AVX512-NEXT: kshiftlw $15, %k0, %k1
; AVX512-NEXT: kshiftrw $15, %k1, %k1 ; AVX512-NEXT: kshiftrw $15, %k1, %k1
; AVX512-NEXT: kmovd %k1, %r9d ; AVX512-NEXT: kmovd %k1, %r9d
▲ Show 20 Lines • Show All 684 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: v32i16: ; AVX512F-LABEL: v32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: .Lcfi0:
; AVX512F-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-NEXT: .cfi_def_cfa_offset 16
; AVX512F-NEXT: .Lcfi1:
; AVX512F-NEXT: .cfi_offset %rbp, -16 ; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp ; AVX512F-NEXT: movq %rsp, %rbp
; AVX512F-NEXT: .Lcfi2:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp ; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp ; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $32, %rsp ; AVX512F-NEXT: subq $32, %rsp
; AVX512F-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1 ; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1
; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1 ; AVX512F-NEXT: vpslld $31, %zmm1, %zmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0 ; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k1 ; AVX512F-NEXT: kshiftlw $14, %k0, %k1
▲ Show 20 Lines • Show All 486 Lines • ▼ Show 20 Lines
; SSE-NEXT: orl %edx, %eax ; SSE-NEXT: orl %edx, %eax
; SSE-NEXT: shlq $32, %rax ; SSE-NEXT: shlq $32, %rax
; SSE-NEXT: orq %rcx, %rax ; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v64i8: ; AVX1-LABEL: v64i8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi0:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi1:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi2:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $64, %rsp ; AVX1-NEXT: subq $64, %rsp
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
; AVX1-NEXT: vpcmpgtb %xmm4, %xmm5, %xmm4 ; AVX1-NEXT: vpcmpgtb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpextrb $15, %xmm4, %eax ; AVX1-NEXT: vpextrb $15, %xmm4, %eax
; AVX1-NEXT: andb $1, %al ; AVX1-NEXT: andb $1, %al
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; AVX1-NEXT: movq %rbp, %rsp ; AVX1-NEXT: movq %rbp, %rsp
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: v64i8: ; AVX2-LABEL: v64i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi1:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi2:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $64, %rsp ; AVX2-NEXT: subq $64, %rsp
; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpextrb $15, %xmm2, %eax ; AVX2-NEXT: vpextrb $15, %xmm2, %eax
; AVX2-NEXT: andb $1, %al ; AVX2-NEXT: andb $1, %al
; AVX2-NEXT: movb %al, (%rsp) ; AVX2-NEXT: movb %al, (%rsp)
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
; AVX2-NEXT: movq %rbp, %rsp ; AVX2-NEXT: movq %rbp, %rsp
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: v64i8: ; AVX512F-LABEL: v64i8:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: .Lcfi3:
; AVX512F-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-NEXT: .cfi_def_cfa_offset 16
; AVX512F-NEXT: .Lcfi4:
; AVX512F-NEXT: .cfi_offset %rbp, -16 ; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp ; AVX512F-NEXT: movq %rsp, %rbp
; AVX512F-NEXT: .Lcfi5:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp ; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp ; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $64, %rsp ; AVX512F-NEXT: subq $64, %rsp
; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512F-NEXT: vpmovsxbd %xmm2, %zmm2 ; AVX512F-NEXT: vpmovsxbd %xmm2, %zmm2
; AVX512F-NEXT: vpslld $31, %zmm2, %zmm2 ; AVX512F-NEXT: vpslld $31, %zmm2, %zmm2
; AVX512F-NEXT: vptestmd %zmm2, %zmm2, %k0 ; AVX512F-NEXT: vptestmd %zmm2, %zmm2, %k0
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bool-vector.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%2 = zext i4 %1 to i32 %2 = zext i4 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @PR15215_good(<4 x i32> %input) { define i32 @PR15215_good(<4 x i32> %input) {
; X32-LABEL: PR15215_good: ; X32-LABEL: PR15215_good:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_offset %esi, -8 ; X32-NEXT: .cfi_offset %esi, -8
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andl $1, %eax ; X32-NEXT: andl $1, %eax
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: andl $1, %ecx ; X32-NEXT: andl $1, %ecx
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X32-NEXT: andl $1, %edx ; X32-NEXT: andl $1, %edx
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %esi
; X32-NEXT: andl $1, %esi ; X32-NEXT: andl $1, %esi
; X32-NEXT: leal (%eax,%ecx,2), %eax ; X32-NEXT: leal (%eax,%ecx,2), %eax
; X32-NEXT: leal (%eax,%edx,4), %eax ; X32-NEXT: leal (%eax,%edx,4), %eax
; X32-NEXT: leal (%eax,%esi,8), %eax ; X32-NEXT: leal (%eax,%esi,8), %eax
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X32-SSE2-LABEL: PR15215_good: ; X32-SSE2-LABEL: PR15215_good:
; X32-SSE2: # BB#0: # %entry ; X32-SSE2: # BB#0: # %entry
; X32-SSE2-NEXT: pushl %esi ; X32-SSE2-NEXT: pushl %esi
; X32-SSE2-NEXT: .Lcfi0:
; X32-SSE2-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE2-NEXT: .cfi_def_cfa_offset 8
; X32-SSE2-NEXT: .Lcfi1:
; X32-SSE2-NEXT: .cfi_offset %esi, -8 ; X32-SSE2-NEXT: .cfi_offset %esi, -8
; X32-SSE2-NEXT: movd %xmm0, %eax ; X32-SSE2-NEXT: movd %xmm0, %eax
; X32-SSE2-NEXT: andl $1, %eax ; X32-SSE2-NEXT: andl $1, %eax
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; X32-SSE2-NEXT: movd %xmm1, %ecx ; X32-SSE2-NEXT: movd %xmm1, %ecx
; X32-SSE2-NEXT: andl $1, %ecx ; X32-SSE2-NEXT: andl $1, %ecx
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X32-SSE2-NEXT: movd %xmm1, %edx ; X32-SSE2-NEXT: movd %xmm1, %edx
; X32-SSE2-NEXT: andl $1, %edx ; X32-SSE2-NEXT: andl $1, %edx
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; X32-SSE2-NEXT: movd %xmm0, %esi ; X32-SSE2-NEXT: movd %xmm0, %esi
; X32-SSE2-NEXT: andl $1, %esi ; X32-SSE2-NEXT: andl $1, %esi
; X32-SSE2-NEXT: leal (%eax,%ecx,2), %eax ; X32-SSE2-NEXT: leal (%eax,%ecx,2), %eax
; X32-SSE2-NEXT: leal (%eax,%edx,4), %eax ; X32-SSE2-NEXT: leal (%eax,%edx,4), %eax
; X32-SSE2-NEXT: leal (%eax,%esi,8), %eax ; X32-SSE2-NEXT: leal (%eax,%esi,8), %eax
; X32-SSE2-NEXT: popl %esi ; X32-SSE2-NEXT: popl %esi
; X32-SSE2-NEXT: retl ; X32-SSE2-NEXT: retl
; ;
; X32-AVX2-LABEL: PR15215_good: ; X32-AVX2-LABEL: PR15215_good:
; X32-AVX2: # BB#0: # %entry ; X32-AVX2: # BB#0: # %entry
; X32-AVX2-NEXT: pushl %esi ; X32-AVX2-NEXT: pushl %esi
; X32-AVX2-NEXT: .Lcfi0:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 8 ; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
; X32-AVX2-NEXT: .Lcfi1:
; X32-AVX2-NEXT: .cfi_offset %esi, -8 ; X32-AVX2-NEXT: .cfi_offset %esi, -8
; X32-AVX2-NEXT: vmovd %xmm0, %eax ; X32-AVX2-NEXT: vmovd %xmm0, %eax
; X32-AVX2-NEXT: andl $1, %eax ; X32-AVX2-NEXT: andl $1, %eax
; X32-AVX2-NEXT: vpextrd $1, %xmm0, %ecx ; X32-AVX2-NEXT: vpextrd $1, %xmm0, %ecx
; X32-AVX2-NEXT: andl $1, %ecx ; X32-AVX2-NEXT: andl $1, %ecx
; X32-AVX2-NEXT: vpextrd $2, %xmm0, %edx ; X32-AVX2-NEXT: vpextrd $2, %xmm0, %edx
; X32-AVX2-NEXT: andl $1, %edx ; X32-AVX2-NEXT: andl $1, %edx
; X32-AVX2-NEXT: vpextrd $3, %xmm0, %esi ; X32-AVX2-NEXT: vpextrd $3, %xmm0, %esi
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llvm/trunk/test/CodeGen/X86/cmp.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Linesentry:
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @test12() ssp uwtable { define i32 @test12() ssp uwtable {
; CHECK-LABEL: test12: ; CHECK-LABEL: test12:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushq %rax # encoding: [0x50] ; CHECK-NEXT: pushq %rax # encoding: [0x50]
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq test12b # encoding: [0xe8,A,A,A,A] ; CHECK-NEXT: callq test12b # encoding: [0xe8,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 1, value: test12b-4, kind: FK_PCRel_4 ; CHECK-NEXT: # fixup A - offset: 1, value: test12b-4, kind: FK_PCRel_4
; CHECK-NEXT: testb %al, %al # encoding: [0x84,0xc0] ; CHECK-NEXT: testb %al, %al # encoding: [0x84,0xc0]
; CHECK-NEXT: je .LBB12_2 # encoding: [0x74,A] ; CHECK-NEXT: je .LBB12_2 # encoding: [0x74,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1 ; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
; CHECK-NEXT: # BB#1: # %T ; CHECK-NEXT: # BB#1: # %T
; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] ; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s ; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
declare webkit_jscc i64 @llvm.experimental.deoptimize.i64(...) declare webkit_jscc i64 @llvm.experimental.deoptimize.i64(...)
define i64 @caller_1() { define i64 @caller_1() {
; CHECK-LABEL: _caller_1: ; CHECK-LABEL: _caller_1:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}} ; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: movl $1140457472, (%rsp) ## imm = 0x43FA0000 ; CHECK-NEXT: movl $1140457472, (%rsp) ## imm = 0x43FA0000
; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: callq ___llvm_deoptimize ; CHECK-NEXT: callq ___llvm_deoptimize
; CHECK-NEXT: {{Ltmp[0-9]+}}: ; CHECK-NEXT: {{Ltmp[0-9]+}}:
entry: entry:
%v = call webkit_jscc i64(...) @llvm.experimental.deoptimize.i64(i32 42, float 500.0) [ "deopt"(i32 3) ] %v = call webkit_jscc i64(...) @llvm.experimental.deoptimize.i64(i32 42, float 500.0) [ "deopt"(i32 3) ]
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llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s ; RUN: llc -debug-only=stackmaps < %s 2>&1 | FileCheck --check-prefix=STACKMAPS %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
declare i32 @llvm.experimental.deoptimize.i32(...) declare i32 @llvm.experimental.deoptimize.i32(...)
declare i8 @llvm.experimental.deoptimize.i8(...) declare i8 @llvm.experimental.deoptimize.i8(...)
define i32 @caller_0() { define i32 @caller_0() {
; CHECK-LABEL: _caller_0: ; CHECK-LABEL: _caller_0:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}} ; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: callq ___llvm_deoptimize ; CHECK-NEXT: callq ___llvm_deoptimize
; CHECK-NEXT: {{Ltmp[0-9]+}}: ; CHECK-NEXT: {{Ltmp[0-9]+}}:
entry: entry:
%v = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 0) ] %v = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 0) ]
ret i32 %v ret i32 %v
} }
define i8 @caller_1() { define i8 @caller_1() {
; CHECK-LABEL: _caller_1: ; CHECK-LABEL: _caller_1:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}} ; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}} ; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: movss {{[a-zA-Z0-9_]+}}(%rip), %xmm0 ## xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{[a-zA-Z0-9_]+}}(%rip), %xmm0 ## xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movl $42, %edi ; CHECK-NEXT: movl $42, %edi
; CHECK-NEXT: callq ___llvm_deoptimize ; CHECK-NEXT: callq ___llvm_deoptimize
; CHECK-NEXT: {{Ltmp[0-9]+}}: ; CHECK-NEXT: {{Ltmp[0-9]+}}:
entry: entry:
%v = call i8(...) @llvm.experimental.deoptimize.i8(i32 42, float 500.0) [ "deopt"(i32 1) ] %v = call i8(...) @llvm.experimental.deoptimize.i8(i32 42, float 500.0) [ "deopt"(i32 1) ]
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llvm/trunk/test/CodeGen/X86/empty-functions.ll

Show All 12 Lines
; CHECK-NO-FP-NEXT: .cfi_startproc ; CHECK-NO-FP-NEXT: .cfi_startproc
; CHECK-NO-FP: nop ; CHECK-NO-FP: nop
; CHECK-NO-FP-NEXT: .cfi_endproc ; CHECK-NO-FP-NEXT: .cfi_endproc
; CHECK-FP: _func: ; CHECK-FP: _func:
; CHECK-FP-NEXT: .cfi_startproc ; CHECK-FP-NEXT: .cfi_startproc
; CHECK-FP-NEXT: : ; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: pushq %rbp ; CHECK-FP-NEXT: pushq %rbp
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_def_cfa_offset 16 ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_offset %rbp, -16 ; CHECK-FP-NEXT: .cfi_offset %rbp, -16
; CHECK-FP-NEXT: movq %rsp, %rbp ; CHECK-FP-NEXT: movq %rsp, %rbp
; CHECK-FP-NEXT: .cfi_endproc ; CHECK-FP-NEXT: .cfi_endproc
; An empty function is perfectly fine on ELF. ; An empty function is perfectly fine on ELF.
; LINUX-NO-FP: func: ; LINUX-NO-FP: func:
; LINUX-NO-FP-NEXT: .cfi_startproc ; LINUX-NO-FP-NEXT: .cfi_startproc
; LINUX-NO-FP-NEXT: {{^}}# ; LINUX-NO-FP-NEXT: {{^}}#
; LINUX-NO-FP-NEXT: {{^}}.L{{.*}}:{{$}} ; LINUX-NO-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-NO-FP-NEXT: .size func, .L{{.*}}-func ; LINUX-NO-FP-NEXT: .size func, .L{{.*}}-func
; LINUX-NO-FP-NEXT: .cfi_endproc ; LINUX-NO-FP-NEXT: .cfi_endproc
; A cfi directive cannot point to the end of a function. ; A cfi directive cannot point to the end of a function.
; LINUX-FP: func: ; LINUX-FP: func:
; LINUX-FP-NEXT: .cfi_startproc ; LINUX-FP-NEXT: .cfi_startproc
; LINUX-FP-NEXT: {{^}}# ; LINUX-FP-NEXT: {{^}}#
; LINUX-FP-NEXT: pushq %rbp ; LINUX-FP-NEXT: pushq %rbp
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .cfi_def_cfa_offset 16 ; LINUX-FP-NEXT: .cfi_def_cfa_offset 16
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .cfi_offset %rbp, -16 ; LINUX-FP-NEXT: .cfi_offset %rbp, -16
; LINUX-FP-NEXT: movq %rsp, %rbp ; LINUX-FP-NEXT: movq %rsp, %rbp
; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}} ; LINUX-FP-NEXT:{{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .size func, .Lfunc_end0-func ; LINUX-FP-NEXT: .size func, .Lfunc_end0-func
; LINUX-FP-NEXT: .cfi_endproc ; LINUX-FP-NEXT: .cfi_endproc

llvm/trunk/test/CodeGen/X86/fast-isel-store.ll

Show First 20 Lines • Show All 362 Lines • ▼ Show 20 Lines
; SSE32-NEXT: addpd %xmm2, %xmm0 ; SSE32-NEXT: addpd %xmm2, %xmm0
; SSE32-NEXT: movupd %xmm0, (%rdi) ; SSE32-NEXT: movupd %xmm0, (%rdi)
; SSE32-NEXT: movupd %xmm1, 16(%rdi) ; SSE32-NEXT: movupd %xmm1, 16(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_4xf64: ; SSE64-LABEL: test_store_4xf64:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi0:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd %xmm2, %xmm0 ; SSE64-NEXT: addpd %xmm2, %xmm0
; SSE64-NEXT: movupd %xmm0, (%eax) ; SSE64-NEXT: movupd %xmm0, (%eax)
; SSE64-NEXT: movupd %xmm1, 16(%eax) ; SSE64-NEXT: movupd %xmm1, 16(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: retl ; SSE64-NEXT: retl
Show All 22 Lines
; SSE32-NEXT: addpd %xmm2, %xmm0 ; SSE32-NEXT: addpd %xmm2, %xmm0
; SSE32-NEXT: movapd %xmm0, (%rdi) ; SSE32-NEXT: movapd %xmm0, (%rdi)
; SSE32-NEXT: movapd %xmm1, 16(%rdi) ; SSE32-NEXT: movapd %xmm1, 16(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_4xf64_aligned: ; SSE64-LABEL: test_store_4xf64_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi1:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd %xmm2, %xmm0 ; SSE64-NEXT: addpd %xmm2, %xmm0
; SSE64-NEXT: movapd %xmm0, (%eax) ; SSE64-NEXT: movapd %xmm0, (%eax)
; SSE64-NEXT: movapd %xmm1, 16(%eax) ; SSE64-NEXT: movapd %xmm1, 16(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: retl ; SSE64-NEXT: retl
Show All 22 Lines
; SSE32-NEXT: movups %xmm1, 16(%rdi) ; SSE32-NEXT: movups %xmm1, 16(%rdi)
; SSE32-NEXT: movups %xmm2, 32(%rdi) ; SSE32-NEXT: movups %xmm2, 32(%rdi)
; SSE32-NEXT: movups %xmm3, 48(%rdi) ; SSE32-NEXT: movups %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xi32: ; SSE64-LABEL: test_store_16xi32:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi2:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movups %xmm0, (%eax) ; SSE64-NEXT: movups %xmm0, (%eax)
; SSE64-NEXT: movups %xmm1, 16(%eax) ; SSE64-NEXT: movups %xmm1, 16(%eax)
; SSE64-NEXT: movups %xmm2, 32(%eax) ; SSE64-NEXT: movups %xmm2, 32(%eax)
; SSE64-NEXT: movups %xmm3, 48(%eax) ; SSE64-NEXT: movups %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
Show All 33 Lines
; SSE32-NEXT: movaps %xmm1, 16(%rdi) ; SSE32-NEXT: movaps %xmm1, 16(%rdi)
; SSE32-NEXT: movaps %xmm2, 32(%rdi) ; SSE32-NEXT: movaps %xmm2, 32(%rdi)
; SSE32-NEXT: movaps %xmm3, 48(%rdi) ; SSE32-NEXT: movaps %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xi32_aligned: ; SSE64-LABEL: test_store_16xi32_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi3:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movaps %xmm0, (%eax) ; SSE64-NEXT: movaps %xmm0, (%eax)
; SSE64-NEXT: movaps %xmm1, 16(%eax) ; SSE64-NEXT: movaps %xmm1, 16(%eax)
; SSE64-NEXT: movaps %xmm2, 32(%eax) ; SSE64-NEXT: movaps %xmm2, 32(%eax)
; SSE64-NEXT: movaps %xmm3, 48(%eax) ; SSE64-NEXT: movaps %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
Show All 33 Lines
; SSE32-NEXT: movups %xmm1, 16(%rdi) ; SSE32-NEXT: movups %xmm1, 16(%rdi)
; SSE32-NEXT: movups %xmm2, 32(%rdi) ; SSE32-NEXT: movups %xmm2, 32(%rdi)
; SSE32-NEXT: movups %xmm3, 48(%rdi) ; SSE32-NEXT: movups %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xf32: ; SSE64-LABEL: test_store_16xf32:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi4:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movups %xmm0, (%eax) ; SSE64-NEXT: movups %xmm0, (%eax)
; SSE64-NEXT: movups %xmm1, 16(%eax) ; SSE64-NEXT: movups %xmm1, 16(%eax)
; SSE64-NEXT: movups %xmm2, 32(%eax) ; SSE64-NEXT: movups %xmm2, 32(%eax)
; SSE64-NEXT: movups %xmm3, 48(%eax) ; SSE64-NEXT: movups %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
Show All 33 Lines
; SSE32-NEXT: movaps %xmm1, 16(%rdi) ; SSE32-NEXT: movaps %xmm1, 16(%rdi)
; SSE32-NEXT: movaps %xmm2, 32(%rdi) ; SSE32-NEXT: movaps %xmm2, 32(%rdi)
; SSE32-NEXT: movaps %xmm3, 48(%rdi) ; SSE32-NEXT: movaps %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xf32_aligned: ; SSE64-LABEL: test_store_16xf32_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi5:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movaps %xmm0, (%eax) ; SSE64-NEXT: movaps %xmm0, (%eax)
; SSE64-NEXT: movaps %xmm1, 16(%eax) ; SSE64-NEXT: movaps %xmm1, 16(%eax)
; SSE64-NEXT: movaps %xmm2, 32(%eax) ; SSE64-NEXT: movaps %xmm2, 32(%eax)
; SSE64-NEXT: movaps %xmm3, 48(%eax) ; SSE64-NEXT: movaps %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
Show All 37 Lines
; SSE32-NEXT: movupd %xmm1, 16(%rdi) ; SSE32-NEXT: movupd %xmm1, 16(%rdi)
; SSE32-NEXT: movupd %xmm2, 32(%rdi) ; SSE32-NEXT: movupd %xmm2, 32(%rdi)
; SSE32-NEXT: movupd %xmm3, 48(%rdi) ; SSE32-NEXT: movupd %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_8xf64: ; SSE64-LABEL: test_store_8xf64:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi6:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0
; SSE64-NEXT: movupd %xmm0, (%eax) ; SSE64-NEXT: movupd %xmm0, (%eax)
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; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY32-NEXT: vmovupd %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovupd %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovupd %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovupd %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
; AVXONLY64-LABEL: test_store_8xf64: ; AVXONLY64-LABEL: test_store_8xf64:
; AVXONLY64: # BB#0: ; AVXONLY64: # BB#0:
; AVXONLY64-NEXT: pushl %ebp ; AVXONLY64-NEXT: pushl %ebp
; AVXONLY64-NEXT: .Lcfi0:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8 ; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
; AVXONLY64-NEXT: .Lcfi1:
; AVXONLY64-NEXT: .cfi_offset %ebp, -8 ; AVXONLY64-NEXT: .cfi_offset %ebp, -8
; AVXONLY64-NEXT: movl %esp, %ebp ; AVXONLY64-NEXT: movl %esp, %ebp
; AVXONLY64-NEXT: .Lcfi2:
; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp ; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp
; AVXONLY64-NEXT: andl $-32, %esp ; AVXONLY64-NEXT: andl $-32, %esp
; AVXONLY64-NEXT: subl $32, %esp ; AVXONLY64-NEXT: subl $32, %esp
; AVXONLY64-NEXT: movl 8(%ebp), %eax ; AVXONLY64-NEXT: movl 8(%ebp), %eax
; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1 ; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1
; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY64-NEXT: vmovupd %ymm0, (%eax) ; AVXONLY64-NEXT: vmovupd %ymm0, (%eax)
; AVXONLY64-NEXT: vmovupd %ymm1, 32(%eax) ; AVXONLY64-NEXT: vmovupd %ymm1, 32(%eax)
Show All 29 Lines
; SSE32-NEXT: movapd %xmm1, 16(%rdi) ; SSE32-NEXT: movapd %xmm1, 16(%rdi)
; SSE32-NEXT: movapd %xmm2, 32(%rdi) ; SSE32-NEXT: movapd %xmm2, 32(%rdi)
; SSE32-NEXT: movapd %xmm3, 48(%rdi) ; SSE32-NEXT: movapd %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_8xf64_aligned: ; SSE64-LABEL: test_store_8xf64_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi7:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0
; SSE64-NEXT: movapd %xmm0, (%eax) ; SSE64-NEXT: movapd %xmm0, (%eax)
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; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY32-NEXT: vmovapd %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovapd %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovapd %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovapd %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
; AVXONLY64-LABEL: test_store_8xf64_aligned: ; AVXONLY64-LABEL: test_store_8xf64_aligned:
; AVXONLY64: # BB#0: ; AVXONLY64: # BB#0:
; AVXONLY64-NEXT: pushl %ebp ; AVXONLY64-NEXT: pushl %ebp
; AVXONLY64-NEXT: .Lcfi3:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8 ; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
; AVXONLY64-NEXT: .Lcfi4:
; AVXONLY64-NEXT: .cfi_offset %ebp, -8 ; AVXONLY64-NEXT: .cfi_offset %ebp, -8
; AVXONLY64-NEXT: movl %esp, %ebp ; AVXONLY64-NEXT: movl %esp, %ebp
; AVXONLY64-NEXT: .Lcfi5:
; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp ; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp
; AVXONLY64-NEXT: andl $-32, %esp ; AVXONLY64-NEXT: andl $-32, %esp
; AVXONLY64-NEXT: subl $32, %esp ; AVXONLY64-NEXT: subl $32, %esp
; AVXONLY64-NEXT: movl 8(%ebp), %eax ; AVXONLY64-NEXT: movl 8(%ebp), %eax
; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1 ; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1
; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY64-NEXT: vmovapd %ymm0, (%eax) ; AVXONLY64-NEXT: vmovapd %ymm0, (%eax)
; AVXONLY64-NEXT: vmovapd %ymm1, 32(%eax) ; AVXONLY64-NEXT: vmovapd %ymm1, 32(%eax)
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llvm/trunk/test/CodeGen/X86/haddsub-2.ll

Show First 20 Lines • Show All 618 Lines • ▼ Show 20 Lines; AVX2-NEXT: retq
%vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7 %vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
ret <8 x i32> %vecinit29 ret <8 x i32> %vecinit29
} }
define <16 x i16> @avx2_vphadd_w_test(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @avx2_vphadd_w_test(<16 x i16> %a, <16 x i16> %b) {
; SSE3-LABEL: avx2_vphadd_w_test: ; SSE3-LABEL: avx2_vphadd_w_test:
; SSE3: # BB#0: ; SSE3: # BB#0:
; SSE3-NEXT: pushq %rbp ; SSE3-NEXT: pushq %rbp
; SSE3-NEXT: .Lcfi0:
; SSE3-NEXT: .cfi_def_cfa_offset 16 ; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: pushq %r15 ; SSE3-NEXT: pushq %r15
; SSE3-NEXT: .Lcfi1:
; SSE3-NEXT: .cfi_def_cfa_offset 24 ; SSE3-NEXT: .cfi_def_cfa_offset 24
; SSE3-NEXT: pushq %r14 ; SSE3-NEXT: pushq %r14
; SSE3-NEXT: .Lcfi2:
; SSE3-NEXT: .cfi_def_cfa_offset 32 ; SSE3-NEXT: .cfi_def_cfa_offset 32
; SSE3-NEXT: pushq %r13 ; SSE3-NEXT: pushq %r13
; SSE3-NEXT: .Lcfi3:
; SSE3-NEXT: .cfi_def_cfa_offset 40 ; SSE3-NEXT: .cfi_def_cfa_offset 40
; SSE3-NEXT: pushq %r12 ; SSE3-NEXT: pushq %r12
; SSE3-NEXT: .Lcfi4:
; SSE3-NEXT: .cfi_def_cfa_offset 48 ; SSE3-NEXT: .cfi_def_cfa_offset 48
; SSE3-NEXT: pushq %rbx ; SSE3-NEXT: pushq %rbx
; SSE3-NEXT: .Lcfi5:
; SSE3-NEXT: .cfi_def_cfa_offset 56 ; SSE3-NEXT: .cfi_def_cfa_offset 56
; SSE3-NEXT: .Lcfi6:
; SSE3-NEXT: .cfi_offset %rbx, -56 ; SSE3-NEXT: .cfi_offset %rbx, -56
; SSE3-NEXT: .Lcfi7:
; SSE3-NEXT: .cfi_offset %r12, -48 ; SSE3-NEXT: .cfi_offset %r12, -48
; SSE3-NEXT: .Lcfi8:
; SSE3-NEXT: .cfi_offset %r13, -40 ; SSE3-NEXT: .cfi_offset %r13, -40
; SSE3-NEXT: .Lcfi9:
; SSE3-NEXT: .cfi_offset %r14, -32 ; SSE3-NEXT: .cfi_offset %r14, -32
; SSE3-NEXT: .Lcfi10:
; SSE3-NEXT: .cfi_offset %r15, -24 ; SSE3-NEXT: .cfi_offset %r15, -24
; SSE3-NEXT: .Lcfi11:
; SSE3-NEXT: .cfi_offset %rbp, -16 ; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movd %xmm0, %eax ; SSE3-NEXT: movd %xmm0, %eax
; SSE3-NEXT: pextrw $1, %xmm0, %ecx ; SSE3-NEXT: pextrw $1, %xmm0, %ecx
; SSE3-NEXT: addl %eax, %ecx ; SSE3-NEXT: addl %eax, %ecx
; SSE3-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) # 4-byte Spill ; SSE3-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) # 4-byte Spill
; SSE3-NEXT: pextrw $2, %xmm0, %eax ; SSE3-NEXT: pextrw $2, %xmm0, %eax
; SSE3-NEXT: pextrw $3, %xmm0, %ecx ; SSE3-NEXT: pextrw $3, %xmm0, %ecx
; SSE3-NEXT: addl %eax, %ecx ; SSE3-NEXT: addl %eax, %ecx
▲ Show 20 Lines • Show All 595 Lines • ▼ Show 20 Lines; AVX2-NEXT: retq
%vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7 %vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
ret <8 x i32> %vecinit29 ret <8 x i32> %vecinit29
} }
define <16 x i16> @avx2_hadd_w(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @avx2_hadd_w(<16 x i16> %a, <16 x i16> %b) {
; SSE3-LABEL: avx2_hadd_w: ; SSE3-LABEL: avx2_hadd_w:
; SSE3: # BB#0: ; SSE3: # BB#0:
; SSE3-NEXT: pushq %rbp ; SSE3-NEXT: pushq %rbp
; SSE3-NEXT: .Lcfi12:
; SSE3-NEXT: .cfi_def_cfa_offset 16 ; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: pushq %r15 ; SSE3-NEXT: pushq %r15
; SSE3-NEXT: .Lcfi13:
; SSE3-NEXT: .cfi_def_cfa_offset 24 ; SSE3-NEXT: .cfi_def_cfa_offset 24
; SSE3-NEXT: pushq %r14 ; SSE3-NEXT: pushq %r14
; SSE3-NEXT: .Lcfi14:
; SSE3-NEXT: .cfi_def_cfa_offset 32 ; SSE3-NEXT: .cfi_def_cfa_offset 32
; SSE3-NEXT: pushq %r13 ; SSE3-NEXT: pushq %r13
; SSE3-NEXT: .Lcfi15:
; SSE3-NEXT: .cfi_def_cfa_offset 40 ; SSE3-NEXT: .cfi_def_cfa_offset 40
; SSE3-NEXT: pushq %r12 ; SSE3-NEXT: pushq %r12
; SSE3-NEXT: .Lcfi16:
; SSE3-NEXT: .cfi_def_cfa_offset 48 ; SSE3-NEXT: .cfi_def_cfa_offset 48
; SSE3-NEXT: pushq %rbx ; SSE3-NEXT: pushq %rbx
; SSE3-NEXT: .Lcfi17:
; SSE3-NEXT: .cfi_def_cfa_offset 56 ; SSE3-NEXT: .cfi_def_cfa_offset 56
; SSE3-NEXT: .Lcfi18:
; SSE3-NEXT: .cfi_offset %rbx, -56 ; SSE3-NEXT: .cfi_offset %rbx, -56
; SSE3-NEXT: .Lcfi19:
; SSE3-NEXT: .cfi_offset %r12, -48 ; SSE3-NEXT: .cfi_offset %r12, -48
; SSE3-NEXT: .Lcfi20:
; SSE3-NEXT: .cfi_offset %r13, -40 ; SSE3-NEXT: .cfi_offset %r13, -40
; SSE3-NEXT: .Lcfi21:
; SSE3-NEXT: .cfi_offset %r14, -32 ; SSE3-NEXT: .cfi_offset %r14, -32
; SSE3-NEXT: .Lcfi22:
; SSE3-NEXT: .cfi_offset %r15, -24 ; SSE3-NEXT: .cfi_offset %r15, -24
; SSE3-NEXT: .Lcfi23:
; SSE3-NEXT: .cfi_offset %rbp, -16 ; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movd %xmm0, %eax ; SSE3-NEXT: movd %xmm0, %eax
; SSE3-NEXT: pextrw $1, %xmm0, %r10d ; SSE3-NEXT: pextrw $1, %xmm0, %r10d
; SSE3-NEXT: addl %eax, %r10d ; SSE3-NEXT: addl %eax, %r10d
; SSE3-NEXT: pextrw $2, %xmm0, %eax ; SSE3-NEXT: pextrw $2, %xmm0, %eax
; SSE3-NEXT: pextrw $3, %xmm0, %r11d ; SSE3-NEXT: pextrw $3, %xmm0, %r11d
; SSE3-NEXT: addl %eax, %r11d ; SSE3-NEXT: addl %eax, %r11d
; SSE3-NEXT: pextrw $4, %xmm0, %eax ; SSE3-NEXT: pextrw $4, %xmm0, %eax
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/illegal-bitfield-loadstore.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; X64-NEXT: retq
store i24 %d, i24* %a, align 1 store i24 %d, i24* %a, align 1
ret void ret void
} }
define void @i24_insert_bit(i24* %a, i1 zeroext %bit) { define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
; X86-LABEL: i24_insert_bit: ; X86-LABEL: i24_insert_bit:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movzwl (%ecx), %esi ; X86-NEXT: movzwl (%ecx), %esi
; X86-NEXT: movzbl 2(%ecx), %eax ; X86-NEXT: movzbl 2(%ecx), %eax
; X86-NEXT: movb %al, 2(%ecx) ; X86-NEXT: movb %al, 2(%ecx)
; X86-NEXT: shll $16, %eax ; X86-NEXT: shll $16, %eax
; X86-NEXT: orl %esi, %eax ; X86-NEXT: orl %esi, %eax
▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/imul.ll

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
; X64-NEXT: shlq $5, %rax ; X64-NEXT: shlq $5, %rax
; X64-NEXT: subq %rdi, %rax ; X64-NEXT: subq %rdi, %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test5: ; X86-LABEL: test5:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: shll $5, %esi ; X86-NEXT: shll $5, %esi
; X86-NEXT: subl %eax, %esi ; X86-NEXT: subl %eax, %esi
; X86-NEXT: movl $-31, %edx ; X86-NEXT: movl $-31, %edx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
Show All 38 Lines
; X64-NEXT: shlq $5, %rax ; X64-NEXT: shlq $5, %rax
; X64-NEXT: leaq (%rax,%rdi), %rax ; X64-NEXT: leaq (%rax,%rdi), %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test7: ; X86-LABEL: test7:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: shll $5, %esi ; X86-NEXT: shll $5, %esi
; X86-NEXT: addl %eax, %esi ; X86-NEXT: addl %eax, %esi
; X86-NEXT: movl $-33, %edx ; X86-NEXT: movl $-33, %edx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
Show All 12 Lines
; X64: # BB#0: # %entry ; X64: # BB#0: # %entry
; X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF ; X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: imulq %rdi, %rax ; X64-NEXT: imulq %rdi, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: testOverflow: ; X86-LABEL: testOverflow:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi4:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi5:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl $-1, %edx ; X86-NEXT: movl $-1, %edx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %edx ; X86-NEXT: mull %edx
; X86-NEXT: movl %ecx, %esi ; X86-NEXT: movl %ecx, %esi
; X86-NEXT: shll $31, %esi ; X86-NEXT: shll $31, %esi
; X86-NEXT: subl %ecx, %esi ; X86-NEXT: subl %ecx, %esi
; X86-NEXT: addl %esi, %edx ; X86-NEXT: addl %esi, %edx
; X86-NEXT: subl {{[0-9]+}}(%esp), %edx ; X86-NEXT: subl {{[0-9]+}}(%esp), %edx
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%tmp3 = mul i64 %a, 9223372036854775807 %tmp3 = mul i64 %a, 9223372036854775807
ret i64 %tmp3 ret i64 %tmp3
} }

llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
} }
; PR4459 ; PR4459
; The return value from ceil must be duped before being consumed by asm. ; The return value from ceil must be duped before being consumed by asm.
define void @testPR4459(x86_fp80 %a) { define void @testPR4459(x86_fp80 %a) {
; CHECK-LABEL: testPR4459: ; CHECK-LABEL: testPR4459:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: subl $28, %esp ; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpt (%esp) ; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll _ceil ; CHECK-NEXT: calll _ceil
; CHECK-NEXT: fld %st(0) ; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: ## InlineAsm Start ; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistpl %st(0) ; CHECK-NEXT: fistpl %st(0)
; CHECK-NEXT: ## InlineAsm End ; CHECK-NEXT: ## InlineAsm End
Show All 12 Lines
; PR4484 ; PR4484
; test1 leaves a value on the stack that is needed after the asm. ; test1 leaves a value on the stack that is needed after the asm.
; Load %a from stack after ceil ; Load %a from stack after ceil
; Set up call to test. ; Set up call to test.
define void @testPR4484(x86_fp80 %a) { define void @testPR4484(x86_fp80 %a) {
; CHECK-LABEL: testPR4484: ; CHECK-LABEL: testPR4484:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: subl $28, %esp ; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpt {{[0-9]+}}(%esp) ## 10-byte Folded Spill ; CHECK-NEXT: fstpt {{[0-9]+}}(%esp) ## 10-byte Folded Spill
; CHECK-NEXT: calll _test1 ; CHECK-NEXT: calll _test1
; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ## 10-byte Folded Reload ; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ## 10-byte Folded Reload
; CHECK-NEXT: ## InlineAsm Start ; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistpl %st(0) ; CHECK-NEXT: fistpl %st(0)
; CHECK-NEXT: ## InlineAsm End ; CHECK-NEXT: ## InlineAsm End
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
@fpu = external global %struct.fpu_t, align 16 @fpu = external global %struct.fpu_t, align 16
; Function Attrs: ssp ; Function Attrs: ssp
define void @test_live_st(i32 %a1) { define void @test_live_st(i32 %a1) {
; CHECK-LABEL: test_live_st: ; CHECK-LABEL: test_live_st:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fldt (%eax) ; CHECK-NEXT: fldt (%eax)
; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: jne LBB20_2 ; CHECK-NEXT: jne LBB20_2
; CHECK-NEXT: ## BB#1: ## %sw.bb4.i ; CHECK-NEXT: ## BB#1: ## %sw.bb4.i
; CHECK-NEXT: ## InlineAsm Start ; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: frndint ; CHECK-NEXT: frndint
; CHECK-NEXT: ## InlineAsm End ; CHECK-NEXT: ## InlineAsm End
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/lea-opt-cse1.ll

Show All 13 Lines
; X64-NEXT: movl %eax, 12(%rdi) ; X64-NEXT: movl %eax, 12(%rdi)
; X64-NEXT: leal 1(%rcx,%rdx), %eax ; X64-NEXT: leal 1(%rcx,%rdx), %eax
; X64-NEXT: movl %eax, 16(%rdi) ; X64-NEXT: movl %eax, 16(%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_func: ; X86-LABEL: test_func:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl (%eax), %ecx ; X86-NEXT: movl (%eax), %ecx
; X86-NEXT: movl 16(%eax), %edx ; X86-NEXT: movl 16(%eax), %edx
; X86-NEXT: leal 1(%ecx,%edx), %esi ; X86-NEXT: leal 1(%ecx,%edx), %esi
; X86-NEXT: addl %edx, %ecx ; X86-NEXT: addl %edx, %ecx
; X86-NEXT: movl %esi, 12(%eax) ; X86-NEXT: movl %esi, 12(%eax)
; X86-NEXT: leal 1(%edx,%ecx), %ecx ; X86-NEXT: leal 1(%edx,%ecx), %ecx
Show All 16 Lines

llvm/trunk/test/CodeGen/X86/lea-opt-cse2.ll

Show All 19 Lines
; X64-NEXT: addl %ecx, %eax ; X64-NEXT: addl %ecx, %eax
; X64-NEXT: leal 1(%rcx,%rax), %eax ; X64-NEXT: leal 1(%rcx,%rax), %eax
; X64-NEXT: movl %eax, 16(%rdi) ; X64-NEXT: movl %eax, 16(%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: foo: ; X86-LABEL: foo:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_offset %esi, -12 ; X86-NEXT: .cfi_offset %esi, -12
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_offset %edi, -8 ; X86-NEXT: .cfi_offset %edi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .p2align 4, 0x90
; X86-NEXT: .LBB0_1: # %loop ; X86-NEXT: .LBB0_1: # %loop
; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl (%eax), %edx ; X86-NEXT: movl (%eax), %edx
; X86-NEXT: movl 16(%eax), %esi ; X86-NEXT: movl 16(%eax), %esi
Show All 33 Lines

llvm/trunk/test/CodeGen/X86/lea-opt-cse3.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; X64-NEXT: imull %eax, %ecx ; X64-NEXT: imull %eax, %ecx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl %ecx, %eax
; X64-NEXT: .LBB2_2: # %exit ; X64-NEXT: .LBB2_2: # %exit
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: foo1_mult_basic_blocks: ; X86-LABEL: foo1_mult_basic_blocks:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: leal 4(%esi,%edx,4), %ecx ; X86-NEXT: leal 4(%esi,%edx,4), %ecx
; X86-NEXT: xorl %eax, %eax ; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $10, %ecx ; X86-NEXT: cmpl $10, %ecx
; X86-NEXT: je .LBB2_2 ; X86-NEXT: je .LBB2_2
; X86-NEXT: # BB#1: # %mid ; X86-NEXT: # BB#1: # %mid
Show All 35 Lines
; X64-NEXT: imull %eax, %ecx ; X64-NEXT: imull %eax, %ecx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl %ecx, %eax
; X64-NEXT: .LBB3_2: # %exit ; X64-NEXT: .LBB3_2: # %exit
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: foo1_mult_basic_blocks_illegal_scale: ; X86-LABEL: foo1_mult_basic_blocks_illegal_scale:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: leal 4(%esi,%edx,2), %ecx ; X86-NEXT: leal 4(%esi,%edx,2), %ecx
; X86-NEXT: xorl %eax, %eax ; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $10, %ecx ; X86-NEXT: cmpl $10, %ecx
; X86-NEXT: je .LBB3_2 ; X86-NEXT: je .LBB3_2
; X86-NEXT: # BB#1: # %mid ; X86-NEXT: # BB#1: # %mid
Show All 22 Lines

llvm/trunk/test/CodeGen/X86/lea-opt-cse4.ll

Show All 16 Lines
; X64-NEXT: movl %ecx, 12(%rdi) ; X64-NEXT: movl %ecx, 12(%rdi)
; X64-NEXT: leal 1(%rax,%rdx), %eax ; X64-NEXT: leal 1(%rax,%rdx), %eax
; X64-NEXT: movl %eax, 16(%rdi) ; X64-NEXT: movl %eax, 16(%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: foo: ; X86-LABEL: foo:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl 16(%eax), %ecx ; X86-NEXT: movl 16(%eax), %ecx
; X86-NEXT: movl (%eax), %edx ; X86-NEXT: movl (%eax), %edx
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edx
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edx
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edx
; X86-NEXT: leal 1(%ecx,%edx), %esi ; X86-NEXT: leal 1(%ecx,%edx), %esi
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; X64-NEXT: addl %eax, %ecx ; X64-NEXT: addl %eax, %ecx
; X64-NEXT: addl %eax, %ecx ; X64-NEXT: addl %eax, %ecx
; X64-NEXT: movl %ecx, 16(%rdi) ; X64-NEXT: movl %ecx, 16(%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: foo_loop: ; X86-LABEL: foo_loop:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: .Lcfi4:
; X86-NEXT: .cfi_offset %esi, -12 ; X86-NEXT: .cfi_offset %esi, -12
; X86-NEXT: .Lcfi5:
; X86-NEXT: .cfi_offset %edi, -8 ; X86-NEXT: .cfi_offset %edi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .p2align 4, 0x90
; X86-NEXT: .LBB1_1: # %loop ; X86-NEXT: .LBB1_1: # %loop
; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: movl (%eax), %esi ; X86-NEXT: movl (%eax), %esi
; X86-NEXT: movl 16(%eax), %ecx ; X86-NEXT: movl 16(%eax), %ecx
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: retl
ret i64 %shr ret i64 %shr
} }
; PR14668 ; PR14668
define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) { define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 12 ; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 20 ; CHECK-NEXT: .cfi_def_cfa_offset 20
; CHECK-NEXT: .Lcfi4:
; CHECK-NEXT: .cfi_offset %esi, -20 ; CHECK-NEXT: .cfi_offset %esi, -20
; CHECK-NEXT: .Lcfi5:
; CHECK-NEXT: .cfi_offset %edi, -16 ; CHECK-NEXT: .cfi_offset %edi, -16
; CHECK-NEXT: .Lcfi6:
; CHECK-NEXT: .cfi_offset %ebx, -12 ; CHECK-NEXT: .cfi_offset %ebx, -12
; CHECK-NEXT: .Lcfi7:
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %ebx, %edi ; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: shll %cl, %edi ; CHECK-NEXT: shll %cl, %edi
; CHECK-NEXT: shldl %cl, %ebx, %esi ; CHECK-NEXT: shldl %cl, %ebx, %esi
Show All 28 Lines; CHECK-NEXT: retl $4
ret <2 x i64> %shl ret <2 x i64> %shl
} }
; PR16108 ; PR16108
define i32 @test6() { define i32 @test6() {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .Lcfi8:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi9:
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .Lcfi10:
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp ; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: shldl $32, %eax, %ecx ; CHECK-NEXT: shldl $32, %eax, %ecx
Show All 38 Lines

llvm/trunk/test/CodeGen/X86/live-out-reg-info.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; Make sure dagcombine doesn't eliminate the comparison due ; Make sure dagcombine doesn't eliminate the comparison due
; to an off-by-one bug with computeKnownBits information. ; to an off-by-one bug with computeKnownBits information.
declare void @qux() declare void @qux()
define void @foo(i32 %a) { define void @foo(i32 %a) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: shrl $23, %edi ; CHECK-NEXT: shrl $23, %edi
; CHECK-NEXT: btl $8, %edi ; CHECK-NEXT: btl $8, %edi
; CHECK-NEXT: jb .LBB0_2 ; CHECK-NEXT: jb .LBB0_2
; CHECK-NEXT: # BB#1: # %true ; CHECK-NEXT: # BB#1: # %true
; CHECK-NEXT: callq qux ; CHECK-NEXT: callq qux
; CHECK-NEXT: .LBB0_2: # %false ; CHECK-NEXT: .LBB0_2: # %false
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
Show All 14 Lines

llvm/trunk/test/CodeGen/X86/load-combine.ll

Show First 20 Lines • Show All 354 Lines • ▼ Show 20 Lines
; i8* p; ; i8* p;
; i32 x = (i32) p[1] ; i32 x = (i32) p[1]
; res = ((i32) p[0] << 24) | (x << 16) | ((i32) p[2] << 8) | (i32) p[3] ; res = ((i32) p[0] << 24) | (x << 16) | ((i32) p[2] << 8) | (i32) p[3]
; x | res ; x | res
define i32 @load_i32_by_i8_bswap_uses(i32* %arg) { define i32 @load_i32_by_i8_bswap_uses(i32* %arg) {
; CHECK-LABEL: load_i32_by_i8_bswap_uses: ; CHECK-LABEL: load_i32_by_i8_bswap_uses:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movzbl (%eax), %ecx ; CHECK-NEXT: movzbl (%eax), %ecx
; CHECK-NEXT: shll $24, %ecx ; CHECK-NEXT: shll $24, %ecx
; CHECK-NEXT: movzbl 1(%eax), %edx ; CHECK-NEXT: movzbl 1(%eax), %edx
; CHECK-NEXT: movl %edx, %esi ; CHECK-NEXT: movl %edx, %esi
; CHECK-NEXT: shll $16, %esi ; CHECK-NEXT: shll $16, %esi
; CHECK-NEXT: orl %ecx, %esi ; CHECK-NEXT: orl %ecx, %esi
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; res1 = ((i32) p[0] << 24) | ((i32) p[1] << 16) ; res1 = ((i32) p[0] << 24) | ((i32) p[1] << 16)
; *q = 0; ; *q = 0;
; res2 = ((i32) p[2] << 8) | (i32) p[3] ; res2 = ((i32) p[2] << 8) | (i32) p[3]
; res1 | res2 ; res1 | res2
define i32 @load_i32_by_i8_bswap_store_in_between(i32* %arg, i32* %arg1) { define i32 @load_i32_by_i8_bswap_store_in_between(i32* %arg, i32* %arg1) {
; CHECK-LABEL: load_i32_by_i8_bswap_store_in_between: ; CHECK-LABEL: load_i32_by_i8_bswap_store_in_between:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movzbl (%ecx), %edx ; CHECK-NEXT: movzbl (%ecx), %edx
; CHECK-NEXT: shll $24, %edx ; CHECK-NEXT: shll $24, %edx
; CHECK-NEXT: movzbl 1(%ecx), %esi ; CHECK-NEXT: movzbl 1(%ecx), %esi
; CHECK-NEXT: movl $0, (%eax) ; CHECK-NEXT: movl $0, (%eax)
; CHECK-NEXT: shll $16, %esi ; CHECK-NEXT: shll $16, %esi
▲ Show 20 Lines • Show All 819 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll

Show First 20 Lines • Show All 1,679 Lines • ▼ Show 20 Lines
; KNL_64-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2} ; KNL_64-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2}
; KNL_64-NEXT: vmovdqa64 %zmm3, %zmm0 ; KNL_64-NEXT: vmovdqa64 %zmm3, %zmm0
; KNL_64-NEXT: vmovdqa64 %zmm4, %zmm1 ; KNL_64-NEXT: vmovdqa64 %zmm4, %zmm1
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test_gather_16i64: ; KNL_32-LABEL: test_gather_16i64:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp ; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi0:
; KNL_32-NEXT: .cfi_def_cfa_offset 8 ; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi1:
; KNL_32-NEXT: .cfi_offset %ebp, -8 ; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp ; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi2:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp ; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp ; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1 ; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2 ; KNL_32-NEXT: kshiftrw $8, %k1, %k2
Show All 15 Lines
; SKX-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2} ; SKX-NEXT: vpgatherqq (,%zmm1), %zmm4 {%k2}
; SKX-NEXT: vmovdqa64 %zmm3, %zmm0 ; SKX-NEXT: vmovdqa64 %zmm3, %zmm0
; SKX-NEXT: vmovdqa64 %zmm4, %zmm1 ; SKX-NEXT: vmovdqa64 %zmm4, %zmm1
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; SKX_32-LABEL: test_gather_16i64: ; SKX_32-LABEL: test_gather_16i64:
; SKX_32: # BB#0: ; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp ; SKX_32-NEXT: pushl %ebp
; SKX_32-NEXT: .Lcfi1:
; SKX_32-NEXT: .cfi_def_cfa_offset 8 ; SKX_32-NEXT: .cfi_def_cfa_offset 8
; SKX_32-NEXT: .Lcfi2:
; SKX_32-NEXT: .cfi_offset %ebp, -8 ; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp ; SKX_32-NEXT: movl %esp, %ebp
; SKX_32-NEXT: .Lcfi3:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp ; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp ; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp ; SKX_32-NEXT: subl $64, %esp
; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1
; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1 ; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1
; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; SKX_32-NEXT: vmovdqa64 8(%ebp), %zmm1 ; SKX_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; SKX_32-NEXT: kshiftrw $8, %k1, %k2 ; SKX_32-NEXT: kshiftrw $8, %k1, %k2
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; KNL_64-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2} ; KNL_64-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2}
; KNL_64-NEXT: vmovapd %zmm3, %zmm0 ; KNL_64-NEXT: vmovapd %zmm3, %zmm0
; KNL_64-NEXT: vmovapd %zmm4, %zmm1 ; KNL_64-NEXT: vmovapd %zmm4, %zmm1
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test_gather_16f64: ; KNL_32-LABEL: test_gather_16f64:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp ; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi3:
; KNL_32-NEXT: .cfi_def_cfa_offset 8 ; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi4:
; KNL_32-NEXT: .cfi_offset %ebp, -8 ; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp ; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi5:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp ; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp ; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1 ; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2 ; KNL_32-NEXT: kshiftrw $8, %k1, %k2
Show All 15 Lines
; SKX-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2} ; SKX-NEXT: vgatherqpd (,%zmm1), %zmm4 {%k2}
; SKX-NEXT: vmovapd %zmm3, %zmm0 ; SKX-NEXT: vmovapd %zmm3, %zmm0
; SKX-NEXT: vmovapd %zmm4, %zmm1 ; SKX-NEXT: vmovapd %zmm4, %zmm1
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; SKX_32-LABEL: test_gather_16f64: ; SKX_32-LABEL: test_gather_16f64:
; SKX_32: # BB#0: ; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp ; SKX_32-NEXT: pushl %ebp
; SKX_32-NEXT: .Lcfi4:
; SKX_32-NEXT: .cfi_def_cfa_offset 8 ; SKX_32-NEXT: .cfi_def_cfa_offset 8
; SKX_32-NEXT: .Lcfi5:
; SKX_32-NEXT: .cfi_offset %ebp, -8 ; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp ; SKX_32-NEXT: movl %esp, %ebp
; SKX_32-NEXT: .Lcfi6:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp ; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp ; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp ; SKX_32-NEXT: subl $64, %esp
; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1
; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1 ; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1
; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; SKX_32-NEXT: vmovapd 8(%ebp), %zmm1 ; SKX_32-NEXT: vmovapd 8(%ebp), %zmm1
; SKX_32-NEXT: kshiftrw $8, %k1, %k2 ; SKX_32-NEXT: kshiftrw $8, %k1, %k2
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; KNL_64-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1} ; KNL_64-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1}
; KNL_64-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2} ; KNL_64-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2}
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test_scatter_16i64: ; KNL_32-LABEL: test_scatter_16i64:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp ; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi6:
; KNL_32-NEXT: .cfi_def_cfa_offset 8 ; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi7:
; KNL_32-NEXT: .cfi_offset %ebp, -8 ; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp ; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi8:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp ; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp ; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1 ; KNL_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2 ; KNL_32-NEXT: kshiftrw $8, %k1, %k2
Show All 14 Lines
; SKX-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1} ; SKX-NEXT: vpscatterqq %zmm3, (,%zmm0) {%k1}
; SKX-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2} ; SKX-NEXT: vpscatterqq %zmm4, (,%zmm1) {%k2}
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; SKX_32-LABEL: test_scatter_16i64: ; SKX_32-LABEL: test_scatter_16i64:
; SKX_32: # BB#0: ; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp ; SKX_32-NEXT: pushl %ebp
; SKX_32-NEXT: .Lcfi7:
; SKX_32-NEXT: .cfi_def_cfa_offset 8 ; SKX_32-NEXT: .cfi_def_cfa_offset 8
; SKX_32-NEXT: .Lcfi8:
; SKX_32-NEXT: .cfi_offset %ebp, -8 ; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp ; SKX_32-NEXT: movl %esp, %ebp
; SKX_32-NEXT: .Lcfi9:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp ; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp ; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp ; SKX_32-NEXT: subl $64, %esp
; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1
; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1 ; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1
; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; SKX_32-NEXT: vmovdqa64 8(%ebp), %zmm1 ; SKX_32-NEXT: vmovdqa64 8(%ebp), %zmm1
; SKX_32-NEXT: kshiftrw $8, %k1, %k2 ; SKX_32-NEXT: kshiftrw $8, %k1, %k2
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; KNL_64-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1} ; KNL_64-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1}
; KNL_64-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2} ; KNL_64-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2}
; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: vzeroupper
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test_scatter_16f64: ; KNL_32-LABEL: test_scatter_16f64:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp ; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi9:
; KNL_32-NEXT: .cfi_def_cfa_offset 8 ; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi10:
; KNL_32-NEXT: .cfi_offset %ebp, -8 ; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp ; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi11:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp ; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp ; KNL_32-NEXT: subl $64, %esp
; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; KNL_32-NEXT: vpmovsxbd %xmm1, %zmm1
; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL_32-NEXT: vpslld $31, %zmm1, %zmm1
; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1 ; KNL_32-NEXT: vmovapd 8(%ebp), %zmm1
; KNL_32-NEXT: kshiftrw $8, %k1, %k2 ; KNL_32-NEXT: kshiftrw $8, %k1, %k2
Show All 14 Lines
; SKX-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1} ; SKX-NEXT: vscatterqpd %zmm3, (,%zmm0) {%k1}
; SKX-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2} ; SKX-NEXT: vscatterqpd %zmm4, (,%zmm1) {%k2}
; SKX-NEXT: vzeroupper ; SKX-NEXT: vzeroupper
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; SKX_32-LABEL: test_scatter_16f64: ; SKX_32-LABEL: test_scatter_16f64:
; SKX_32: # BB#0: ; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp ; SKX_32-NEXT: pushl %ebp
; SKX_32-NEXT: .Lcfi10:
; SKX_32-NEXT: .cfi_def_cfa_offset 8 ; SKX_32-NEXT: .cfi_def_cfa_offset 8
; SKX_32-NEXT: .Lcfi11:
; SKX_32-NEXT: .cfi_offset %ebp, -8 ; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp ; SKX_32-NEXT: movl %esp, %ebp
; SKX_32-NEXT: .Lcfi12:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp ; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp ; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp ; SKX_32-NEXT: subl $64, %esp
; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1 ; SKX_32-NEXT: vpmovsxbd %xmm1, %zmm1
; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1 ; SKX_32-NEXT: vpslld $31, %zmm1, %zmm1
; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1 ; SKX_32-NEXT: vptestmd %zmm1, %zmm1, %k1
; SKX_32-NEXT: vmovapd 8(%ebp), %zmm1 ; SKX_32-NEXT: vmovapd 8(%ebp), %zmm1
; SKX_32-NEXT: kshiftrw $8, %k1, %k2 ; SKX_32-NEXT: kshiftrw $8, %k1, %k2
Show All 22 Lines
; KNL_64-NEXT: vpgatherqq (,%zmm0), %zmm1 {%k1} ; KNL_64-NEXT: vpgatherqq (,%zmm0), %zmm1 {%k1}
; KNL_64-NEXT: vpaddq %ymm1, %ymm1, %ymm0 ; KNL_64-NEXT: vpaddq %ymm1, %ymm1, %ymm0
; KNL_64-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; KNL_64-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test_pr28312: ; KNL_32-LABEL: test_pr28312:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp ; KNL_32-NEXT: pushl %ebp
; KNL_32-NEXT: .Lcfi12:
; KNL_32-NEXT: .cfi_def_cfa_offset 8 ; KNL_32-NEXT: .cfi_def_cfa_offset 8
; KNL_32-NEXT: .Lcfi13:
; KNL_32-NEXT: .cfi_offset %ebp, -8 ; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp ; KNL_32-NEXT: movl %esp, %ebp
; KNL_32-NEXT: .Lcfi14:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-32, %esp ; KNL_32-NEXT: andl $-32, %esp
; KNL_32-NEXT: subl $32, %esp ; KNL_32-NEXT: subl $32, %esp
; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1
; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1
; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1 ; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1
; KNL_32-NEXT: vmovdqa %ymm1, %ymm1 ; KNL_32-NEXT: vmovdqa %ymm1, %ymm1
Show All 14 Lines
; SKX-NEXT: vpgatherqq (,%ymm0), %ymm1 {%k1} ; SKX-NEXT: vpgatherqq (,%ymm0), %ymm1 {%k1}
; SKX-NEXT: vpaddq %ymm1, %ymm1, %ymm0 ; SKX-NEXT: vpaddq %ymm1, %ymm1, %ymm0
; SKX-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; SKX-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; SKX_32-LABEL: test_pr28312: ; SKX_32-LABEL: test_pr28312:
; SKX_32: # BB#0: ; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp ; SKX_32-NEXT: pushl %ebp
; SKX_32-NEXT: .Lcfi13:
; SKX_32-NEXT: .cfi_def_cfa_offset 8 ; SKX_32-NEXT: .cfi_def_cfa_offset 8
; SKX_32-NEXT: .Lcfi14:
; SKX_32-NEXT: .cfi_offset %ebp, -8 ; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp ; SKX_32-NEXT: movl %esp, %ebp
; SKX_32-NEXT: .Lcfi15:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp ; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-32, %esp ; SKX_32-NEXT: andl $-32, %esp
; SKX_32-NEXT: subl $32, %esp ; SKX_32-NEXT: subl $32, %esp
; SKX_32-NEXT: vpslld $31, %xmm1, %xmm1 ; SKX_32-NEXT: vpslld $31, %xmm1, %xmm1
; SKX_32-NEXT: vptestmd %xmm1, %xmm1, %k1 ; SKX_32-NEXT: vptestmd %xmm1, %xmm1, %k1
; SKX_32-NEXT: vpgatherdq (,%xmm0), %ymm1 {%k1} ; SKX_32-NEXT: vpgatherdq (,%xmm0), %ymm1 {%k1}
; SKX_32-NEXT: vpaddq %ymm1, %ymm1, %ymm0 ; SKX_32-NEXT: vpaddq %ymm1, %ymm1, %ymm0
; SKX_32-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; SKX_32-NEXT: vpaddq %ymm0, %ymm1, %ymm0
Show All 11 Lines

llvm/trunk/test/CodeGen/X86/memset-nonzero.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1) %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1)
ret void ret void
} }
define void @memset_256_nonzero_bytes(i8* %x) { define void @memset_256_nonzero_bytes(i8* %x) {
; SSE-LABEL: memset_256_nonzero_bytes: ; SSE-LABEL: memset_256_nonzero_bytes:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: pushq %rax ; SSE-NEXT: pushq %rax
; SSE-NEXT: .Lcfi0:
; SSE-NEXT: .cfi_def_cfa_offset 16 ; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: movl $42, %esi ; SSE-NEXT: movl $42, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100 ; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: callq memset ; SSE-NEXT: callq memset
; SSE-NEXT: popq %rax ; SSE-NEXT: popq %rax
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; SSE2FAST-LABEL: memset_256_nonzero_bytes: ; SSE2FAST-LABEL: memset_256_nonzero_bytes:
▲ Show 20 Lines • Show All 306 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; AVX-LABEL: merge_2i64_i64_12: ; AVX-LABEL: merge_2i64_i64_12:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_2i64_i64_12: ; X32-SSE1-LABEL: merge_2i64_i64_12:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi0:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi1:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi2:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi3:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 16(%ecx), %edi ; X32-SSE1-NEXT: movl 16(%ecx), %edi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
▲ Show 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
; AVX-LABEL: merge_4i32_i32_23u5: ; AVX-LABEL: merge_4i32_i32_23u5:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5: ; X32-SSE1-LABEL: merge_4i32_i32_23u5:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi4:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: .Lcfi5:
; X32-SSE1-NEXT: .cfi_offset %esi, -8 ; X32-SSE1-NEXT: .cfi_offset %esi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
Show All 29 Lines
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: incl 8(%rdi) ; AVX-NEXT: incl 8(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc2: ; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc2:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi6:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi7:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi8:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi9:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%edx), %edi ; X32-SSE1-NEXT: leal 1(%edx), %edi
; X32-SSE1-NEXT: movl %edi, 8(%ecx) ; X32-SSE1-NEXT: movl %edi, 8(%ecx)
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
Show All 35 Lines
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: incl 12(%rdi) ; AVX-NEXT: incl 12(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc3: ; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc3:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi10:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi11:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi12:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi13:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%esi), %edi ; X32-SSE1-NEXT: leal 1(%esi), %edi
; X32-SSE1-NEXT: movl %edi, 12(%ecx) ; X32-SSE1-NEXT: movl %edi, 12(%ecx)
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: incl 16(%rdi) ; AVX-NEXT: incl 16(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc4: ; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc4:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi14:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi15:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi16:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi17:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 16(%ecx), %edx ; X32-SSE1-NEXT: movl 16(%ecx), %edx
; X32-SSE1-NEXT: movl 20(%ecx), %esi ; X32-SSE1-NEXT: movl 20(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%edx), %edi ; X32-SSE1-NEXT: leal 1(%edx), %edi
; X32-SSE1-NEXT: movl %edi, 16(%ecx) ; X32-SSE1-NEXT: movl %edi, 16(%ecx)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
Show All 32 Lines
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: incl 20(%rdi) ; AVX-NEXT: incl 20(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc5: ; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc5:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi18:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi19:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi20:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi21:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 16(%ecx), %edx ; X32-SSE1-NEXT: movl 16(%ecx), %edx
; X32-SSE1-NEXT: movl 20(%ecx), %esi ; X32-SSE1-NEXT: movl 20(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%esi), %edi ; X32-SSE1-NEXT: leal 1(%esi), %edi
; X32-SSE1-NEXT: movl %edi, 20(%ecx) ; X32-SSE1-NEXT: movl %edi, 20(%ecx)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
Show All 30 Lines
; AVX-LABEL: merge_8i16_i16_23u567u9: ; AVX-LABEL: merge_8i16_i16_23u567u9:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 4(%rdi), %xmm0 ; AVX-NEXT: vmovups 4(%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_8i16_i16_23u567u9: ; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi22:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi23:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi24:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi25:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 4(%ecx), %edx ; X32-SSE1-NEXT: movl 4(%ecx), %edx
; X32-SSE1-NEXT: movl 10(%ecx), %esi ; X32-SSE1-NEXT: movl 10(%ecx), %esi
; X32-SSE1-NEXT: movzwl 14(%ecx), %edi ; X32-SSE1-NEXT: movzwl 14(%ecx), %edi
; X32-SSE1-NEXT: movzwl 18(%ecx), %ecx ; X32-SSE1-NEXT: movzwl 18(%ecx), %ecx
; X32-SSE1-NEXT: movw %di, 10(%eax) ; X32-SSE1-NEXT: movw %di, 10(%eax)
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; AVX-LABEL: merge_16i8_i8_01u3456789ABCDuF: ; AVX-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups (%rdi), %xmm0 ; AVX-NEXT: vmovups (%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF: ; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebp ; X32-SSE1-NEXT: pushl %ebp
; X32-SSE1-NEXT: .Lcfi26:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %ebx ; X32-SSE1-NEXT: pushl %ebx
; X32-SSE1-NEXT: .Lcfi27:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi28:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 16 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 16
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi29:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 20 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 20
; X32-SSE1-NEXT: .Lcfi30:
; X32-SSE1-NEXT: .cfi_offset %esi, -20 ; X32-SSE1-NEXT: .cfi_offset %esi, -20
; X32-SSE1-NEXT: .Lcfi31:
; X32-SSE1-NEXT: .cfi_offset %edi, -16 ; X32-SSE1-NEXT: .cfi_offset %edi, -16
; X32-SSE1-NEXT: .Lcfi32:
; X32-SSE1-NEXT: .cfi_offset %ebx, -12 ; X32-SSE1-NEXT: .cfi_offset %ebx, -12
; X32-SSE1-NEXT: .Lcfi33:
; X32-SSE1-NEXT: .cfi_offset %ebp, -8 ; X32-SSE1-NEXT: .cfi_offset %ebp, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movzwl (%ecx), %ebp ; X32-SSE1-NEXT: movzwl (%ecx), %ebp
; X32-SSE1-NEXT: movl 3(%ecx), %esi ; X32-SSE1-NEXT: movl 3(%ecx), %esi
; X32-SSE1-NEXT: movl 7(%ecx), %edi ; X32-SSE1-NEXT: movl 7(%ecx), %edi
; X32-SSE1-NEXT: movzwl 11(%ecx), %ebx ; X32-SSE1-NEXT: movzwl 11(%ecx), %ebx
; X32-SSE1-NEXT: movb 13(%ecx), %dl ; X32-SSE1-NEXT: movb 13(%ecx), %dl
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_2i64_i64_12_volatile: ; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi34:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi35:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi36:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi37:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 16(%ecx), %edi ; X32-SSE1-NEXT: movl 16(%ecx), %edi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/movpc32-check.ll

Show All 27 Lines
!7 = !{i32 2, !"Dwarf Version", i32 4} !7 = !{i32 2, !"Dwarf Version", i32 4}
!8 = !{i32 2, !"Debug Info Version", i32 3} !8 = !{i32 2, !"Debug Info Version", i32 3}
!9 = !{i32 1, !"PIC Level", i32 2} !9 = !{i32 1, !"PIC Level", i32 2}
!10 = !{!"clang version 3.8.0 (http://llvm.org/git/clang.git 3490ab8630d5643f71f1f04e46984f05b27b8d67) (http://llvm.org/git/llvm.git d2643e2ff955ed234944fe3c6b4ffc1250085843)"} !10 = !{!"clang version 3.8.0 (http://llvm.org/git/clang.git 3490ab8630d5643f71f1f04e46984f05b27b8d67) (http://llvm.org/git/llvm.git d2643e2ff955ed234944fe3c6b4ffc1250085843)"}
!11 = !DILocation(line: 4, column: 3, scope: !4) !11 = !DILocation(line: 4, column: 3, scope: !4)
!12 = !DILocation(line: 5, column: 1, scope: !4) !12 = !DILocation(line: 5, column: 1, scope: !4)
; CHECK: calll .L0$pb ; CHECK: calll .L0$pb
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_adjust_cfa_offset 4 ; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: .L0$pb: ; CHECK-NEXT: .L0$pb:
; CHECK-NEXT: popl ; CHECK-NEXT: popl
; CHECK-NEXT: .Lcfi4:
; CHECK-NEXT: .cfi_adjust_cfa_offset -4 ; CHECK-NEXT: .cfi_adjust_cfa_offset -4

llvm/trunk/test/CodeGen/X86/mul-constant-result.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; Incremental updates of the instruction depths should be enough for this test ; Incremental updates of the instruction depths should be enough for this test
; case. ; case.
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell -machine-combiner-inc-threshold=0| FileCheck %s --check-prefix=X64-HSW ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell -machine-combiner-inc-threshold=0| FileCheck %s --check-prefix=X64-HSW
; Function Attrs: norecurse nounwind readnone uwtable ; Function Attrs: norecurse nounwind readnone uwtable
define i32 @mult(i32, i32) local_unnamed_addr #0 { define i32 @mult(i32, i32) local_unnamed_addr #0 {
; X86-LABEL: mult: ; X86-LABEL: mult:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: cmpl $1, %edx ; X86-NEXT: cmpl $1, %edx
; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $1, %eax
; X86-NEXT: movl $1, %esi ; X86-NEXT: movl $1, %esi
; X86-NEXT: jg .LBB0_2 ; X86-NEXT: jg .LBB0_2
; X86-NEXT: # BB#1: ; X86-NEXT: # BB#1:
; X86-NEXT: movl %edx, %esi ; X86-NEXT: movl %edx, %esi
▲ Show 20 Lines • Show All 499 Lines • ▼ Show 20 Lines; <label>:70: ; preds = %2, %69, %67, %65, %63, %61, %59, %57, %55, %53, %51, %49, %47, %45, %43, %41, %39, %37, %35, %33, %31, %29, %27, %25, %23, %21, %19, %17, %15, %13, %11, %9, %7
ret i32 %71 ret i32 %71
} }
; Function Attrs: norecurse nounwind readnone uwtable ; Function Attrs: norecurse nounwind readnone uwtable
define i32 @foo() local_unnamed_addr #0 { define i32 @foo() local_unnamed_addr #0 {
; X86-LABEL: foo: ; X86-LABEL: foo:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi4:
; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: .cfi_def_cfa_offset 16
; X86-NEXT: .Lcfi5:
; X86-NEXT: .cfi_offset %esi, -16 ; X86-NEXT: .cfi_offset %esi, -16
; X86-NEXT: .Lcfi6:
; X86-NEXT: .cfi_offset %edi, -12 ; X86-NEXT: .cfi_offset %edi, -12
; X86-NEXT: .Lcfi7:
; X86-NEXT: .cfi_offset %ebx, -8 ; X86-NEXT: .cfi_offset %ebx, -8
; X86-NEXT: pushl $0 ; X86-NEXT: pushl $0
; X86-NEXT: .Lcfi8:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $1 ; X86-NEXT: pushl $1
; X86-NEXT: .Lcfi9:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi10:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: xorl $1, %esi ; X86-NEXT: xorl $1, %esi
; X86-NEXT: pushl $1 ; X86-NEXT: pushl $1
; X86-NEXT: .Lcfi11:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $2 ; X86-NEXT: pushl $2
; X86-NEXT: .Lcfi12:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi13:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $2, %edi ; X86-NEXT: xorl $2, %edi
; X86-NEXT: pushl $1 ; X86-NEXT: pushl $1
; X86-NEXT: .Lcfi14:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $3 ; X86-NEXT: pushl $3
; X86-NEXT: .Lcfi15:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi16:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $3, %ebx ; X86-NEXT: xorl $3, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $2 ; X86-NEXT: pushl $2
; X86-NEXT: .Lcfi17:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $4 ; X86-NEXT: pushl $4
; X86-NEXT: .Lcfi18:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi19:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $4, %edi ; X86-NEXT: xorl $4, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $2 ; X86-NEXT: pushl $2
; X86-NEXT: .Lcfi20:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $5 ; X86-NEXT: pushl $5
; X86-NEXT: .Lcfi21:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi22:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $5, %ebx ; X86-NEXT: xorl $5, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $3 ; X86-NEXT: pushl $3
; X86-NEXT: .Lcfi23:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $6 ; X86-NEXT: pushl $6
; X86-NEXT: .Lcfi24:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi25:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $6, %edi ; X86-NEXT: xorl $6, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $3 ; X86-NEXT: pushl $3
; X86-NEXT: .Lcfi26:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $7 ; X86-NEXT: pushl $7
; X86-NEXT: .Lcfi27:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi28:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $7, %ebx ; X86-NEXT: xorl $7, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $4 ; X86-NEXT: pushl $4
; X86-NEXT: .Lcfi29:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $8 ; X86-NEXT: pushl $8
; X86-NEXT: .Lcfi30:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi31:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $8, %edi ; X86-NEXT: xorl $8, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $4 ; X86-NEXT: pushl $4
; X86-NEXT: .Lcfi32:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $9 ; X86-NEXT: pushl $9
; X86-NEXT: .Lcfi33:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi34:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $9, %ebx ; X86-NEXT: xorl $9, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $5 ; X86-NEXT: pushl $5
; X86-NEXT: .Lcfi35:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $10 ; X86-NEXT: pushl $10
; X86-NEXT: .Lcfi36:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi37:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $10, %edi ; X86-NEXT: xorl $10, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $5 ; X86-NEXT: pushl $5
; X86-NEXT: .Lcfi38:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $11 ; X86-NEXT: pushl $11
; X86-NEXT: .Lcfi39:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi40:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $11, %ebx ; X86-NEXT: xorl $11, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $6 ; X86-NEXT: pushl $6
; X86-NEXT: .Lcfi41:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $12 ; X86-NEXT: pushl $12
; X86-NEXT: .Lcfi42:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi43:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $12, %edi ; X86-NEXT: xorl $12, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $6 ; X86-NEXT: pushl $6
; X86-NEXT: .Lcfi44:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $13 ; X86-NEXT: pushl $13
; X86-NEXT: .Lcfi45:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi46:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $13, %ebx ; X86-NEXT: xorl $13, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $7 ; X86-NEXT: pushl $7
; X86-NEXT: .Lcfi47:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $14 ; X86-NEXT: pushl $14
; X86-NEXT: .Lcfi48:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi49:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $14, %edi ; X86-NEXT: xorl $14, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $7 ; X86-NEXT: pushl $7
; X86-NEXT: .Lcfi50:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $15 ; X86-NEXT: pushl $15
; X86-NEXT: .Lcfi51:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi52:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $15, %ebx ; X86-NEXT: xorl $15, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $8 ; X86-NEXT: pushl $8
; X86-NEXT: .Lcfi53:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $16 ; X86-NEXT: pushl $16
; X86-NEXT: .Lcfi54:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi55:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $16, %edi ; X86-NEXT: xorl $16, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $8 ; X86-NEXT: pushl $8
; X86-NEXT: .Lcfi56:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $17 ; X86-NEXT: pushl $17
; X86-NEXT: .Lcfi57:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi58:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $17, %ebx ; X86-NEXT: xorl $17, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $9 ; X86-NEXT: pushl $9
; X86-NEXT: .Lcfi59:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $18 ; X86-NEXT: pushl $18
; X86-NEXT: .Lcfi60:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi61:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $18, %edi ; X86-NEXT: xorl $18, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $9 ; X86-NEXT: pushl $9
; X86-NEXT: .Lcfi62:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $19 ; X86-NEXT: pushl $19
; X86-NEXT: .Lcfi63:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi64:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $19, %ebx ; X86-NEXT: xorl $19, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $10 ; X86-NEXT: pushl $10
; X86-NEXT: .Lcfi65:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $20 ; X86-NEXT: pushl $20
; X86-NEXT: .Lcfi66:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi67:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $20, %edi ; X86-NEXT: xorl $20, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $10 ; X86-NEXT: pushl $10
; X86-NEXT: .Lcfi68:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $21 ; X86-NEXT: pushl $21
; X86-NEXT: .Lcfi69:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi70:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $21, %ebx ; X86-NEXT: xorl $21, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $11 ; X86-NEXT: pushl $11
; X86-NEXT: .Lcfi71:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $22 ; X86-NEXT: pushl $22
; X86-NEXT: .Lcfi72:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi73:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $22, %edi ; X86-NEXT: xorl $22, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $11 ; X86-NEXT: pushl $11
; X86-NEXT: .Lcfi74:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $23 ; X86-NEXT: pushl $23
; X86-NEXT: .Lcfi75:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi76:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $23, %ebx ; X86-NEXT: xorl $23, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $12 ; X86-NEXT: pushl $12
; X86-NEXT: .Lcfi77:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $24 ; X86-NEXT: pushl $24
; X86-NEXT: .Lcfi78:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi79:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $24, %edi ; X86-NEXT: xorl $24, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $12 ; X86-NEXT: pushl $12
; X86-NEXT: .Lcfi80:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $25 ; X86-NEXT: pushl $25
; X86-NEXT: .Lcfi81:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi82:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $25, %ebx ; X86-NEXT: xorl $25, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $13 ; X86-NEXT: pushl $13
; X86-NEXT: .Lcfi83:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $26 ; X86-NEXT: pushl $26
; X86-NEXT: .Lcfi84:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi85:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $26, %edi ; X86-NEXT: xorl $26, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $13 ; X86-NEXT: pushl $13
; X86-NEXT: .Lcfi86:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $27 ; X86-NEXT: pushl $27
; X86-NEXT: .Lcfi87:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi88:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $27, %ebx ; X86-NEXT: xorl $27, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $14 ; X86-NEXT: pushl $14
; X86-NEXT: .Lcfi89:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $28 ; X86-NEXT: pushl $28
; X86-NEXT: .Lcfi90:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi91:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $28, %edi ; X86-NEXT: xorl $28, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $14 ; X86-NEXT: pushl $14
; X86-NEXT: .Lcfi92:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $29 ; X86-NEXT: pushl $29
; X86-NEXT: .Lcfi93:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi94:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $29, %ebx ; X86-NEXT: xorl $29, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: pushl $15 ; X86-NEXT: pushl $15
; X86-NEXT: .Lcfi95:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $30 ; X86-NEXT: pushl $30
; X86-NEXT: .Lcfi96:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi97:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: xorl $30, %edi ; X86-NEXT: xorl $30, %edi
; X86-NEXT: orl %ebx, %edi ; X86-NEXT: orl %ebx, %edi
; X86-NEXT: pushl $15 ; X86-NEXT: pushl $15
; X86-NEXT: .Lcfi98:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $31 ; X86-NEXT: pushl $31
; X86-NEXT: .Lcfi99:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi100:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: xorl $31, %ebx ; X86-NEXT: xorl $31, %ebx
; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %edi, %ebx
; X86-NEXT: orl %esi, %ebx ; X86-NEXT: orl %esi, %ebx
; X86-NEXT: pushl $16 ; X86-NEXT: pushl $16
; X86-NEXT: .Lcfi101:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $32 ; X86-NEXT: pushl $32
; X86-NEXT: .Lcfi102:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll mult ; X86-NEXT: calll mult
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .Lcfi103:
; X86-NEXT: .cfi_adjust_cfa_offset -8 ; X86-NEXT: .cfi_adjust_cfa_offset -8
; X86-NEXT: xorl $32, %eax ; X86-NEXT: xorl $32, %eax
; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: orl %ebx, %eax ; X86-NEXT: orl %ebx, %eax
; X86-NEXT: setne %cl ; X86-NEXT: setne %cl
; X86-NEXT: negl %ecx ; X86-NEXT: negl %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-HSW-LABEL: foo: ; X64-HSW-LABEL: foo:
; X64-HSW: # BB#0: ; X64-HSW: # BB#0:
; X64-HSW-NEXT: pushq %rbp ; X64-HSW-NEXT: pushq %rbp
; X64-HSW-NEXT: .Lcfi0:
; X64-HSW-NEXT: .cfi_def_cfa_offset 16 ; X64-HSW-NEXT: .cfi_def_cfa_offset 16
; X64-HSW-NEXT: pushq %r15 ; X64-HSW-NEXT: pushq %r15
; X64-HSW-NEXT: .Lcfi1:
; X64-HSW-NEXT: .cfi_def_cfa_offset 24 ; X64-HSW-NEXT: .cfi_def_cfa_offset 24
; X64-HSW-NEXT: pushq %r14 ; X64-HSW-NEXT: pushq %r14
; X64-HSW-NEXT: .Lcfi2:
; X64-HSW-NEXT: .cfi_def_cfa_offset 32 ; X64-HSW-NEXT: .cfi_def_cfa_offset 32
; X64-HSW-NEXT: pushq %rbx ; X64-HSW-NEXT: pushq %rbx
; X64-HSW-NEXT: .Lcfi3:
; X64-HSW-NEXT: .cfi_def_cfa_offset 40 ; X64-HSW-NEXT: .cfi_def_cfa_offset 40
; X64-HSW-NEXT: pushq %rax ; X64-HSW-NEXT: pushq %rax
; X64-HSW-NEXT: .Lcfi4:
; X64-HSW-NEXT: .cfi_def_cfa_offset 48 ; X64-HSW-NEXT: .cfi_def_cfa_offset 48
; X64-HSW-NEXT: .Lcfi5:
; X64-HSW-NEXT: .cfi_offset %rbx, -40 ; X64-HSW-NEXT: .cfi_offset %rbx, -40
; X64-HSW-NEXT: .Lcfi6:
; X64-HSW-NEXT: .cfi_offset %r14, -32 ; X64-HSW-NEXT: .cfi_offset %r14, -32
; X64-HSW-NEXT: .Lcfi7:
; X64-HSW-NEXT: .cfi_offset %r15, -24 ; X64-HSW-NEXT: .cfi_offset %r15, -24
; X64-HSW-NEXT: .Lcfi8:
; X64-HSW-NEXT: .cfi_offset %rbp, -16 ; X64-HSW-NEXT: .cfi_offset %rbp, -16
; X64-HSW-NEXT: movl $1, %edi ; X64-HSW-NEXT: movl $1, %edi
; X64-HSW-NEXT: xorl %esi, %esi ; X64-HSW-NEXT: xorl %esi, %esi
; X64-HSW-NEXT: callq mult ; X64-HSW-NEXT: callq mult
; X64-HSW-NEXT: movl %eax, %ebx ; X64-HSW-NEXT: movl %eax, %ebx
; X64-HSW-NEXT: xorl $1, %ebx ; X64-HSW-NEXT: xorl $1, %ebx
; X64-HSW-NEXT: movl $2, %edi ; X64-HSW-NEXT: movl $2, %edi
; X64-HSW-NEXT: movl $1, %esi ; X64-HSW-NEXT: movl $1, %esi
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llvm/trunk/test/CodeGen/X86/mul-i256.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i386-unknown | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @test(i256* %a, i256* %b, i256* %out) #0 { define void @test(i256* %a, i256* %b, i256* %out) #0 {
; X32-LABEL: test: ; X32-LABEL: test:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: andl $-8, %esp ; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $168, %esp ; X32-NEXT: subl $168, %esp
; X32-NEXT: .Lcfi3:
; X32-NEXT: .cfi_offset %esi, -20 ; X32-NEXT: .cfi_offset %esi, -20
; X32-NEXT: .Lcfi4:
; X32-NEXT: .cfi_offset %edi, -16 ; X32-NEXT: .cfi_offset %edi, -16
; X32-NEXT: .Lcfi5:
; X32-NEXT: .cfi_offset %ebx, -12 ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: movl 8(%ebp), %eax ; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: movl 16(%eax), %ecx ; X32-NEXT: movl 16(%eax), %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl 20(%eax), %ecx ; X32-NEXT: movl 20(%eax), %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl 24(%eax), %ecx ; X32-NEXT: movl 24(%eax), %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill ; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; X32-NEXT: popl %edi ; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test: ; X64-LABEL: test:
; X64: # BB#0: # %entry ; X64: # BB#0: # %entry
; X64-NEXT: pushq %r15 ; X64-NEXT: pushq %r15
; X64-NEXT: .Lcfi0:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: pushq %r14 ; X64-NEXT: pushq %r14
; X64-NEXT: .Lcfi1:
; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: .cfi_def_cfa_offset 24
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: .Lcfi2:
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
; X64-NEXT: .Lcfi3:
; X64-NEXT: .cfi_offset %rbx, -32 ; X64-NEXT: .cfi_offset %rbx, -32
; X64-NEXT: .Lcfi4:
; X64-NEXT: .cfi_offset %r14, -24 ; X64-NEXT: .cfi_offset %r14, -24
; X64-NEXT: .Lcfi5:
; X64-NEXT: .cfi_offset %r15, -16 ; X64-NEXT: .cfi_offset %r15, -16
; X64-NEXT: movq %rdx, %r9 ; X64-NEXT: movq %rdx, %r9
; X64-NEXT: movq (%rdi), %r11 ; X64-NEXT: movq (%rdi), %r11
; X64-NEXT: movq 8(%rdi), %r8 ; X64-NEXT: movq 8(%rdi), %r8
; X64-NEXT: movq 16(%rdi), %rbx ; X64-NEXT: movq 16(%rdi), %rbx
; X64-NEXT: movq 16(%rsi), %r10 ; X64-NEXT: movq 16(%rsi), %r10
; X64-NEXT: movq (%rsi), %rcx ; X64-NEXT: movq (%rsi), %rcx
; X64-NEXT: movq 8(%rsi), %r15 ; X64-NEXT: movq 8(%rsi), %r15
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll

; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
; Test the webkit_jscc calling convention. ; Test the webkit_jscc calling convention.
; One argument will be passed in register, the other will be pushed on the stack. ; One argument will be passed in register, the other will be pushed on the stack.
; Return value in $rax. ; Return value in $rax.
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen: ; CHECK-LABEL: jscall_patchpoint_codegen:
; CHECK: Lcfi
; CHECK: movq %r{{.+}}, (%rsp) ; CHECK: movq %r{{.+}}, (%rsp)
; CHECK: movq %r{{.+}}, %rax ; CHECK: movq %r{{.+}}, %rax
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: movabsq $-559038736, %r11 ; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
; CHECK: movq %rax, (%rsp) ; CHECK: movq %rax, (%rsp)
; CHECK: callq ; CHECK: callq
; FAST-LABEL: jscall_patchpoint_codegen: ; FAST-LABEL: jscall_patchpoint_codegen:
; FAST: Lcfi
; FAST: movq %r{{.+}}, (%rsp) ; FAST: movq %r{{.+}}, (%rsp)
; FAST: movq %r{{.+}}, %rax ; FAST: movq %r{{.+}}, %rax
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: movabsq $-559038736, %r11 ; FAST-NEXT: movabsq $-559038736, %r11
; FAST-NEXT: callq *%r11 ; FAST-NEXT: callq *%r11
; FAST: movq %rax, (%rsp) ; FAST: movq %rax, (%rsp)
; FAST: callq ; FAST: callq
%resolveCall2 = inttoptr i64 -559038736 to i8* %resolveCall2 = inttoptr i64 -559038736 to i8*
%result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
%resolveCall3 = inttoptr i64 -559038737 to i8* %resolveCall3 = inttoptr i64 -559038737 to i8*
tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveCall3, i32 2, i64 %p4, i64 %result) tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
ret void ret void
} }
; Test if the arguments are properly aligned and that we don't store undef arguments. ; Test if the arguments are properly aligned and that we don't store undef arguments.
define i64 @jscall_patchpoint_codegen2(i64 %callee) { define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen2: ; CHECK-LABEL: jscall_patchpoint_codegen2:
; CHECK: Lcfi
; CHECK: movq $6, 24(%rsp) ; CHECK: movq $6, 24(%rsp)
; CHECK-NEXT: movl $4, 16(%rsp) ; CHECK-NEXT: movl $4, 16(%rsp)
; CHECK-NEXT: movq $2, (%rsp) ; CHECK-NEXT: movq $2, (%rsp)
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: movabsq $-559038736, %r11 ; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
; FAST-LABEL: jscall_patchpoint_codegen2: ; FAST-LABEL: jscall_patchpoint_codegen2:
; FAST: Lcfi
; FAST: movq $2, (%rsp) ; FAST: movq $2, (%rsp)
; FAST-NEXT: movl $4, 16(%rsp) ; FAST-NEXT: movl $4, 16(%rsp)
; FAST-NEXT: movq $6, 24(%rsp) ; FAST-NEXT: movq $6, 24(%rsp)
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: movabsq $-559038736, %r11 ; FAST-NEXT: movabsq $-559038736, %r11
; FAST-NEXT: callq *%r11 ; FAST-NEXT: callq *%r11
%call = inttoptr i64 -559038736 to i8* %call = inttoptr i64 -559038736 to i8*
%result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
ret i64 %result ret i64 %result
} }
; Test if the arguments are properly aligned and that we don't store undef arguments. ; Test if the arguments are properly aligned and that we don't store undef arguments.
define i64 @jscall_patchpoint_codegen3(i64 %callee) { define i64 @jscall_patchpoint_codegen3(i64 %callee) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen3: ; CHECK-LABEL: jscall_patchpoint_codegen3:
; CHECK: Lcfi
; CHECK: movq $10, 48(%rsp) ; CHECK: movq $10, 48(%rsp)
; CHECK-NEXT: movl $8, 36(%rsp) ; CHECK-NEXT: movl $8, 36(%rsp)
; CHECK-NEXT: movq $6, 24(%rsp) ; CHECK-NEXT: movq $6, 24(%rsp)
; CHECK-NEXT: movl $4, 16(%rsp) ; CHECK-NEXT: movl $4, 16(%rsp)
; CHECK-NEXT: movq $2, (%rsp) ; CHECK-NEXT: movq $2, (%rsp)
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: movabsq $-559038736, %r11 ; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
; FAST-LABEL: jscall_patchpoint_codegen3: ; FAST-LABEL: jscall_patchpoint_codegen3:
; FAST: Lcfi
; FAST: movq $2, (%rsp) ; FAST: movq $2, (%rsp)
; FAST-NEXT: movl $4, 16(%rsp) ; FAST-NEXT: movl $4, 16(%rsp)
; FAST-NEXT: movq $6, 24(%rsp) ; FAST-NEXT: movq $6, 24(%rsp)
; FAST-NEXT: movl $8, 36(%rsp) ; FAST-NEXT: movl $8, 36(%rsp)
; FAST-NEXT: movq $10, 48(%rsp) ; FAST-NEXT: movq $10, 48(%rsp)
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: movabsq $-559038736, %r11 ; FAST-NEXT: movabsq $-559038736, %r11
; FAST-NEXT: callq *%r11 ; FAST-NEXT: callq *%r11
%call = inttoptr i64 -559038736 to i8* %call = inttoptr i64 -559038736 to i8*
%result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10) %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 15, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
ret i64 %result ret i64 %result
} }
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/X86/pr21792.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s
; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by ; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by
; PR21792 ; PR21792
@stuff = external constant [256 x double], align 16 @stuff = external constant [256 x double], align 16
define void @func(<4 x float> %vx) { define void @func(<4 x float> %vx) {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 ; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: pextrq $1, %xmm0, %rdx ; CHECK-NEXT: pextrq $1, %xmm0, %rdx
; CHECK-NEXT: movq %rdx, %rcx ; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: shrq $32, %rcx ; CHECK-NEXT: shrq $32, %rcx
; CHECK-NEXT: movq %xmm0, %rax ; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: movq %rax, %r9 ; CHECK-NEXT: movq %rax, %r9
; CHECK-NEXT: shrq $32, %r9 ; CHECK-NEXT: shrq $32, %r9
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llvm/trunk/test/CodeGen/X86/pr2656.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; We can not fold the load from the stack into the 'and' instruction because ; We can not fold the load from the stack into the 'and' instruction because
; that changes an 8-byte load into a 16-byte load (illegal memory access). ; that changes an 8-byte load into a 16-byte load (illegal memory access).
; We can fold the load of the constant because it is a 16-byte vector constant. ; We can fold the load of the constant because it is a 16-byte vector constant.
define double @PR22371(double %x) { define double @PR22371(double %x) {
; CHECK-LABEL: PR22371: ; CHECK-LABEL: PR22371:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: andps LCPI1_0, %xmm0 ; CHECK-NEXT: andps LCPI1_0, %xmm0
; CHECK-NEXT: movlps %xmm0, (%esp) ; CHECK-NEXT: movlps %xmm0, (%esp)
; CHECK-NEXT: fldl (%esp) ; CHECK-NEXT: fldl (%esp)
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%call = tail call double @fabs(double %x) #0 %call = tail call double @fabs(double %x) #0
ret double %call ret double %call
} }
declare double @fabs(double) #0 declare double @fabs(double) #0
attributes #0 = { readnone } attributes #0 = { readnone }

llvm/trunk/test/CodeGen/X86/pr29061.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple i386-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple i386-unknown-linux-gnu < %s | FileCheck %s
; Previously, a reference to SIL/DIL was being emitted ; Previously, a reference to SIL/DIL was being emitted
; but those aren't available unless on a 64bit mode ; but those aren't available unless on a 64bit mode
define void @t1(i8 signext %c) { define void @t1(i8 signext %c) {
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %edi, -8 ; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: # kill: %DI<def> %DI<kill> %EDI<kill> ; CHECK-NEXT: # kill: %DI<def> %DI<kill> %EDI<kill>
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
tail call void asm sideeffect "", "{di},~{dirflag},~{fpsr},~{flags}"(i8 %c) tail call void asm sideeffect "", "{di},~{dirflag},~{fpsr},~{flags}"(i8 %c)
ret void ret void
} }
define void @t2(i8 signext %c) { define void @t2(i8 signext %c) {
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: # kill: %SI<def> %SI<kill> %ESI<kill> ; CHECK-NEXT: # kill: %SI<def> %SI<kill> %ESI<kill>
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
tail call void asm sideeffect "", "{si},~{dirflag},~{fpsr},~{flags}"(i8 %c) tail call void asm sideeffect "", "{si},~{dirflag},~{fpsr},~{flags}"(i8 %c)
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/pr29112.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s
declare <4 x float> @foo(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>) declare <4 x float> @foo(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>)
; Due to a bug in X86RegisterInfo::getLargestLegalSuperClass this test case was trying to use XMM16 and spill it without VLX support for the necessary store instruction. We briefly implemented the spill using VEXTRACTF32X4, but the bug in getLargestLegalSuperClass has now been fixed so we no longer use XMM16. ; Due to a bug in X86RegisterInfo::getLargestLegalSuperClass this test case was trying to use XMM16 and spill it without VLX support for the necessary store instruction. We briefly implemented the spill using VEXTRACTF32X4, but the bug in getLargestLegalSuperClass has now been fixed so we no longer use XMM16.
define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <4 x float> %a4, <16 x float>%c1, <16 x float>%c2) { define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <4 x float> %a4, <16 x float>%c1, <16 x float>%c2) {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: subq $88, %rsp ; CHECK-NEXT: subq $88, %rsp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-NEXT: vextractf128 $1, %ymm3, %xmm1 ; CHECK-NEXT: vextractf128 $1, %ymm3, %xmm1
; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm8 ; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm8
; CHECK-NEXT: vinsertps {{.*#+}} xmm9 = xmm8[0],xmm1[0],xmm8[2,3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm9 = xmm8[0],xmm1[0],xmm8[2,3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm9[0,1],xmm2[1],xmm9[3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm9[0,1],xmm2[1],xmm9[3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm15 = xmm0[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm15 = xmm0[0,1,2],xmm3[1]
; CHECK-NEXT: vblendps {{.*#+}} xmm4 = xmm8[0],xmm1[1],xmm8[2,3] ; CHECK-NEXT: vblendps {{.*#+}} xmm4 = xmm8[0],xmm1[1],xmm8[2,3]
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llvm/trunk/test/CodeGen/X86/pr30430.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f -O0 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f -O0 | FileCheck %s
define <16 x float> @makefloat(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, float %f8, float %f9, float %f10, float %f11, float %f12, float %f13, float %f14, float %f15, float %f16) #0 { define <16 x float> @makefloat(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, float %f8, float %f9, float %f10, float %f11, float %f12, float %f13, float %f14, float %f15, float %f16) #0 {
; CHECK-LABEL: makefloat: ; CHECK-LABEL: makefloat:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $256, %rsp # imm = 0x100 ; CHECK-NEXT: subq $256, %rsp # imm = 0x100
; CHECK-NEXT: vmovss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm10 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm10 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm11 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm11 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm12 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm12 = mem[0],zero,zero,zero
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llvm/trunk/test/CodeGen/X86/pr32241.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
define i32 @_Z3foov() { define i32 @_Z3foov() {
; CHECK-LABEL: _Z3foov: ; CHECK-LABEL: _Z3foov:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $24, %esp ; CHECK-NEXT: subl $24, %esp
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF ; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF
; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376 ; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376
; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9 ; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill ; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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llvm/trunk/test/CodeGen/X86/pr32256.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
@c = external global i8, align 1 @c = external global i8, align 1
; Function Attrs: noinline nounwind ; Function Attrs: noinline nounwind
define void @_Z1av() { define void @_Z1av() {
; CHECK-LABEL: _Z1av: ; CHECK-LABEL: _Z1av:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: subl $2, %esp ; CHECK-NEXT: subl $2, %esp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 6 ; CHECK-NEXT: .cfi_def_cfa_offset 6
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movb %al, %cl ; CHECK-NEXT: movb %al, %cl
; CHECK-NEXT: movb c, %dl ; CHECK-NEXT: movb c, %dl
; CHECK-NEXT: xorb $-1, %dl ; CHECK-NEXT: xorb $-1, %dl
; CHECK-NEXT: testb $1, %dl ; CHECK-NEXT: testb $1, %dl
; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill ; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill
; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: jne .LBB0_1
Show All 28 Lines

llvm/trunk/test/CodeGen/X86/pr32282.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X64
; Check for assert in foldMaskAndShiftToScale due to out of range mask scaling. ; Check for assert in foldMaskAndShiftToScale due to out of range mask scaling.
@b = common global i8 zeroinitializer, align 1 @b = common global i8 zeroinitializer, align 1
@c = common global i8 zeroinitializer, align 1 @c = common global i8 zeroinitializer, align 1
@d = common global i64 zeroinitializer, align 8 @d = common global i64 zeroinitializer, align 8
@e = common global i64 zeroinitializer, align 8 @e = common global i64 zeroinitializer, align 8
define void @foo() { define void @foo() {
; X86-LABEL: foo: ; X86-LABEL: foo:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: movl d, %eax ; X86-NEXT: movl d, %eax
; X86-NEXT: movl d+4, %ecx ; X86-NEXT: movl d+4, %ecx
; X86-NEXT: movl $701685459, %edx # imm = 0x29D2DED3 ; X86-NEXT: movl $701685459, %edx # imm = 0x29D2DED3
; X86-NEXT: andnl %edx, %ecx, %ecx ; X86-NEXT: andnl %edx, %ecx, %ecx
; X86-NEXT: movl $-564453154, %edx # imm = 0xDE5B20DE ; X86-NEXT: movl $-564453154, %edx # imm = 0xDE5B20DE
; X86-NEXT: andnl %edx, %eax, %edx ; X86-NEXT: andnl %edx, %eax, %edx
; X86-NEXT: shrdl $21, %ecx, %edx ; X86-NEXT: shrdl $21, %ecx, %edx
; X86-NEXT: shrl $21, %ecx ; X86-NEXT: shrl $21, %ecx
; X86-NEXT: xorl %eax, %eax ; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testb %al, %al ; X86-NEXT: testb %al, %al
; X86-NEXT: cmovnel %ecx, %edx ; X86-NEXT: cmovnel %ecx, %edx
; X86-NEXT: cmovnel %eax, %ecx ; X86-NEXT: cmovnel %eax, %ecx
; X86-NEXT: andl $-2, %edx ; X86-NEXT: andl $-2, %edx
; X86-NEXT: addl $7, %edx ; X86-NEXT: addl $7, %edx
; X86-NEXT: adcxl %eax, %ecx ; X86-NEXT: adcxl %eax, %ecx
; X86-NEXT: pushl %ecx ; X86-NEXT: pushl %ecx
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %edx ; X86-NEXT: pushl %edx
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $0 ; X86-NEXT: pushl $0
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl $0 ; X86-NEXT: pushl $0
; X86-NEXT: .Lcfi4:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll __divdi3 ; X86-NEXT: calll __divdi3
; X86-NEXT: addl $16, %esp ; X86-NEXT: addl $16, %esp
; X86-NEXT: .Lcfi5:
; X86-NEXT: .cfi_adjust_cfa_offset -16 ; X86-NEXT: .cfi_adjust_cfa_offset -16
; X86-NEXT: orl %eax, %edx ; X86-NEXT: orl %eax, %edx
; X86-NEXT: setne {{[0-9]+}}(%esp) ; X86-NEXT: setne {{[0-9]+}}(%esp)
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: foo: ; X64-LABEL: foo:
; X64: # BB#0: ; X64: # BB#0:
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llvm/trunk/test/CodeGen/X86/pr32329.ll

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@var_50 = external local_unnamed_addr global i64, align 8 @var_50 = external local_unnamed_addr global i64, align 8
@var_205 = external local_unnamed_addr global i8, align 1 @var_205 = external local_unnamed_addr global i8, align 1
@var_218 = external local_unnamed_addr global i8, align 1 @var_218 = external local_unnamed_addr global i8, align 1
define void @foo() local_unnamed_addr { define void @foo() local_unnamed_addr {
; X86-LABEL: foo: ; X86-LABEL: foo:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: .cfi_def_cfa_offset 16
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_def_cfa_offset 20 ; X86-NEXT: .cfi_def_cfa_offset 20
; X86-NEXT: .Lcfi4:
; X86-NEXT: .cfi_offset %esi, -20 ; X86-NEXT: .cfi_offset %esi, -20
; X86-NEXT: .Lcfi5:
; X86-NEXT: .cfi_offset %edi, -16 ; X86-NEXT: .cfi_offset %edi, -16
; X86-NEXT: .Lcfi6:
; X86-NEXT: .cfi_offset %ebx, -12 ; X86-NEXT: .cfi_offset %ebx, -12
; X86-NEXT: .Lcfi7:
; X86-NEXT: .cfi_offset %ebp, -8 ; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl obj, %edx ; X86-NEXT: movl obj, %edx
; X86-NEXT: movsbl var_27, %eax ; X86-NEXT: movsbl var_27, %eax
; X86-NEXT: movzwl var_2, %esi ; X86-NEXT: movzwl var_2, %esi
; X86-NEXT: movl var_310, %ecx ; X86-NEXT: movl var_310, %ecx
; X86-NEXT: imull %eax, %ecx ; X86-NEXT: imull %eax, %ecx
; X86-NEXT: addl var_24, %ecx ; X86-NEXT: addl var_24, %ecx
; X86-NEXT: andl $4194303, %edx # imm = 0x3FFFFF ; X86-NEXT: andl $4194303, %edx # imm = 0x3FFFFF
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llvm/trunk/test/CodeGen/X86/pr32345.ll

Show All 31 Lines
; X640-NEXT: sarq %cl, %rsi ; X640-NEXT: sarq %cl, %rsi
; X640-NEXT: movb %sil, %cl ; X640-NEXT: movb %sil, %cl
; X640-NEXT: movb %cl, (%rax) ; X640-NEXT: movb %cl, (%rax)
; X640-NEXT: retq ; X640-NEXT: retq
; ;
; 6860-LABEL: foo: ; 6860-LABEL: foo:
; 6860: # BB#0: # %bb ; 6860: # BB#0: # %bb
; 6860-NEXT: pushl %ebp ; 6860-NEXT: pushl %ebp
; 6860-NEXT: .Lcfi0:
; 6860-NEXT: .cfi_def_cfa_offset 8 ; 6860-NEXT: .cfi_def_cfa_offset 8
; 6860-NEXT: .Lcfi1:
; 6860-NEXT: .cfi_offset %ebp, -8 ; 6860-NEXT: .cfi_offset %ebp, -8
; 6860-NEXT: movl %esp, %ebp ; 6860-NEXT: movl %esp, %ebp
; 6860-NEXT: .Lcfi2:
; 6860-NEXT: .cfi_def_cfa_register %ebp ; 6860-NEXT: .cfi_def_cfa_register %ebp
; 6860-NEXT: pushl %ebx ; 6860-NEXT: pushl %ebx
; 6860-NEXT: pushl %edi ; 6860-NEXT: pushl %edi
; 6860-NEXT: pushl %esi ; 6860-NEXT: pushl %esi
; 6860-NEXT: andl $-8, %esp ; 6860-NEXT: andl $-8, %esp
; 6860-NEXT: subl $32, %esp ; 6860-NEXT: subl $32, %esp
; 6860-NEXT: .Lcfi3:
; 6860-NEXT: .cfi_offset %esi, -20 ; 6860-NEXT: .cfi_offset %esi, -20
; 6860-NEXT: .Lcfi4:
; 6860-NEXT: .cfi_offset %edi, -16 ; 6860-NEXT: .cfi_offset %edi, -16
; 6860-NEXT: .Lcfi5:
; 6860-NEXT: .cfi_offset %ebx, -12 ; 6860-NEXT: .cfi_offset %ebx, -12
; 6860-NEXT: # implicit-def: %EAX ; 6860-NEXT: # implicit-def: %EAX
; 6860-NEXT: movw var_22, %cx ; 6860-NEXT: movw var_22, %cx
; 6860-NEXT: movzwl var_27, %edx ; 6860-NEXT: movzwl var_27, %edx
; 6860-NEXT: movw %dx, %si ; 6860-NEXT: movw %dx, %si
; 6860-NEXT: xorw %si, %cx ; 6860-NEXT: xorw %si, %cx
; 6860-NEXT: # implicit-def: %EDI ; 6860-NEXT: # implicit-def: %EDI
; 6860-NEXT: movw %cx, %di ; 6860-NEXT: movw %cx, %di
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; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> ; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
; X64-NEXT: shrq %cl, %rax ; X64-NEXT: shrq %cl, %rax
; X64-NEXT: movb %al, (%rax) ; X64-NEXT: movb %al, (%rax)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; 686-LABEL: foo: ; 686-LABEL: foo:
; 686: # BB#0: # %bb ; 686: # BB#0: # %bb
; 686-NEXT: pushl %ebp ; 686-NEXT: pushl %ebp
; 686-NEXT: .Lcfi0:
; 686-NEXT: .cfi_def_cfa_offset 8 ; 686-NEXT: .cfi_def_cfa_offset 8
; 686-NEXT: .Lcfi1:
; 686-NEXT: .cfi_offset %ebp, -8 ; 686-NEXT: .cfi_offset %ebp, -8
; 686-NEXT: movl %esp, %ebp ; 686-NEXT: movl %esp, %ebp
; 686-NEXT: .Lcfi2:
; 686-NEXT: .cfi_def_cfa_register %ebp ; 686-NEXT: .cfi_def_cfa_register %ebp
; 686-NEXT: andl $-8, %esp ; 686-NEXT: andl $-8, %esp
; 686-NEXT: subl $8, %esp ; 686-NEXT: subl $8, %esp
; 686-NEXT: movzwl var_27, %ecx ; 686-NEXT: movzwl var_27, %ecx
; 686-NEXT: movzwl var_22, %eax ; 686-NEXT: movzwl var_22, %eax
; 686-NEXT: xorw %cx, %ax ; 686-NEXT: xorw %cx, %ax
; 686-NEXT: xorl %ecx, %eax ; 686-NEXT: xorl %ecx, %eax
; 686-NEXT: movzwl %ax, %eax ; 686-NEXT: movzwl %ax, %eax
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llvm/trunk/test/CodeGen/X86/pr32451.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=knl | FileCheck %s ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=knl | FileCheck %s
; ModuleID = 'convert' ; ModuleID = 'convert'
source_filename = "convert" source_filename = "convert"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i8** @japi1_convert_690(i8**, i8***, i32) { define i8** @japi1_convert_690(i8**, i8***, i32) {
; CHECK-LABEL: japi1_convert_690: ; CHECK-LABEL: japi1_convert_690:
; CHECK: # BB#0: # %top ; CHECK: # BB#0: # %top
; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_offset %ebx, -8 ; CHECK-NEXT: .cfi_offset %ebx, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; CHECK-NEXT: calll julia.gc_root_decl ; CHECK-NEXT: calll julia.gc_root_decl
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; CHECK-NEXT: calll jl_get_ptls_states ; CHECK-NEXT: calll jl_get_ptls_states
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload
; CHECK-NEXT: movl 4(%ecx), %edx ; CHECK-NEXT: movl 4(%ecx), %edx
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llvm/trunk/test/CodeGen/X86/pr34080.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -mcpu=x86-64 | FileCheck %s --check-prefix=SSE2-BROKEN ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -mcpu=x86-64 | FileCheck %s --check-prefix=SSE2-BROKEN
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 | FileCheck %s --check-prefix=SSE3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=prescott | FileCheck %s --check-prefix=SSE3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=prescott | FileCheck %s --check-prefix=SSE3
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -mcpu=sandybridge | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 { define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE2-LABEL: _Z1fe: ; SSE2-LABEL: _Z1fe:
; SSE2: ## BB#0: ## %entry ; SSE2: ## BB#0: ## %entry
; SSE2-NEXT: pushq %rbp ; SSE2-NEXT: pushq %rbp
; SSE2-NEXT: Lcfi0:
; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: .cfi_def_cfa_offset 16
; SSE2-NEXT: Lcfi1:
; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: .cfi_offset %rbp, -16
; SSE2-NEXT: movq %rsp, %rbp ; SSE2-NEXT: movq %rsp, %rbp
; SSE2-NEXT: Lcfi2:
; SSE2-NEXT: .cfi_def_cfa_register %rbp ; SSE2-NEXT: .cfi_def_cfa_register %rbp
; SSE2-NEXT: fldt 16(%rbp) ; SSE2-NEXT: fldt 16(%rbp)
; SSE2-NEXT: fnstcw -4(%rbp) ; SSE2-NEXT: fnstcw -4(%rbp)
; SSE2-NEXT: movzwl -4(%rbp), %eax ; SSE2-NEXT: movzwl -4(%rbp), %eax
; SSE2-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F ; SSE2-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
; SSE2-NEXT: fldcw -4(%rbp) ; SSE2-NEXT: fldcw -4(%rbp)
; SSE2-NEXT: movw %ax, -4(%rbp) ; SSE2-NEXT: movw %ax, -4(%rbp)
; SSE2-NEXT: fistl -8(%rbp) ; SSE2-NEXT: fistl -8(%rbp)
Show All 20 Lines
; SSE2-NEXT: fmulp %st(1) ; SSE2-NEXT: fmulp %st(1)
; SSE2-NEXT: fstpl -48(%rbp) ; SSE2-NEXT: fstpl -48(%rbp)
; SSE2-NEXT: popq %rbp ; SSE2-NEXT: popq %rbp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE2-BROKEN-LABEL: _Z1fe: ; SSE2-BROKEN-LABEL: _Z1fe:
; SSE2-BROKEN: ## BB#0: ## %entry ; SSE2-BROKEN: ## BB#0: ## %entry
; SSE2-BROKEN-NEXT: pushq %rbp ; SSE2-BROKEN-NEXT: pushq %rbp
; SSE2-BROKEN-NEXT: Lcfi0:
; SSE2-BROKEN-NEXT: .cfi_def_cfa_offset 16 ; SSE2-BROKEN-NEXT: .cfi_def_cfa_offset 16
; SSE2-BROKEN-NEXT: Lcfi1:
; SSE2-BROKEN-NEXT: .cfi_offset %rbp, -16 ; SSE2-BROKEN-NEXT: .cfi_offset %rbp, -16
; SSE2-BROKEN-NEXT: movq %rsp, %rbp ; SSE2-BROKEN-NEXT: movq %rsp, %rbp
; SSE2-BROKEN-NEXT: Lcfi2:
; SSE2-BROKEN-NEXT: .cfi_def_cfa_register %rbp ; SSE2-BROKEN-NEXT: .cfi_def_cfa_register %rbp
; SSE2-BROKEN-NEXT: fnstcw -4(%rbp) ; SSE2-BROKEN-NEXT: fnstcw -4(%rbp)
; SSE2-BROKEN-NEXT: fldt 16(%rbp) ; SSE2-BROKEN-NEXT: fldt 16(%rbp)
; SSE2-BROKEN-NEXT: movzwl -4(%rbp), %eax ; SSE2-BROKEN-NEXT: movzwl -4(%rbp), %eax
; SSE2-BROKEN-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F ; SSE2-BROKEN-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
; SSE2-BROKEN-NEXT: fldcw -4(%rbp) ; SSE2-BROKEN-NEXT: fldcw -4(%rbp)
; SSE2-BROKEN-NEXT: movw %ax, -4(%rbp) ; SSE2-BROKEN-NEXT: movw %ax, -4(%rbp)
; SSE2-BROKEN-NEXT: fistl -8(%rbp) ; SSE2-BROKEN-NEXT: fistl -8(%rbp)
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; SSE2-BROKEN-NEXT: fmulp %st(1) ; SSE2-BROKEN-NEXT: fmulp %st(1)
; SSE2-BROKEN-NEXT: fstpl -48(%rbp) ; SSE2-BROKEN-NEXT: fstpl -48(%rbp)
; SSE2-BROKEN-NEXT: popq %rbp ; SSE2-BROKEN-NEXT: popq %rbp
; SSE2-BROKEN-NEXT: retq ; SSE2-BROKEN-NEXT: retq
; ;
; SSE3-LABEL: _Z1fe: ; SSE3-LABEL: _Z1fe:
; SSE3: ## BB#0: ## %entry ; SSE3: ## BB#0: ## %entry
; SSE3-NEXT: pushq %rbp ; SSE3-NEXT: pushq %rbp
; SSE3-NEXT: Lcfi0:
; SSE3-NEXT: .cfi_def_cfa_offset 16 ; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: Lcfi1:
; SSE3-NEXT: .cfi_offset %rbp, -16 ; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movq %rsp, %rbp ; SSE3-NEXT: movq %rsp, %rbp
; SSE3-NEXT: Lcfi2:
; SSE3-NEXT: .cfi_def_cfa_register %rbp ; SSE3-NEXT: .cfi_def_cfa_register %rbp
; SSE3-NEXT: fldt 16(%rbp) ; SSE3-NEXT: fldt 16(%rbp)
; SSE3-NEXT: fld %st(0) ; SSE3-NEXT: fld %st(0)
; SSE3-NEXT: fisttpl -4(%rbp) ; SSE3-NEXT: fisttpl -4(%rbp)
; SSE3-NEXT: cvtsi2sdl -4(%rbp), %xmm0 ; SSE3-NEXT: cvtsi2sdl -4(%rbp), %xmm0
; SSE3-NEXT: movsd %xmm0, -48(%rbp) ; SSE3-NEXT: movsd %xmm0, -48(%rbp)
; SSE3-NEXT: movsd %xmm0, -24(%rbp) ; SSE3-NEXT: movsd %xmm0, -24(%rbp)
; SSE3-NEXT: fsubl -24(%rbp) ; SSE3-NEXT: fsubl -24(%rbp)
Show All 10 Lines
; SSE3-NEXT: fmulp %st(1) ; SSE3-NEXT: fmulp %st(1)
; SSE3-NEXT: fstpl -32(%rbp) ; SSE3-NEXT: fstpl -32(%rbp)
; SSE3-NEXT: popq %rbp ; SSE3-NEXT: popq %rbp
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: _Z1fe: ; AVX-LABEL: _Z1fe:
; AVX: ## BB#0: ## %entry ; AVX: ## BB#0: ## %entry
; AVX-NEXT: pushq %rbp ; AVX-NEXT: pushq %rbp
; AVX-NEXT: Lcfi0:
; AVX-NEXT: .cfi_def_cfa_offset 16 ; AVX-NEXT: .cfi_def_cfa_offset 16
; AVX-NEXT: Lcfi1:
; AVX-NEXT: .cfi_offset %rbp, -16 ; AVX-NEXT: .cfi_offset %rbp, -16
; AVX-NEXT: movq %rsp, %rbp ; AVX-NEXT: movq %rsp, %rbp
; AVX-NEXT: Lcfi2:
; AVX-NEXT: .cfi_def_cfa_register %rbp ; AVX-NEXT: .cfi_def_cfa_register %rbp
; AVX-NEXT: fldt 16(%rbp) ; AVX-NEXT: fldt 16(%rbp)
; AVX-NEXT: fld %st(0) ; AVX-NEXT: fld %st(0)
; AVX-NEXT: fisttpl -4(%rbp) ; AVX-NEXT: fisttpl -4(%rbp)
; AVX-NEXT: vcvtsi2sdl -4(%rbp), %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2sdl -4(%rbp), %xmm0, %xmm0
; AVX-NEXT: vmovsd %xmm0, -48(%rbp) ; AVX-NEXT: vmovsd %xmm0, -48(%rbp)
; AVX-NEXT: vmovsd %xmm0, -24(%rbp) ; AVX-NEXT: vmovsd %xmm0, -24(%rbp)
; AVX-NEXT: fsubl -24(%rbp) ; AVX-NEXT: fsubl -24(%rbp)
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llvm/trunk/test/CodeGen/X86/pr34088.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mcpu=pentium4 | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown -mcpu=pentium4 | FileCheck %s
%struct.Foo = type { i32, %struct.Bar } %struct.Foo = type { i32, %struct.Bar }
%struct.Bar = type { i32, %struct.Buffer, i32 } %struct.Bar = type { i32, %struct.Buffer, i32 }
%struct.Buffer = type { i8*, i32 } %struct.Buffer = type { i8*, i32 }
; This test checks that the load of store %2 is not dropped. ; This test checks that the load of store %2 is not dropped.
; ;
define i32 @pr34088() local_unnamed_addr { define i32 @pr34088() local_unnamed_addr {
; CHECK-LABEL: pr34088: ; CHECK-LABEL: pr34088:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-16, %esp ; CHECK-NEXT: andl $-16, %esp
; CHECK-NEXT: subl $32, %esp ; CHECK-NEXT: subl $32, %esp
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movaps %xmm0, (%esp) ; CHECK-NEXT: movaps %xmm0, (%esp)
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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llvm/trunk/test/CodeGen/X86/pr9743.ll

; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-fp-elim -asm-verbose=0 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-fp-elim -asm-verbose=0 | FileCheck %s
define void @f() { define void @f() {
ret void ret void
} }
; CHECK: .cfi_startproc ; CHECK: .cfi_startproc
; CHECK-NEXT: pushq ; CHECK-NEXT: pushq
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: popq %rbp ; CHECK-NEXT: popq %rbp
; CHECK-NEXT: ret ; CHECK-NEXT: ret

llvm/trunk/test/CodeGen/X86/push-cfi.ll

; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=LINUX -check-prefix=CHECK ; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=LINUX -check-prefix=CHECK
; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=DARWIN -check-prefix=CHECK ; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=DARWIN -check-prefix=CHECK
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare void @good(i32 %a, i32 %b, i32 %c, i32 %d) declare void @good(i32 %a, i32 %b, i32 %c, i32 %d)
declare void @large(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) declare void @large(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f)
declare void @empty() declare void @empty()
; When we use an invoke, we expect a .cfi_escape GNU_ARGS_SIZE ; When we use an invoke, we expect a .cfi_escape GNU_ARGS_SIZE
; with size 16 before the invocation. Without FP, we also expect ; with size 16 before the invocation. Without FP, we also expect
; .cfi_adjust_cfa_offset after each push. ; .cfi_adjust_cfa_offset after each push.
; Darwin should not generate pushes in either circumstance. ; Darwin should not generate pushes in either circumstance.
; CHECK-LABEL: test1_nofp: ; CHECK-LABEL: test1_nofp:
; LINUX: .cfi_escape 0x2e, 0x10 ; LINUX: .cfi_escape 0x2e, 0x10
; LINUX-NEXT: pushl $4 ; LINUX-NEXT: pushl $4
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3 ; LINUX-NEXT: pushl $3
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2 ; LINUX-NEXT: pushl $2
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1 ; LINUX-NEXT: pushl $1
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call ; LINUX-NEXT: call
; LINUX-NEXT: addl $16, %esp ; LINUX-NEXT: addl $16, %esp
; LINUX: .cfi_adjust_cfa_offset -16 ; LINUX: .cfi_adjust_cfa_offset -16
; DARWIN-NOT: .cfi_escape ; DARWIN-NOT: .cfi_escape
; DARWIN-NOT: pushl ; DARWIN-NOT: pushl
define void @test1_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define void @test1_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
entry: entry:
Show All 31 Lines
} }
; If the function has no handlers, we don't need to generate GNU_ARGS_SIZE, ; If the function has no handlers, we don't need to generate GNU_ARGS_SIZE,
; even if it has an unwind table. Without FP, we still need cfi_adjust_cfa_offset, ; even if it has an unwind table. Without FP, we still need cfi_adjust_cfa_offset,
; so darwin should not generate pushes. ; so darwin should not generate pushes.
; CHECK-LABEL: test2_nofp: ; CHECK-LABEL: test2_nofp:
; LINUX-NOT: .cfi_escape ; LINUX-NOT: .cfi_escape
; LINUX: pushl $4 ; LINUX: pushl $4
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3 ; LINUX-NEXT: pushl $3
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2 ; LINUX-NEXT: pushl $2
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1 ; LINUX-NEXT: pushl $1
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call ; LINUX-NEXT: call
; LINUX-NEXT: addl $28, %esp ; LINUX-NEXT: addl $28, %esp
; LINUX: .cfi_adjust_cfa_offset -16 ; LINUX: .cfi_adjust_cfa_offset -16
; DARWIN-NOT: .cfi_escape ; DARWIN-NOT: .cfi_escape
; DARWIN-NOT: pushl ; DARWIN-NOT: pushl
define void @test2_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define void @test2_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
entry: entry:
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Linescleanup:
ret void ret void
} }
; If we did use pushes, we need to reset GNU_ARGS_SIZE before a call ; If we did use pushes, we need to reset GNU_ARGS_SIZE before a call
; without parameters, but don't need to adjust the cfa offset ; without parameters, but don't need to adjust the cfa offset
; CHECK-LABEL: test5_nofp: ; CHECK-LABEL: test5_nofp:
; LINUX: .cfi_escape 0x2e, 0x10 ; LINUX: .cfi_escape 0x2e, 0x10
; LINUX-NEXT: pushl $4 ; LINUX-NEXT: pushl $4
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3 ; LINUX-NEXT: pushl $3
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2 ; LINUX-NEXT: pushl $2
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1 ; LINUX-NEXT: pushl $1
; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call ; LINUX-NEXT: call
; LINUX-NEXT: addl $16, %esp ; LINUX-NEXT: addl $16, %esp
; LINUX: .cfi_adjust_cfa_offset -16 ; LINUX: .cfi_adjust_cfa_offset -16
; LINUX-NOT: .cfi_adjust_cfa_offset ; LINUX-NOT: .cfi_adjust_cfa_offset
; LINUX: .cfi_escape 0x2e, 0x00 ; LINUX: .cfi_escape 0x2e, 0x00
; LINUX-NOT: .cfi_adjust_cfa_offset ; LINUX-NOT: .cfi_adjust_cfa_offset
; LINUX: call ; LINUX: call
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llvm/trunk/test/CodeGen/X86/recip-pic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -enable-unsafe-fp-math -mcpu=slm -relocation-model=pic | FileCheck %s --check-prefix=CHECK ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -enable-unsafe-fp-math -mcpu=slm -relocation-model=pic | FileCheck %s --check-prefix=CHECK
define fastcc float @foo(float %x) unnamed_addr #0 { define fastcc float @foo(float %x) unnamed_addr #0 {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: calll .L0$pb ; CHECK-NEXT: calll .L0$pb
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_adjust_cfa_offset 4 ; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: .L0$pb: ; CHECK-NEXT: .L0$pb:
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_adjust_cfa_offset -4 ; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax ; CHECK-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: divss %xmm0, %xmm1 ; CHECK-NEXT: divss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: movss %xmm1, (%eax) ; CHECK-NEXT: movss %xmm1, (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%div = fdiv fast float 3.0, %x %div = fdiv fast float 3.0, %x
store float %div, float* undef, align 4 store float %div, float* undef, align 4
ret float %div ret float %div
} }

llvm/trunk/test/CodeGen/X86/rtm.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: xabort $1 ; X86-NEXT: xabort $1
; X86-NEXT: calll f1 ; X86-NEXT: calll f1
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: f2: ; X64-LABEL: f2:
; X64: # BB#0: # %entry ; X64: # BB#0: # %entry
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: .Lcfi0:
; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; X64-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; X64-NEXT: xabort $1 ; X64-NEXT: xabort $1
; X64-NEXT: callq f1 ; X64-NEXT: callq f1
; X64-NEXT: popq %rax ; X64-NEXT: popq %rax
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%x.addr = alloca i32, align 4 %x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4 store i32 %x, i32* %x.addr, align 4
call void @llvm.x86.xabort(i8 1) call void @llvm.x86.xabort(i8 1)
call void @f1() call void @f1()
ret void ret void
} }

llvm/trunk/test/CodeGen/X86/select-mmx.ll

Show All 20 Lines
; X64-NEXT: movd %rax, %mm0 ; X64-NEXT: movd %rax, %mm0
; X64-NEXT: psllw %mm0, %mm0 ; X64-NEXT: psllw %mm0, %mm0
; X64-NEXT: movd %mm0, %rax ; X64-NEXT: movd %mm0, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; I32-LABEL: test47: ; I32-LABEL: test47:
; I32: # BB#0: ; I32: # BB#0:
; I32-NEXT: pushl %ebp ; I32-NEXT: pushl %ebp
; I32-NEXT: .Lcfi0:
; I32-NEXT: .cfi_def_cfa_offset 8 ; I32-NEXT: .cfi_def_cfa_offset 8
; I32-NEXT: .Lcfi1:
; I32-NEXT: .cfi_offset %ebp, -8 ; I32-NEXT: .cfi_offset %ebp, -8
; I32-NEXT: movl %esp, %ebp ; I32-NEXT: movl %esp, %ebp
; I32-NEXT: .Lcfi2:
; I32-NEXT: .cfi_def_cfa_register %ebp ; I32-NEXT: .cfi_def_cfa_register %ebp
; I32-NEXT: andl $-8, %esp ; I32-NEXT: andl $-8, %esp
; I32-NEXT: subl $16, %esp ; I32-NEXT: subl $16, %esp
; I32-NEXT: movl 8(%ebp), %eax ; I32-NEXT: movl 8(%ebp), %eax
; I32-NEXT: orl 12(%ebp), %eax ; I32-NEXT: orl 12(%ebp), %eax
; I32-NEXT: movl $7, %eax ; I32-NEXT: movl $7, %eax
; I32-NEXT: je .LBB0_2 ; I32-NEXT: je .LBB0_2
; I32-NEXT: # BB#1: ; I32-NEXT: # BB#1:
Show All 33 Lines
; X64-NEXT: movd %rsi, %mm0 ; X64-NEXT: movd %rsi, %mm0
; X64-NEXT: psllw %mm0, %mm0 ; X64-NEXT: psllw %mm0, %mm0
; X64-NEXT: movd %mm0, %rax ; X64-NEXT: movd %mm0, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; I32-LABEL: test49: ; I32-LABEL: test49:
; I32: # BB#0: ; I32: # BB#0:
; I32-NEXT: pushl %ebp ; I32-NEXT: pushl %ebp
; I32-NEXT: .Lcfi3:
; I32-NEXT: .cfi_def_cfa_offset 8 ; I32-NEXT: .cfi_def_cfa_offset 8
; I32-NEXT: .Lcfi4:
; I32-NEXT: .cfi_offset %ebp, -8 ; I32-NEXT: .cfi_offset %ebp, -8
; I32-NEXT: movl %esp, %ebp ; I32-NEXT: movl %esp, %ebp
; I32-NEXT: .Lcfi5:
; I32-NEXT: .cfi_def_cfa_register %ebp ; I32-NEXT: .cfi_def_cfa_register %ebp
; I32-NEXT: andl $-8, %esp ; I32-NEXT: andl $-8, %esp
; I32-NEXT: subl $8, %esp ; I32-NEXT: subl $8, %esp
; I32-NEXT: movl 8(%ebp), %eax ; I32-NEXT: movl 8(%ebp), %eax
; I32-NEXT: orl 12(%ebp), %eax ; I32-NEXT: orl 12(%ebp), %eax
; I32-NEXT: je .LBB1_1 ; I32-NEXT: je .LBB1_1
; I32-NEXT: # BB#2: ; I32-NEXT: # BB#2:
; I32-NEXT: leal 24(%ebp), %eax ; I32-NEXT: leal 24(%ebp), %eax
Show All 23 Lines

llvm/trunk/test/CodeGen/X86/setcc-lowering.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; AVX-NEXT: testw %ax, %ax ; AVX-NEXT: testw %ax, %ax
; AVX-NEXT: jne .LBB1_1 ; AVX-NEXT: jne .LBB1_1
; AVX-NEXT: # BB#2: # %for_exit600 ; AVX-NEXT: # BB#2: # %for_exit600
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; KNL-32-LABEL: pr26232: ; KNL-32-LABEL: pr26232:
; KNL-32: # BB#0: # %for_loop599.preheader ; KNL-32: # BB#0: # %for_loop599.preheader
; KNL-32-NEXT: pushl %esi ; KNL-32-NEXT: pushl %esi
; KNL-32-NEXT: .Lcfi0:
; KNL-32-NEXT: .cfi_def_cfa_offset 8 ; KNL-32-NEXT: .cfi_def_cfa_offset 8
; KNL-32-NEXT: .Lcfi1:
; KNL-32-NEXT: .cfi_offset %esi, -8 ; KNL-32-NEXT: .cfi_offset %esi, -8
; KNL-32-NEXT: vpmovsxbd %xmm0, %zmm0 ; KNL-32-NEXT: vpmovsxbd %xmm0, %zmm0
; KNL-32-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-32-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-32-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-32-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; KNL-32-NEXT: movw $-1, %dx ; KNL-32-NEXT: movw $-1, %dx
; KNL-32-NEXT: .p2align 4, 0x90 ; KNL-32-NEXT: .p2align 4, 0x90
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llvm/trunk/test/CodeGen/X86/sincos.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Make sure this testcase codegens to the sin and cos instructions, not calls ; Make sure this testcase codegens to the sin and cos instructions, not calls
; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK --check-prefix=UNSAFE ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK --check-prefix=UNSAFE
; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SAFE ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=SAFE
declare float @sinf(float) readonly declare float @sinf(float) readonly
declare double @sin(double) readonly declare double @sin(double) readonly
declare x86_fp80 @sinl(x86_fp80) readonly declare x86_fp80 @sinl(x86_fp80) readonly
define float @test1(float %X) { define float @test1(float %X) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: flds {{[0-9]+}}(%esp) ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: fstps (%esp) ; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: calll _sinf ; CHECK-NEXT: calll _sinf
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call float @sinf(float %X) readonly %Y = call float @sinf(float %X) readonly
ret float %Y ret float %Y
} }
define double @test2(double %X) { define double @test2(double %X) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fldl {{[0-9]+}}(%esp) ; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpl (%esp) ; CHECK-NEXT: fstpl (%esp)
; CHECK-NEXT: calll _sin ; CHECK-NEXT: calll _sin
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call double @sin(double %X) readonly %Y = call double @sin(double %X) readonly
ret double %Y ret double %Y
} }
define x86_fp80 @test3(x86_fp80 %X) { define x86_fp80 @test3(x86_fp80 %X) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $28, %esp ; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpt (%esp) ; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll _sinl ; CHECK-NEXT: calll _sinl
; CHECK-NEXT: addl $28, %esp ; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call x86_fp80 @sinl(x86_fp80 %X) readonly %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
ret x86_fp80 %Y ret x86_fp80 %Y
} }
declare float @cosf(float) readonly declare float @cosf(float) readonly
declare double @cos(double) readonly declare double @cos(double) readonly
declare x86_fp80 @cosl(x86_fp80) readonly declare x86_fp80 @cosl(x86_fp80) readonly
define float @test4(float %X) { define float @test4(float %X) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: flds {{[0-9]+}}(%esp) ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: fstps (%esp) ; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: calll _cosf ; CHECK-NEXT: calll _cosf
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call float @cosf(float %X) readonly %Y = call float @cosf(float %X) readonly
ret float %Y ret float %Y
} }
define double @test5(double %X) { define double @test5(double %X) {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: Lcfi4:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fldl {{[0-9]+}}(%esp) ; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpl (%esp) ; CHECK-NEXT: fstpl (%esp)
; CHECK-NEXT: calll _cos ; CHECK-NEXT: calll _cos
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call double @cos(double %X) readonly %Y = call double @cos(double %X) readonly
ret double %Y ret double %Y
} }
define x86_fp80 @test6(x86_fp80 %X) { define x86_fp80 @test6(x86_fp80 %X) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: subl $28, %esp ; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: Lcfi5:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%esp) ; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpt (%esp) ; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll _cosl ; CHECK-NEXT: calll _cosl
; CHECK-NEXT: addl $28, %esp ; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%Y = call x86_fp80 @cosl(x86_fp80 %X) readonly %Y = call x86_fp80 @cosl(x86_fp80 %X) readonly
ret x86_fp80 %Y ret x86_fp80 %Y
} }

llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
declare void @bar() #0 declare void @bar() #0
declare void @baz() declare void @baz()
define void @test1(i32 %a) gc "statepoint-example" { define void @test1(i32 %a) gc "statepoint-example" {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: Ltmp0:
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
; We expect the argument to be passed in an extra register to bar ; We expect the argument to be passed in an extra register to bar
%statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a) %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
ret void ret void
} }
define void @test2(i32 %a, i32 %b) gc "statepoint-example" { define void @test2(i32 %a, i32 %b) gc "statepoint-example" {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: Lcfi4:
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: Lcfi5:
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: movl %esi, %ebx
; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: movl %edi, %ebp
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp1: ; CHECK-NEXT: Ltmp1:
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp2: ; CHECK-NEXT: Ltmp2:
; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %rbp ; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
; Because the first call clobbers esi, we have to move the values into ; Because the first call clobbers esi, we have to move the values into
; new registers. Note that they stay in the registers for both calls. ; new registers. Note that they stay in the registers for both calls.
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %a, i32 %b) call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %a, i32 %b)
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %b, i32 %a) call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %b, i32 %a)
ret void ret void
} }
define void @test3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) gc "statepoint-example" { define void @test3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) gc "statepoint-example" {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi6:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp3: ; CHECK-NEXT: Ltmp3:
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
; We directly reference the argument slot ; We directly reference the argument slot
%statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 9, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 9, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i)
ret void ret void
} }
; This case just confirms that we don't crash when given more live values ; This case just confirms that we don't crash when given more live values
; than registers. This is a case where we *have* to use a stack slot. This ; than registers. This is a case where we *have* to use a stack slot. This
; also ends up being a good test of whether we can fold loads from immutable ; also ends up being a good test of whether we can fold loads from immutable
; stack slots into the statepoint. ; stack slots into the statepoint.
define void @test4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) gc "statepoint-example" { define void @test4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) gc "statepoint-example" {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi7:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp4: ; CHECK-NEXT: Ltmp4:
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 26, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 26, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z)
ret void ret void
} }
; A live-through gc-value must be spilled even if it is also a live-in deopt ; A live-through gc-value must be spilled even if it is also a live-in deopt
; value. For live-in, we could technically report the register copy, but from ; value. For live-in, we could technically report the register copy, but from
; a code quality perspective it's better to reuse the required stack slot so ; a code quality perspective it's better to reuse the required stack slot so
; as to put less stress on the register allocator for no benefit. ; as to put less stress on the register allocator for no benefit.
define i32 addrspace(1)* @test5(i32 %a, i32 addrspace(1)* %p) gc "statepoint-example" { define i32 addrspace(1)* @test5(i32 %a, i32 addrspace(1)* %p) gc "statepoint-example" {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: Lcfi8:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq %rsi, (%rsp) ; CHECK-NEXT: movq %rsi, (%rsp)
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp5: ; CHECK-NEXT: Ltmp5:
; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: movq (%rsp), %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a, i32 addrspace(1)* %p, i32 addrspace(1)* %p) %token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a, i32 addrspace(1)* %p, i32 addrspace(1)* %p)
%p2 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 9, i32 9) %p2 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 9, i32 9)
ret i32 addrspace(1)* %p2 ret i32 addrspace(1)* %p2
} }
; Show the interaction of live-through spilling followed by live-in. ; Show the interaction of live-through spilling followed by live-in.
define void @test6(i32 %a) gc "statepoint-example" { define void @test6(i32 %a) gc "statepoint-example" {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: ## BB#0: ## %entry ; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: Lcfi9:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: subq $16, %rsp ; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: Lcfi10:
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: Lcfi11:
; CHECK-NEXT: .cfi_offset %rbx, -16 ; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movl %edi, %ebx ; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: callq _baz ; CHECK-NEXT: callq _baz
; CHECK-NEXT: Ltmp6: ; CHECK-NEXT: Ltmp6:
; CHECK-NEXT: callq _bar ; CHECK-NEXT: callq _bar
; CHECK-NEXT: Ltmp7: ; CHECK-NEXT: Ltmp7:
; CHECK-NEXT: addq $16, %rsp ; CHECK-NEXT: addq $16, %rsp
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llvm/trunk/test/CodeGen/X86/tls-pie.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
entry: entry:
ret i32* @i ret i32* @i
} }
define i32 @f3() { define i32 @f3() {
; X86-LABEL: f3: ; X86-LABEL: f3:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: calll .L2$pb ; X86-NEXT: calll .L2$pb
; X86-NEXT: .Lcfi0:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: .L2$pb: ; X86-NEXT: .L2$pb:
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: .Lcfi1:
; X86-NEXT: .cfi_adjust_cfa_offset -4 ; X86-NEXT: .cfi_adjust_cfa_offset -4
; X86-NEXT: .Ltmp0: ; X86-NEXT: .Ltmp0:
; X86-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L2$pb), %eax ; X86-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L2$pb), %eax
; X86-NEXT: movl i2@GOTNTPOFF(%eax), %eax ; X86-NEXT: movl i2@GOTNTPOFF(%eax), %eax
; X86-NEXT: movl %gs:(%eax), %eax ; X86-NEXT: movl %gs:(%eax), %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X32-LABEL: f3: ; X32-LABEL: f3:
Show All 11 Linesentry:
%tmp1 = load i32, i32* @i2 %tmp1 = load i32, i32* @i2
ret i32 %tmp1 ret i32 %tmp1
} }
define i32* @f4() { define i32* @f4() {
; X86-LABEL: f4: ; X86-LABEL: f4:
; X86: # BB#0: # %entry ; X86: # BB#0: # %entry
; X86-NEXT: calll .L3$pb ; X86-NEXT: calll .L3$pb
; X86-NEXT: .Lcfi2:
; X86-NEXT: .cfi_adjust_cfa_offset 4 ; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: .L3$pb: ; X86-NEXT: .L3$pb:
; X86-NEXT: popl %ecx ; X86-NEXT: popl %ecx
; X86-NEXT: .Lcfi3:
; X86-NEXT: .cfi_adjust_cfa_offset -4 ; X86-NEXT: .cfi_adjust_cfa_offset -4
; X86-NEXT: .Ltmp1: ; X86-NEXT: .Ltmp1:
; X86-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.L3$pb), %ecx ; X86-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.L3$pb), %ecx
; X86-NEXT: movl %gs:0, %eax ; X86-NEXT: movl %gs:0, %eax
; X86-NEXT: addl i2@GOTNTPOFF(%ecx), %eax ; X86-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X32-LABEL: f4: ; X32-LABEL: f4:
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llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll

Show All 33 Linesif.end: ; preds = %if.then, %entry
%tmp1 = phi i32 [ 0, %entry ], [ %.pre, %if.then ] %tmp1 = phi i32 [ 0, %entry ], [ %.pre, %if.then ]
ret i32 %tmp1 ret i32 %tmp1
} }
; CHECK: g: # @g ; CHECK: g: # @g
; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: # BB#0: # %entry ; CHECK-NEXT: # BB#0: # %entry
; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: data16 ; CHECK-NEXT: data16
; CHECK-NEXT: leaq i@TLSGD(%rip), %rdi ; CHECK-NEXT: leaq i@TLSGD(%rip), %rdi
declare void @f(...) #1 declare void @f(...) #1
attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind } attributes #2 = { nounwind }

llvm/trunk/test/CodeGen/X86/vector-sext.ll

Show First 20 Lines • Show All 3,246 Lines • ▼ Show 20 Lines
; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE41-NEXT: psllw $15, %xmm1 ; SSE41-NEXT: psllw $15, %xmm1
; SSE41-NEXT: psraw $15, %xmm1 ; SSE41-NEXT: psraw $15, %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: load_sext_16i1_to_16i16: ; AVX1-LABEL: load_sext_16i1_to_16i16:
; AVX1: # BB#0: # %entry ; AVX1: # BB#0: # %entry
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi0:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: pushq %r15 ; AVX1-NEXT: pushq %r15
; AVX1-NEXT: .Lcfi1:
; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: .cfi_def_cfa_offset 24
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: .Lcfi2:
; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX1-NEXT: pushq %r13 ; AVX1-NEXT: pushq %r13
; AVX1-NEXT: .Lcfi3:
; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: .cfi_def_cfa_offset 40
; AVX1-NEXT: pushq %r12 ; AVX1-NEXT: pushq %r12
; AVX1-NEXT: .Lcfi4:
; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: .cfi_def_cfa_offset 48
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: .Lcfi5:
; AVX1-NEXT: .cfi_def_cfa_offset 56 ; AVX1-NEXT: .cfi_def_cfa_offset 56
; AVX1-NEXT: .Lcfi6:
; AVX1-NEXT: .cfi_offset %rbx, -56 ; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi7:
; AVX1-NEXT: .cfi_offset %r12, -48 ; AVX1-NEXT: .cfi_offset %r12, -48
; AVX1-NEXT: .Lcfi8:
; AVX1-NEXT: .cfi_offset %r13, -40 ; AVX1-NEXT: .cfi_offset %r13, -40
; AVX1-NEXT: .Lcfi9:
; AVX1-NEXT: .cfi_offset %r14, -32 ; AVX1-NEXT: .cfi_offset %r14, -32
; AVX1-NEXT: .Lcfi10:
; AVX1-NEXT: .cfi_offset %r15, -24 ; AVX1-NEXT: .cfi_offset %r15, -24
; AVX1-NEXT: .Lcfi11:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movswq (%rdi), %rax ; AVX1-NEXT: movswq (%rdi), %rax
; AVX1-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shlq $55, %rcx ; AVX1-NEXT: shlq $55, %rcx
; AVX1-NEXT: sarq $63, %rcx ; AVX1-NEXT: sarq $63, %rcx
; AVX1-NEXT: vmovd %ecx, %xmm0 ; AVX1-NEXT: vmovd %ecx, %xmm0
; AVX1-NEXT: movq %rax, %r8 ; AVX1-NEXT: movq %rax, %r8
; AVX1-NEXT: movq %rax, %r10 ; AVX1-NEXT: movq %rax, %r10
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: load_sext_16i1_to_16i16: ; AVX2-LABEL: load_sext_16i1_to_16i16:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
; AVX2-NEXT: .Lcfi1:
; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: .cfi_def_cfa_offset 24
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: .Lcfi2:
; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: .cfi_def_cfa_offset 32
; AVX2-NEXT: pushq %r13 ; AVX2-NEXT: pushq %r13
; AVX2-NEXT: .Lcfi3:
; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: .cfi_def_cfa_offset 40
; AVX2-NEXT: pushq %r12 ; AVX2-NEXT: pushq %r12
; AVX2-NEXT: .Lcfi4:
; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: .cfi_def_cfa_offset 48
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: .Lcfi5:
; AVX2-NEXT: .cfi_def_cfa_offset 56 ; AVX2-NEXT: .cfi_def_cfa_offset 56
; AVX2-NEXT: .Lcfi6:
; AVX2-NEXT: .cfi_offset %rbx, -56 ; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi7:
; AVX2-NEXT: .cfi_offset %r12, -48 ; AVX2-NEXT: .cfi_offset %r12, -48
; AVX2-NEXT: .Lcfi8:
; AVX2-NEXT: .cfi_offset %r13, -40 ; AVX2-NEXT: .cfi_offset %r13, -40
; AVX2-NEXT: .Lcfi9:
; AVX2-NEXT: .cfi_offset %r14, -32 ; AVX2-NEXT: .cfi_offset %r14, -32
; AVX2-NEXT: .Lcfi10:
; AVX2-NEXT: .cfi_offset %r15, -24 ; AVX2-NEXT: .cfi_offset %r15, -24
; AVX2-NEXT: .Lcfi11:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movswq (%rdi), %rax ; AVX2-NEXT: movswq (%rdi), %rax
; AVX2-NEXT: movq %rax, %rcx ; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shlq $55, %rcx ; AVX2-NEXT: shlq $55, %rcx
; AVX2-NEXT: sarq $63, %rcx ; AVX2-NEXT: sarq $63, %rcx
; AVX2-NEXT: vmovd %ecx, %xmm0 ; AVX2-NEXT: vmovd %ecx, %xmm0
; AVX2-NEXT: movq %rax, %r8 ; AVX2-NEXT: movq %rax, %r8
; AVX2-NEXT: movq %rax, %r10 ; AVX2-NEXT: movq %rax, %r10
▲ Show 20 Lines • Show All 1,445 Lines • ▼ Show 20 Lines
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpmovsxbw %xmm0, %xmm0 ; AVX-NEXT: vpmovsxbw %xmm0, %xmm0
; AVX-NEXT: vmovd %xmm0, %eax ; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE41-LABEL: sext_2i8_to_i32: ; X32-SSE41-LABEL: sext_2i8_to_i32:
; X32-SSE41: # BB#0: # %entry ; X32-SSE41: # BB#0: # %entry
; X32-SSE41-NEXT: pushl %eax ; X32-SSE41-NEXT: pushl %eax
; X32-SSE41-NEXT: .Lcfi0:
; X32-SSE41-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE41-NEXT: .cfi_def_cfa_offset 8
; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0 ; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0
; X32-SSE41-NEXT: movd %xmm0, %eax ; X32-SSE41-NEXT: movd %xmm0, %eax
; X32-SSE41-NEXT: popl %ecx ; X32-SSE41-NEXT: popl %ecx
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
entry: entry:
%Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1> %Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%Ex = sext <2 x i8> %Shuf to <2 x i16> %Ex = sext <2 x i8> %Shuf to <2 x i16>
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-avx512.ll

Show First 20 Lines • Show All 602 Lines • ▼ Show 20 Lines
; SKX32-NEXT: kmovd %eax, %k0 ; SKX32-NEXT: kmovd %eax, %k0
; SKX32-NEXT: kunpckdq %k0, %k0, %k1 ; SKX32-NEXT: kunpckdq %k0, %k0, %k1
; SKX32-NEXT: vpblendmb %zmm0, %zmm1, %zmm0 {%k1} ; SKX32-NEXT: vpblendmb %zmm0, %zmm1, %zmm0 {%k1}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: test_mm512_mask_blend_epi8: ; KNL32-LABEL: test_mm512_mask_blend_epi8:
; KNL32: # BB#0: # %entry ; KNL32: # BB#0: # %entry
; KNL32-NEXT: pushl %ebp ; KNL32-NEXT: pushl %ebp
; KNL32-NEXT: .Lcfi0:
; KNL32-NEXT: .cfi_def_cfa_offset 8 ; KNL32-NEXT: .cfi_def_cfa_offset 8
; KNL32-NEXT: .Lcfi1:
; KNL32-NEXT: .cfi_offset %ebp, -8 ; KNL32-NEXT: .cfi_offset %ebp, -8
; KNL32-NEXT: movl %esp, %ebp ; KNL32-NEXT: movl %esp, %ebp
; KNL32-NEXT: .Lcfi2:
; KNL32-NEXT: .cfi_def_cfa_register %ebp ; KNL32-NEXT: .cfi_def_cfa_register %ebp
; KNL32-NEXT: andl $-32, %esp ; KNL32-NEXT: andl $-32, %esp
; KNL32-NEXT: subl $32, %esp ; KNL32-NEXT: subl $32, %esp
; KNL32-NEXT: vpbroadcastw {{.*#+}} ymm3 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; KNL32-NEXT: vpbroadcastw {{.*#+}} ymm3 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; KNL32-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0 ; KNL32-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0
; KNL32-NEXT: vpblendvb %ymm3, 8(%ebp), %ymm1, %ymm1 ; KNL32-NEXT: vpblendvb %ymm3, 8(%ebp), %ymm1, %ymm1
; KNL32-NEXT: movl %ebp, %esp ; KNL32-NEXT: movl %ebp, %esp
; KNL32-NEXT: popl %ebp ; KNL32-NEXT: popl %ebp
Show All 22 Lines
; SKX32-NEXT: movl $-1431655766, %eax # imm = 0xAAAAAAAA ; SKX32-NEXT: movl $-1431655766, %eax # imm = 0xAAAAAAAA
; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: kmovd %eax, %k1
; SKX32-NEXT: vpblendmw %zmm0, %zmm1, %zmm0 {%k1} ; SKX32-NEXT: vpblendmw %zmm0, %zmm1, %zmm0 {%k1}
; SKX32-NEXT: retl ; SKX32-NEXT: retl
; ;
; KNL32-LABEL: test_mm512_mask_blend_epi16: ; KNL32-LABEL: test_mm512_mask_blend_epi16:
; KNL32: # BB#0: # %entry ; KNL32: # BB#0: # %entry
; KNL32-NEXT: pushl %ebp ; KNL32-NEXT: pushl %ebp
; KNL32-NEXT: .Lcfi3:
; KNL32-NEXT: .cfi_def_cfa_offset 8 ; KNL32-NEXT: .cfi_def_cfa_offset 8
; KNL32-NEXT: .Lcfi4:
; KNL32-NEXT: .cfi_offset %ebp, -8 ; KNL32-NEXT: .cfi_offset %ebp, -8
; KNL32-NEXT: movl %esp, %ebp ; KNL32-NEXT: movl %esp, %ebp
; KNL32-NEXT: .Lcfi5:
; KNL32-NEXT: .cfi_def_cfa_register %ebp ; KNL32-NEXT: .cfi_def_cfa_register %ebp
; KNL32-NEXT: andl $-32, %esp ; KNL32-NEXT: andl $-32, %esp
; KNL32-NEXT: subl $32, %esp ; KNL32-NEXT: subl $32, %esp
; KNL32-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2],ymm0[3],ymm2[4],ymm0[5],ymm2[6],ymm0[7],ymm2[8],ymm0[9],ymm2[10],ymm0[11],ymm2[12],ymm0[13],ymm2[14],ymm0[15] ; KNL32-NEXT: vpblendw {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2],ymm0[3],ymm2[4],ymm0[5],ymm2[6],ymm0[7],ymm2[8],ymm0[9],ymm2[10],ymm0[11],ymm2[12],ymm0[13],ymm2[14],ymm0[15]
; KNL32-NEXT: vpblendw {{.*#+}} ymm1 = mem[0],ymm1[1],mem[2],ymm1[3],mem[4],ymm1[5],mem[6],ymm1[7],mem[8],ymm1[9],mem[10],ymm1[11],mem[12],ymm1[13],mem[14],ymm1[15] ; KNL32-NEXT: vpblendw {{.*#+}} ymm1 = mem[0],ymm1[1],mem[2],ymm1[3],mem[4],ymm1[5],mem[6],ymm1[7],mem[8],ymm1[9],mem[10],ymm1[11],mem[12],ymm1[13],mem[14],ymm1[15]
; KNL32-NEXT: movl %ebp, %esp ; KNL32-NEXT: movl %ebp, %esp
; KNL32-NEXT: popl %ebp ; KNL32-NEXT: popl %ebp
; KNL32-NEXT: retl ; KNL32-NEXT: retl
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll

Show All 26 Linesentry:
store <1 x i64> %tmp10, <1 x i64>* %x store <1 x i64> %tmp10, <1 x i64>* %x
ret void ret void
} }
define void @test1() { define void @test1() {
; X32-LABEL: test1: ; X32-LABEL: test1:
; X32: ## BB#0: ## %entry ; X32: ## BB#0: ## %entry
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: subl $16, %esp ; X32-NEXT: subl $16, %esp
; X32-NEXT: Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 24 ; X32-NEXT: .cfi_def_cfa_offset 24
; X32-NEXT: Lcfi2:
; X32-NEXT: .cfi_offset %edi, -8 ; X32-NEXT: .cfi_offset %edi, -8
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movlps %xmm0, (%esp) ; X32-NEXT: movlps %xmm0, (%esp)
; X32-NEXT: movq (%esp), %mm0 ; X32-NEXT: movq (%esp), %mm0
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: movq {{[0-9]+}}(%esp), %mm1 ; X32-NEXT: movq {{[0-9]+}}(%esp), %mm1
; X32-NEXT: xorl %edi, %edi ; X32-NEXT: xorl %edi, %edi
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll

Show First 20 Lines • Show All 598 Lines • ▼ Show 20 Lines; VL_BW_DQ-NEXT: retq
%d = bitcast <16 x i1> %c to i16 %d = bitcast <16 x i1> %c to i16
ret i16 %d ret i16 %d
} }
define i64 @shuf64i1_zero(i64 %a) { define i64 @shuf64i1_zero(i64 %a) {
; AVX512F-LABEL: shuf64i1_zero: ; AVX512F-LABEL: shuf64i1_zero:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp ; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: .Lcfi0:
; AVX512F-NEXT: .cfi_def_cfa_offset 16 ; AVX512F-NEXT: .cfi_def_cfa_offset 16
; AVX512F-NEXT: .Lcfi1:
; AVX512F-NEXT: .cfi_offset %rbp, -16 ; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp ; AVX512F-NEXT: movq %rsp, %rbp
; AVX512F-NEXT: .Lcfi2:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp ; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp ; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $96, %rsp ; AVX512F-NEXT: subq $96, %rsp
; AVX512F-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX512F-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX512F-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512F-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
; AVX512F-NEXT: vpbroadcastb %xmm0, %ymm0 ; AVX512F-NEXT: vpbroadcastb %xmm0, %ymm0
Show All 13 Lines
; AVX512F-NEXT: movq %rbp, %rsp ; AVX512F-NEXT: movq %rbp, %rsp
; AVX512F-NEXT: popq %rbp ; AVX512F-NEXT: popq %rbp
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: shuf64i1_zero: ; AVX512VL-LABEL: shuf64i1_zero:
; AVX512VL: # BB#0: ; AVX512VL: # BB#0:
; AVX512VL-NEXT: pushq %rbp ; AVX512VL-NEXT: pushq %rbp
; AVX512VL-NEXT: .Lcfi0:
; AVX512VL-NEXT: .cfi_def_cfa_offset 16 ; AVX512VL-NEXT: .cfi_def_cfa_offset 16
; AVX512VL-NEXT: .Lcfi1:
; AVX512VL-NEXT: .cfi_offset %rbp, -16 ; AVX512VL-NEXT: .cfi_offset %rbp, -16
; AVX512VL-NEXT: movq %rsp, %rbp ; AVX512VL-NEXT: movq %rsp, %rbp
; AVX512VL-NEXT: .Lcfi2:
; AVX512VL-NEXT: .cfi_def_cfa_register %rbp ; AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; AVX512VL-NEXT: andq $-32, %rsp ; AVX512VL-NEXT: andq $-32, %rsp
; AVX512VL-NEXT: subq $96, %rsp ; AVX512VL-NEXT: subq $96, %rsp
; AVX512VL-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX512VL-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX512VL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1 ; AVX512VL-NEXT: kmovw {{[0-9]+}}(%rsp), %k1
; AVX512VL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512VL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512VL-NEXT: vpmovdb %zmm0, %xmm0
; AVX512VL-NEXT: vpbroadcastb %xmm0, %ymm0 ; AVX512VL-NEXT: vpbroadcastb %xmm0, %ymm0
Show All 32 Lines

llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=bdver2 -mattr=-fma -mtriple=i686-apple-darwin < %s | FileCheck %s ; RUN: llc -mcpu=bdver2 -mattr=-fma -mtriple=i686-apple-darwin < %s | FileCheck %s
; RUN: llc -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=i686-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA ; RUN: llc -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=i686-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
; CHECK-LABEL: fmafunc ; CHECK-LABEL: fmafunc
; CHECK-NOFMA-LABEL: fmafunc ; CHECK-NOFMA-LABEL: fmafunc
define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) { define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
; CHECK-LABEL: fmafunc: ; CHECK-LABEL: fmafunc:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-32, %esp ; CHECK-NEXT: andl $-32, %esp
; CHECK-NEXT: subl $32, %esp ; CHECK-NEXT: subl $32, %esp
; CHECK-NEXT: vfmaddps 8(%ebp), %ymm2, %ymm0, %ymm0 ; CHECK-NEXT: vfmaddps 8(%ebp), %ymm2, %ymm0, %ymm0
; CHECK-NEXT: vfmaddps 40(%ebp), %ymm3, %ymm1, %ymm1 ; CHECK-NEXT: vfmaddps 40(%ebp), %ymm3, %ymm1, %ymm1
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; CHECK-NOFMA-LABEL: fmafunc: ; CHECK-NOFMA-LABEL: fmafunc:
; CHECK-NOFMA: ## BB#0: ; CHECK-NOFMA: ## BB#0:
; CHECK-NOFMA-NEXT: pushl %ebp ; CHECK-NOFMA-NEXT: pushl %ebp
; CHECK-NOFMA-NEXT: Lcfi0:
; CHECK-NOFMA-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NOFMA-NEXT: .cfi_def_cfa_offset 8
; CHECK-NOFMA-NEXT: Lcfi1:
; CHECK-NOFMA-NEXT: .cfi_offset %ebp, -8 ; CHECK-NOFMA-NEXT: .cfi_offset %ebp, -8
; CHECK-NOFMA-NEXT: movl %esp, %ebp ; CHECK-NOFMA-NEXT: movl %esp, %ebp
; CHECK-NOFMA-NEXT: Lcfi2:
; CHECK-NOFMA-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NOFMA-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NOFMA-NEXT: andl $-32, %esp ; CHECK-NOFMA-NEXT: andl $-32, %esp
; CHECK-NOFMA-NEXT: subl $32, %esp ; CHECK-NOFMA-NEXT: subl $32, %esp
; CHECK-NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; CHECK-NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0
; CHECK-NOFMA-NEXT: vaddps 8(%ebp), %ymm0, %ymm0 ; CHECK-NOFMA-NEXT: vaddps 8(%ebp), %ymm0, %ymm0
; CHECK-NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1 ; CHECK-NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1
; CHECK-NOFMA-NEXT: vaddps 40(%ebp), %ymm1, %ymm1 ; CHECK-NOFMA-NEXT: vaddps 40(%ebp), %ymm1, %ymm1
; CHECK-NOFMA-NEXT: movl %ebp, %esp ; CHECK-NOFMA-NEXT: movl %ebp, %esp
Show All 9 Lines

llvm/trunk/test/CodeGen/X86/wide-integer-cmp.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%res = select i1 %cmp, i32 1, i32 0 %res = select i1 %cmp, i32 1, i32 0
ret i32 %res ret i32 %res
} }
define i32 @test_wide(i128 %a, i128 %b) { define i32 @test_wide(i128 %a, i128 %b) {
; CHECK-LABEL: test_wide: ; CHECK-LABEL: test_wide:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll

; RUN: llc < %s -relocation-model=pic | FileCheck %s ; RUN: llc < %s -relocation-model=pic | FileCheck %s
; CHECK: calll L0$pb ; CHECK: calll L0$pb
; CHECK-NEXT: Lcfi{{[0-9]+}}:
; CHECK-NEXT: .cfi_adjust_cfa_offset 4 ; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: L0$pb: ; CHECK-NEXT: L0$pb:
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: Lcfi{{[0-9]+}}:
; CHECK-NEXT: .cfi_adjust_cfa_offset -4 ; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: addl LJTI0_0(,%ecx,4), %eax ; CHECK-NEXT: addl LJTI0_0(,%ecx,4), %eax
; CHECK-NEXT: jmpl *%eax ; CHECK-NEXT: jmpl *%eax
; CHECK: LJTI0_0: ; CHECK: LJTI0_0:
; CHECK-NEXT: .long LBB0_2-L0$pb ; CHECK-NEXT: .long LBB0_2-L0$pb
; CHECK-NEXT: .long LBB0_3-L0$pb ; CHECK-NEXT: .long LBB0_3-L0$pb
; CHECK-NEXT: .long LBB0_4-L0$pb ; CHECK-NEXT: .long LBB0_4-L0$pb
Show All 24 Lines

llvm/trunk/test/CodeGen/X86/x86-interleaved-access.ll

Show First 20 Lines • Show All 1,683 Lines • ▼ Show 20 Lines
%add2 = add <64 x i8> %v3, %add1 %add2 = add <64 x i8> %v3, %add1
ret <64 x i8> %add2 ret <64 x i8> %add2
} }
define void @interleaved_store_vf64_i8_stride4(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c,<64 x i8> %d, <256 x i8>* %p) { define void @interleaved_store_vf64_i8_stride4(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c,<64 x i8> %d, <256 x i8>* %p) {
; AVX1-LABEL: interleaved_store_vf64_i8_stride4: ; AVX1-LABEL: interleaved_store_vf64_i8_stride4:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: subq $24, %rsp ; AVX1-NEXT: subq $24, %rsp
; AVX1-NEXT: .Lcfi0:
; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; AVX1-NEXT: vmovdqa %xmm8, -{{[0-9]+}}(%rsp) # 16-byte Spill ; AVX1-NEXT: vmovdqa %xmm8, -{{[0-9]+}}(%rsp) # 16-byte Spill
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm11 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm11
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm12 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm12
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm10 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3],xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm10 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3],xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7]
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm13 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm13
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py for function "bar" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py for function "bar"
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
;; In functions with 'no_caller_saved_registers' attribute, all registers should ;; In functions with 'no_caller_saved_registers' attribute, all registers should
;; be preserved except for registers used for passing/returning arguments. ;; be preserved except for registers used for passing/returning arguments.
;; In the following function registers %RDI, %RSI and %XMM0 are used to store ;; In the following function registers %RDI, %RSI and %XMM0 are used to store
;; arguments %a0, %a1 and %b0 accordingally. The value is returned in %RAX. ;; arguments %a0, %a1 and %b0 accordingally. The value is returned in %RAX.
;; The above registers should not be preserved, however other registers ;; The above registers should not be preserved, however other registers
;; (that are modified by the function) should be preserved (%RDX and %XMM1). ;; (that are modified by the function) should be preserved (%RDX and %XMM1).
define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 { define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushq %rdx ; CHECK-NEXT: pushq %rdx
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %rdx, -16 ; CHECK-NEXT: .cfi_offset %rdx, -16
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_offset %xmm1, -32 ; CHECK-NEXT: .cfi_offset %xmm1, -32
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movl $4, %eax ; CHECK-NEXT: movl $4, %eax
; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: popq %rdx ; CHECK-NEXT: popq %rdx
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void asm sideeffect "", "~{rax},~{rdx},~{xmm1},~{rdi},~{rsi},~{xmm0}"() call void asm sideeffect "", "~{rax},~{rdx},~{xmm1},~{rdi},~{rsi},~{xmm0}"()
Show All 27 Lines

llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Linesentry:
call void @f2() call void @f2()
ret i32 %i ret i32 %i
} }
; FP + large frame: spill FP+SR = entsp 2 + 100000 ; FP + large frame: spill FP+SR = entsp 2 + 100000
; CHECKFP-LABEL: f4: ; CHECKFP-LABEL: f4:
; CHECKFP: entsp 65535 ; CHECKFP: entsp 65535
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140 ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 15, 0 ; CHECKFP-NEXT: .cfi_offset 15, 0
; CHECKFP-NEXT: extsp 34467 ; CHECKFP-NEXT: extsp 34467
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 400008 ; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: stw r10, sp[1]
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 10, -400004 ; CHECKFP-NEXT: .cfi_offset 10, -400004
; CHECKFP-NEXT: ldaw r10, sp[0] ; CHECKFP-NEXT: ldaw r10, sp[0]
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_register 10 ; CHECKFP-NEXT: .cfi_def_cfa_register 10
; CHECKFP-NEXT: set sp, r10 ; CHECKFP-NEXT: set sp, r10
; CHECKFP-NEXT: ldw r10, sp[1] ; CHECKFP-NEXT: ldw r10, sp[1]
; CHECKFP-NEXT: ldaw sp, sp[65535] ; CHECKFP-NEXT: ldaw sp, sp[65535]
; CHECKFP-NEXT: retsp 34467 ; CHECKFP-NEXT: retsp 34467
; ;
; !FP + large frame: spill SR+SR = entsp 2 + 100000 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
; CHECK-LABEL: f4: ; CHECK-LABEL: f4:
; CHECK: entsp 65535 ; CHECK: entsp 65535
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 262140 ; CHECK-NEXT: .cfi_def_cfa_offset 262140
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 15, 0 ; CHECK-NEXT: .cfi_offset 15, 0
; CHECK-NEXT: extsp 34467 ; CHECK-NEXT: extsp 34467
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 400008 ; CHECK-NEXT: .cfi_def_cfa_offset 400008
; CHECK-NEXT: ldaw sp, sp[65535] ; CHECK-NEXT: ldaw sp, sp[65535]
; CHECK-NEXT: retsp 34467 ; CHECK-NEXT: retsp 34467
define void @f4() { define void @f4() {
entry: entry:
%0 = alloca [100000 x i32] %0 = alloca [100000 x i32]
ret void ret void
} }
; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1 ; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
; CHECKFP: .section .cp.rodata.cst4,"aMc",@progbits,4 ; CHECKFP: .section .cp.rodata.cst4,"aMc",@progbits,4
; CHECKFP-NEXT: .p2align 2 ; CHECKFP-NEXT: .p2align 2
; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]: ; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]:
; CHECKFP-NEXT: .long 200002 ; CHECKFP-NEXT: .long 200002
; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]: ; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]:
; CHECKFP-NEXT: .long 200001 ; CHECKFP-NEXT: .long 200001
; CHECKFP-NEXT: .text ; CHECKFP-NEXT: .text
; CHECKFP-LABEL: f6: ; CHECKFP-LABEL: f6:
; CHECKFP: entsp 65535 ; CHECKFP: entsp 65535
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140 ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 15, 0 ; CHECKFP-NEXT: .cfi_offset 15, 0
; CHECKFP-NEXT: extsp 65535 ; CHECKFP-NEXT: extsp 65535
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 524280 ; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
; CHECKFP-NEXT: extsp 65535 ; CHECKFP-NEXT: extsp 65535
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 786420 ; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
; CHECKFP-NEXT: extsp 3398 ; CHECKFP-NEXT: extsp 3398
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 800012 ; CHECKFP-NEXT: .cfi_def_cfa_offset 800012
; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: stw r10, sp[1]
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 10, -800008 ; CHECKFP-NEXT: .cfi_offset 10, -800008
; CHECKFP-NEXT: ldaw r10, sp[0] ; CHECKFP-NEXT: ldaw r10, sp[0]
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_register 10 ; CHECKFP-NEXT: .cfi_def_cfa_register 10
; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]] ; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1] ; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 4, -4 ; CHECKFP-NEXT: .cfi_offset 4, -4
; CHECKFP-NEXT: mov [[REG]], r0 ; CHECKFP-NEXT: mov [[REG]], r0
; CHECKFP-NEXT: extsp 1 ; CHECKFP-NEXT: extsp 1
; CHECKFP-NEXT: ldaw r0, r10[2] ; CHECKFP-NEXT: ldaw r0, r10[2]
; CHECKFP-NEXT: bl f5 ; CHECKFP-NEXT: bl f5
; CHECKFP-NEXT: ldaw sp, sp[1] ; CHECKFP-NEXT: ldaw sp, sp[1]
; CHECKFP-NEXT: ldw r1, cp[.LCPI3_1] ; CHECKFP-NEXT: ldw r1, cp[.LCPI3_1]
; CHECKFP-NEXT: ldaw r0, r10[r1] ; CHECKFP-NEXT: ldaw r0, r10[r1]
Show All 15 Lines
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]: ; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]:
; CHECK-NEXT: .long 200003 ; CHECK-NEXT: .long 200003
; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]: ; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]:
; CHECK-NEXT: .long 200002 ; CHECK-NEXT: .long 200002
; CHECK-NEXT: .text ; CHECK-NEXT: .text
; CHECK-LABEL: f6: ; CHECK-LABEL: f6:
; CHECK: entsp 65535 ; CHECK: entsp 65535
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 262140 ; CHECK-NEXT: .cfi_def_cfa_offset 262140
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 15, 0 ; CHECK-NEXT: .cfi_offset 15, 0
; CHECK-NEXT: extsp 65535 ; CHECK-NEXT: extsp 65535
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 524280 ; CHECK-NEXT: .cfi_def_cfa_offset 524280
; CHECK-NEXT: extsp 65535 ; CHECK-NEXT: extsp 65535
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 786420 ; CHECK-NEXT: .cfi_def_cfa_offset 786420
; CHECK-NEXT: extsp 3399 ; CHECK-NEXT: extsp 3399
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 800016 ; CHECK-NEXT: .cfi_def_cfa_offset 800016
; CHECK-NEXT: ldaw r1, sp[0] ; CHECK-NEXT: ldaw r1, sp[0]
; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]] ; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]]
; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2] ; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 4, -4 ; CHECK-NEXT: .cfi_offset 4, -4
; CHECK-NEXT: mov [[REG]], r0 ; CHECK-NEXT: mov [[REG]], r0
; CHECK-NEXT: ldaw r0, sp[3] ; CHECK-NEXT: ldaw r0, sp[3]
; CHECK-NEXT: bl f5 ; CHECK-NEXT: bl f5
; CHECK-NEXT: ldaw r0, sp[0] ; CHECK-NEXT: ldaw r0, sp[0]
; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST1]]] ; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST1]]]
; CHECK-NEXT: ldaw r0, r0[r1] ; CHECK-NEXT: ldaw r0, r0[r1]
; CHECK-NEXT: bl f5 ; CHECK-NEXT: bl f5
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llvm/trunk/test/MC/AsmParser/seh-unfinished-frame.s

// RUN: not llvm-mc -filetype=asm -triple x86_64-windows %s -o %t 2>%t.out
// RUN: FileCheck -input-file=%t.out %s
foo:
.seh_proc foo
// CHECK: Unfinished frame

llvm/trunk/test/tools/llvm-dwarfdump/X86/brief.s

Show All 34 Lines# and that the .debug_line table is printed rather than the opcodes.
.p2align 4, 0x90 .p2align 4, 0x90
_main: ## @main _main: ## @main
Lfunc_begin0: Lfunc_begin0:
.file 1 "brief.c" .file 1 "brief.c"
.loc 1 1 0 ## brief.c:1:0 .loc 1 1 0 ## brief.c:1:0
.cfi_startproc .cfi_startproc
## BB#0: ## %entry ## BB#0: ## %entry
pushq %rbp pushq %rbp
Lcfi0:
.cfi_def_cfa_offset 16 .cfi_def_cfa_offset 16
Lcfi1:
.cfi_offset %rbp, -16 .cfi_offset %rbp, -16
movq %rsp, %rbp movq %rsp, %rbp
Lcfi2:
.cfi_def_cfa_register %rbp .cfi_def_cfa_register %rbp
xorl %eax, %eax xorl %eax, %eax
Ltmp0: Ltmp0:
.loc 1 1 12 prologue_end ## brief.c:1:12 .loc 1 1 12 prologue_end ## brief.c:1:12
popq %rbp popq %rbp
retq retq
Ltmp1: Ltmp1:
Lfunc_end0: Lfunc_end0:
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/trunk/test/tools/llvm-dwarfdump/X86/verify_debug_info.s

Show All 22 Lines# CHECK-NEXT: note: The unit type encoding is not valid.
.p2align 4, 0x90 .p2align 4, 0x90
_main: ## @main _main: ## @main
Lfunc_begin0: Lfunc_begin0:
.file 1 "basic.c" .file 1 "basic.c"
.loc 1 1 0 ## basic.c:1:0 .loc 1 1 0 ## basic.c:1:0
.cfi_startproc .cfi_startproc
## BB#0: ## %entry ## BB#0: ## %entry
pushq %rbp pushq %rbp
Lcfi0:
.cfi_def_cfa_offset 16 .cfi_def_cfa_offset 16
Lcfi1:
.cfi_offset %rbp, -16 .cfi_offset %rbp, -16
movq %rsp, %rbp movq %rsp, %rbp
Lcfi2:
.cfi_def_cfa_register %rbp .cfi_def_cfa_register %rbp
xorl %eax, %eax xorl %eax, %eax
movl $0, -4(%rbp) movl $0, -4(%rbp)
Ltmp0: Ltmp0:
.loc 1 2 7 prologue_end ## basic.c:2:7 .loc 1 2 7 prologue_end ## basic.c:2:7
movl $1, -8(%rbp) movl $1, -8(%rbp)
.loc 1 3 3 ## basic.c:3:3 .loc 1 3 3 ## basic.c:3:3
popq %rbp popq %rbp
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

llvm/trunk/test/tools/llvm-dwarfdump/X86/verify_die_ranges.s

Show All 10 Lines# CHECK-NEXT: error: Invalid address range [0x0000000000000007, 0x0000000000000006)
.p2align 4, 0x90 .p2align 4, 0x90
_foo: ## @foo _foo: ## @foo
Lfunc_begin0: Lfunc_begin0:
.file 1 "basic.c" .file 1 "basic.c"
.loc 1 1 0 ## basic.c:1:0 .loc 1 1 0 ## basic.c:1:0
.cfi_startproc .cfi_startproc
## BB#0: ## %entry ## BB#0: ## %entry
pushq %rbp pushq %rbp
Lcfi0:
.cfi_def_cfa_offset 16 .cfi_def_cfa_offset 16
Lcfi1:
.cfi_offset %rbp, -16 .cfi_offset %rbp, -16
movq %rsp, %rbp movq %rsp, %rbp
Lcfi2:
.cfi_def_cfa_register %rbp .cfi_def_cfa_register %rbp
Ltmp0: Ltmp0:
.loc 1 1 17 prologue_end ## basic.c:1:17 .loc 1 1 17 prologue_end ## basic.c:1:17
popq %rbp popq %rbp
retq retq
Ltmp1: Ltmp1:
Lfunc_end0: Lfunc_end0:
.cfi_endproc .cfi_endproc
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