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Differential D38620

[mips] Add support for parsing target specific flags for MIR
ClosedPublic

Authored by sdardis on Oct 6 2017, 5:02 AM.

Details

Reviewers
atanasyan
Commits
rG41851e35468b: [mips] Add support for parsing target specific flags for MIR
rL315451: [mips] Add support for parsing target specific flags for MIR

Diff Detail

Event Timeline

sdardis created this revision.Oct 6 2017, 5:02 AM
Herald added a subscriber: arichardson. · View Herald TranscriptOct 6 2017, 5:02 AM
atanasyan accepted this revision.Oct 10 2017, 3:45 AM

LGTM

This revision is now accepted and ready to land.Oct 10 2017, 3:45 AM
Closed by commit rL315451: [mips] Add support for parsing target specific flags for MIR (authored by sdardis). · Explain WhyOct 11 2017, 4:11 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
6 lines
36 lines
test/
CodeGen/
Mips/
mirparser/
275 lines
95 lines
98 lines
236 lines

Diff 117972

lib/Target/Mips/MipsInstrInfo.h

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Linespublic:
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const override; unsigned &SrcOpIdx2) const override;
/// Perform target specific instruction verification. /// Perform target specific instruction verification.
bool verifyInstruction(const MachineInstr &MI, bool verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const override; StringRef &ErrInfo) const override;
std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const override;
protected: protected:
bool isZeroImm(const MachineOperand &op) const; bool isZeroImm(const MachineOperand &op) const;
MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
MachineMemOperand::Flags Flags) const; MachineMemOperand::Flags Flags) const;
private: private:
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
Show All 16 Lines

lib/Target/Mips/MipsInstrInfo.cpp

Show First 20 Lines • Show All 612 Lines • ▼ Show 20 Lines case Mips::DEXTU_MM64R6:
return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
default: default:
return true; return true;
} }
return true; return true;
} }
std::pair<unsigned, unsigned>
MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
return std::make_pair(TF, 0u);
}
ArrayRef<std::pair<unsigned, const char*>>
MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
using namespace MipsII;
static const std::pair<unsigned, const char*> Flags[] = {
{MO_GOT, "mips-got"},
{MO_GOT_CALL, "mips-got-call"},
{MO_GPREL, "mips-gprel"},
{MO_ABS_HI, "mips-abs-hi"},
{MO_ABS_LO, "mips-abs-lo"},
{MO_TLSGD, "mips-tlsgd"},
{MO_TLSLDM, "mips-tlsldm"},
{MO_DTPREL_HI, "mips-dtprel-hi"},
{MO_DTPREL_LO, "mips-dtprel-lo"},
{MO_GOTTPREL, "mips-gottprel"},
{MO_TPREL_HI, "mips-tprel-hi"},
{MO_TPREL_LO, "mips-tprel-lo"},
{MO_GPOFF_HI, "mips-gpoff-hi"},
{MO_GPOFF_LO, "mips-gpoff-lo"},
{MO_GOT_DISP, "mips-got-disp"},
{MO_GOT_PAGE, "mips-got-page"},
{MO_GOT_OFST, "mips-got-ofst"},
{MO_HIGHER, "mips-higher"},
{MO_HIGHEST, "mips-highest"},
{MO_GOT_HI16, "mips-got-hi16"},
{MO_GOT_LO16, "mips-got-lo16"},
{MO_CALL_HI16, "mips-call-hi16"},
{MO_CALL_LO16, "mips-call-lo16"}
};
return makeArrayRef(Flags);
}

test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir

  • This file was added.
# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \
# RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: gpoff-hi,
# gpoff-lo, tlsgd, tlsldm, dtprel-hi, dtprel-lo, got-hi, got-lo, call-hi,
# call-lo.
--- |
@v = global i32 0, align 4
@k = thread_local global i32 0, align 4
@j = external thread_local global i32, align 4
@__tls_guard = internal thread_local global i1 false, align 1
declare extern_weak void @_ZTH1j()
declare i32 @_Z1gi(i32 signext)
define i32 @_Z2k1i(i32 signext %asd) {
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%add1 = add nsw i32 %add, %0
%.b.i.i = load i1, i1* @__tls_guard, align 1
br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i
entry._ZTW1k.exit_crit_edge:
%.pre = load i32, i32* @k, align 4
br label %_ZTW1k.exit
init.i.i:
store i1 true, i1* @__tls_guard, align 1
%call.i.i.i = tail call i32 @_Z1gi(i32 signext 3)
store i32 %call.i.i.i, i32* @k, align 4
br label %_ZTW1k.exit
_ZTW1k.exit:
%1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ]
%add2 = add nsw i32 %add1, %1
br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit
; <label>:2:
tail call void @_ZTH1j()
br label %_ZTW1j.exit
_ZTW1j.exit:
%3 = load i32, i32* @j, align 4
%add3 = add nsw i32 %add2, %3
ret i32 %add3
}
...
---
name: _Z2k1i
alignment: 3
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32, preferred-register: '' }
- { id: 5, class: gpr64, preferred-register: '' }
- { id: 6, class: gpr64, preferred-register: '' }
- { id: 7, class: gpr64, preferred-register: '' }
- { id: 8, class: gpr64, preferred-register: '' }
- { id: 9, class: gpr64, preferred-register: '' }
- { id: 10, class: gpr32, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
- { id: 14, class: gpr64, preferred-register: '' }
- { id: 15, class: gpr64, preferred-register: '' }
- { id: 16, class: gpr32, preferred-register: '' }
- { id: 17, class: gpr64, preferred-register: '' }
- { id: 18, class: gpr64, preferred-register: '' }
- { id: 19, class: gpr64, preferred-register: '' }
- { id: 20, class: gpr64, preferred-register: '' }
- { id: 21, class: gpr64, preferred-register: '' }
- { id: 22, class: gpr64, preferred-register: '' }
- { id: 23, class: gpr32, preferred-register: '' }
- { id: 24, class: gpr64, preferred-register: '' }
- { id: 25, class: gpr64, preferred-register: '' }
- { id: 26, class: gpr64, preferred-register: '' }
- { id: 27, class: gpr64, preferred-register: '' }
- { id: 28, class: gpr64, preferred-register: '' }
- { id: 29, class: gpr64, preferred-register: '' }
- { id: 30, class: gpr32, preferred-register: '' }
- { id: 31, class: gpr64, preferred-register: '' }
- { id: 32, class: gpr64, preferred-register: '' }
- { id: 33, class: gpr64, preferred-register: '' }
- { id: 34, class: gpr64, preferred-register: '' }
- { id: 35, class: gpr32, preferred-register: '' }
- { id: 36, class: gpr64, preferred-register: '' }
- { id: 37, class: gpr64, preferred-register: '' }
- { id: 38, class: gpr64, preferred-register: '' }
- { id: 39, class: gpr64, preferred-register: '' }
- { id: 40, class: gpr64, preferred-register: '' }
- { id: 41, class: gpr64, preferred-register: '' }
- { id: 42, class: gpr64, preferred-register: '' }
- { id: 43, class: gpr64, preferred-register: '' }
- { id: 44, class: gpr64, preferred-register: '' }
- { id: 45, class: gpr64, preferred-register: '' }
- { id: 46, class: gpr64, preferred-register: '' }
- { id: 47, class: gpr64, preferred-register: '' }
- { id: 48, class: gpr64, preferred-register: '' }
- { id: 49, class: gpr64, preferred-register: '' }
- { id: 50, class: gpr64, preferred-register: '' }
- { id: 51, class: gpr64, preferred-register: '' }
- { id: 52, class: gpr64, preferred-register: '' }
- { id: 53, class: gpr64, preferred-register: '' }
- { id: 54, class: gpr64, preferred-register: '' }
- { id: 55, class: gpr32, preferred-register: '' }
- { id: 56, class: gpr32, preferred-register: '' }
- { id: 57, class: gpr64, preferred-register: '' }
- { id: 58, class: gpr64, preferred-register: '' }
liveins:
- { reg: '%a0_64', virtual-reg: '%5' }
- { reg: '%t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
liveins: %a0_64, %t9_64
%57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
%58 = DADDu %57, %t9_64
%6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i
%5 = COPY %a0_64
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%7 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%8 = DADDu killed %7, %6
%9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
%a0_64 = COPY %5
%gp_64 = COPY %6
JALR64Pseudo killed %9, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%10 = COPY %v0
%11 = COPY %5.sub_32
%12 = ADDu %10, killed %11
%13 = LUi64 target-flags(mips-got-hi16) @v
%14 = DADDu killed %13, %6
%15 = LD killed %14, target-flags(mips-got-lo16) @v :: (load 8 from got)
%16 = LW killed %15, 0 :: (dereferenceable load 4 from @v)
%0 = ADDu killed %12, killed %16
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%17 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr
%18 = DADDu killed %17, %6
%19 = LD killed %18, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr)
%20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
%a0_64 = COPY %20
%gp_64 = COPY %6
JALR64Pseudo killed %19, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%21 = COPY %v0_64
%22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard
%23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load 1 from @__tls_guard)
BEQ killed %23, %zero, %bb.2.init.i.i, implicit-def dead %at
B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%39 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr
%40 = DADDu killed %39, %6
%41 = LD killed %40, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr)
%42 = DADDiu %6, target-flags(mips-tlsgd) @k
%a0_64 = COPY %42
%gp_64 = COPY %6
JALR64Pseudo killed %41, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%43 = COPY %v0_64
%1 = LW %43, 0 :: (dereferenceable load 4 from @k)
B %bb.3._ZTW1k.exit, implicit-def dead %at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%24 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr
%25 = DADDu killed %24, %6
%26 = LD %25, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr)
%27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
%a0_64 = COPY %27
%gp_64 = COPY %6
JALR64Pseudo killed %26, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%28 = COPY %v0_64
%29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard
%30 = ADDiu %zero, 1
SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store 1 into @__tls_guard)
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%31 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%32 = DADDu killed %31, %6
%33 = DADDiu %zero_64, 3
%34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
%a0_64 = COPY %33
%gp_64 = COPY %6
JALR64Pseudo killed %34, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%35 = COPY %v0
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%36 = LD %25, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr)
%37 = DADDiu %6, target-flags(mips-tlsgd) @k
%a0_64 = COPY %37
%gp_64 = COPY %6
JALR64Pseudo killed %36, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%38 = COPY %v0_64
SW %35, %38, 0 :: (store 4 into @k)
%2 = COPY %35
bb.3._ZTW1k.exit:
successors: %bb.4(0x40000000), %bb.5._ZTW1j.exit(0x40000000)
%3 = PHI %2, %bb.2.init.i.i, %1, %bb.1.entry._ZTW1k.exit_crit_edge
%4 = ADDu %0, %3
%44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j
%45 = DADDu killed %44, %6
%46 = LD killed %45, target-flags(mips-got-lo16) @_ZTH1j :: (load 8 from got)
BEQ64 killed %46, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
B %bb.4, implicit-def dead %at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j
%48 = DADDu killed %47, %6
%49 = LD killed %48, target-flags(mips-call-lo16) @_ZTH1j :: (load 8 from call-entry @_ZTH1j)
%gp_64 = COPY %6
JALR64Pseudo killed %49, csr_n64, implicit-def dead %ra, implicit %gp_64, implicit-def %sp
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
bb.5._ZTW1j.exit:
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%50 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr
%51 = DADDu killed %50, %6
%52 = LD killed %51, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr)
%53 = DADDiu %6, target-flags(mips-tlsgd) @j
%a0_64 = COPY %53
%gp_64 = COPY %6
JALR64Pseudo killed %52, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%54 = COPY %v0_64
%55 = LW %54, 0 :: (dereferenceable load 4 from @j)
%56 = ADDu %4, killed %55
%v0 = COPY %56
RetRA implicit %v0
...

test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir

  • This file was added.
# RUN: llc -march=mips -start-before=expand-isel-pseudos \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \
# RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: got-call,
# got.
--- |
@v = global i32 0, align 4
@j = external global i32, align 4
define i32 @_Z2k1i(i32 signext %asd) {
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%add1 = add nsw i32 %add, %0
%1 = load i32, i32* @j, align 4
%add2 = add nsw i32 %add1, %1
ret i32 %add2
}
declare i32 @_Z1gi(i32 signext)
...
---
name: _Z2k1i
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32, preferred-register: '' }
- { id: 5, class: gpr32, preferred-register: '' }
- { id: 6, class: gpr32, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr32, preferred-register: '' }
- { id: 9, class: gpr32, preferred-register: '' }
- { id: 10, class: gpr32, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- { reg: '%a0', virtual-reg: '%0' }
- { reg: '%t9', virtual-reg: '' }
- { reg: '%v0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: %a0, %t9, %v0
%1 = ADDu %v0, %t9
%0 = COPY %a0
ADJCALLSTACKDOWN 16, 0, implicit-def dead %sp, implicit %sp
%2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load 4 from call-entry @_Z1gi)
%a0 = COPY %0
%gp = COPY %1
JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead %ra, implicit %a0, implicit %gp, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 16, 0, implicit-def dead %sp, implicit %sp
%3 = COPY %v0
%4 = ADDu %3, %0
%5 = LW %1, target-flags(mips-got) @v :: (load 4 from got)
%6 = LW killed %5, 0 :: (dereferenceable load 4 from @v)
%7 = ADDu killed %4, killed %6
%8 = LW %1, target-flags(mips-got) @j :: (load 4 from got)
%9 = LW killed %8, 0 :: (dereferenceable load 4 from @j)
%10 = ADDu killed %7, killed %9
%v0 = COPY %10
RetRA implicit %v0
...

test/CodeGen/Mips/mirparser/target-flags-pic.mir

  • This file was added.
# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \
# RUN: -o /dev/null %s
# A simple test to show that we can parse the target specific flags: gpoff-hi,
#!gpoff-lo, got-call, got-disp.
--- |
@v = global i32 0, align 4
@j = external global i32, align 4
define i32 @_Z2k1i(i32 signext %asd) {
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%add1 = add nsw i32 %add, %0
%1 = load i32, i32* @j, align 4
%add2 = add nsw i32 %add1, %1
ret i32 %add2
}
declare i32 @_Z1gi(i32 signext)
...
---
name: _Z2k1i
alignment: 3
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
- { id: 2, class: gpr64, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32, preferred-register: '' }
- { id: 5, class: gpr32, preferred-register: '' }
- { id: 6, class: gpr64, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr32, preferred-register: '' }
- { id: 9, class: gpr64, preferred-register: '' }
- { id: 10, class: gpr32, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr64, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
liveins:
- { reg: '%a0_64', virtual-reg: '%0' }
- { reg: '%t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: %a0_64, %t9_64
%12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
%13 = DADDu %12, %t9_64
%1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i
%0 = COPY %a0_64
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load 8 from call-entry @_Z1gi)
%a0_64 = COPY %0
%gp_64 = COPY %1
JALR64Pseudo killed %2, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%3 = COPY %v0
%4 = COPY %0.sub_32
%5 = ADDu %3, killed %4
%6 = LD %1, target-flags(mips-got-disp) @v :: (load 8 from got)
%7 = LW killed %6, 0 :: (dereferenceable load 4 from @v)
%8 = ADDu killed %5, killed %7
%9 = LD %1, target-flags(mips-got-disp) @j :: (load 8 from got)
%10 = LW killed %9, 0 :: (dereferenceable load 4 from @j)
%11 = ADDu killed %8, killed %10
%v0 = COPY %11
RetRA implicit %v0
...

test/CodeGen/Mips/mirparser/target-flags-static-tls.mir

  • This file was added.
# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
# RUN: -stop-after=expand-isel-pseudos -relocation-model=static -o /dev/null %s
# A simple test to show that we can parse the target specific flags: highest,
# higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel.
--- |
@v = global i32 0, align 4
@k = thread_local global i32 0, align 4
@j = external thread_local global i32, align 4
@__tls_guard = internal thread_local global i1 false, align 1
declare i32 @_Z1gi(i32 signext)
declare extern_weak void @_ZTH1j()
define i32 @_Z2k1i(i32 signext %asd) {
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%add1 = add nsw i32 %add, %0
%.b.i.i = load i1, i1* @__tls_guard, align 1
br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i
entry._ZTW1k.exit_crit_edge:
%.pre = load i32, i32* @k, align 4
br label %_ZTW1k.exit
init.i.i:
store i1 true, i1* @__tls_guard, align 1
%call.i.i.i = tail call i32 @_Z1gi(i32 signext 3)
store i32 %call.i.i.i, i32* @k, align 4
br label %_ZTW1k.exit
_ZTW1k.exit:
%1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ]
%add2 = add nsw i32 %add1, %1
br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit
; <label>:2:
tail call void @_ZTH1j()
br label %_ZTW1j.exit
_ZTW1j.exit:
%3 = load i32, i32* @j, align 4
%add3 = add nsw i32 %add2, %3
ret i32 %add3
}
...
---
name: _Z2k1i
alignment: 3
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32, preferred-register: '' }
- { id: 5, class: gpr64, preferred-register: '' }
- { id: 6, class: gpr32, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr32, preferred-register: '' }
- { id: 9, class: gpr64, preferred-register: '' }
- { id: 10, class: gpr64, preferred-register: '' }
- { id: 11, class: gpr64, preferred-register: '' }
- { id: 12, class: gpr64, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
- { id: 14, class: gpr32, preferred-register: '' }
- { id: 15, class: gpr64, preferred-register: '' }
- { id: 16, class: gpr64, preferred-register: '' }
- { id: 17, class: gpr64, preferred-register: '' }
- { id: 18, class: gpr64, preferred-register: '' }
- { id: 19, class: gpr64, preferred-register: '' }
- { id: 20, class: gpr32, preferred-register: '' }
- { id: 21, class: gpr64, preferred-register: '' }
- { id: 22, class: gpr64, preferred-register: '' }
- { id: 23, class: gpr64, preferred-register: '' }
- { id: 24, class: gpr64, preferred-register: '' }
- { id: 25, class: gpr64, preferred-register: '' }
- { id: 26, class: gpr32, preferred-register: '' }
- { id: 27, class: gpr64, preferred-register: '' }
- { id: 28, class: gpr64, preferred-register: '' }
- { id: 29, class: gpr64, preferred-register: '' }
- { id: 30, class: gpr64, preferred-register: '' }
- { id: 31, class: gpr32, preferred-register: '' }
- { id: 32, class: gpr64, preferred-register: '' }
- { id: 33, class: gpr64, preferred-register: '' }
- { id: 34, class: gpr64, preferred-register: '' }
- { id: 35, class: gpr64, preferred-register: '' }
- { id: 36, class: gpr64, preferred-register: '' }
- { id: 37, class: gpr64, preferred-register: '' }
- { id: 38, class: gpr64, preferred-register: '' }
- { id: 39, class: gpr64, preferred-register: '' }
- { id: 40, class: gpr64, preferred-register: '' }
- { id: 41, class: gpr64, preferred-register: '' }
- { id: 42, class: gpr64, preferred-register: '' }
- { id: 43, class: gpr64, preferred-register: '' }
- { id: 44, class: gpr64, preferred-register: '' }
- { id: 45, class: gpr64, preferred-register: '' }
- { id: 46, class: gpr64, preferred-register: '' }
- { id: 47, class: gpr64, preferred-register: '' }
- { id: 48, class: gpr32, preferred-register: '' }
- { id: 49, class: gpr32, preferred-register: '' }
- { id: 50, class: gpr64, preferred-register: '' }
- { id: 51, class: gpr64, preferred-register: '' }
liveins:
- { reg: '%a0_64', virtual-reg: '%5' }
- { reg: '%t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
liveins: %a0_64, %t9_64
%50 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
%51 = DADDu %50, %t9_64
%43 = DADDiu %51, target-flags(mips-gpoff-lo) @_Z2k1i
%5 = COPY %a0_64
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%6 = COPY %5.sub_32
%a0_64 = COPY %5
JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%7 = COPY %v0
%8 = ADDu %7, killed %6
%9 = LUi64 target-flags(mips-highest) @v
%10 = DADDiu killed %9, target-flags(mips-higher) @v
%11 = DSLL killed %10, 16
%12 = DADDiu killed %11, target-flags(mips-abs-hi) @v
%13 = DSLL killed %12, 16
%14 = LW killed %13, target-flags(mips-abs-lo) @v :: (dereferenceable load 4 from @v)
%0 = ADDu killed %8, killed %14
%15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard
%17 = RDHWR64 %hwr29
%v1_64 = COPY %17
%18 = COPY %v1_64
%19 = DADDu %18, killed %16
%20 = LBu killed %19, 0 :: (dereferenceable load 1 from @__tls_guard)
BEQ killed %20, %zero, %bb.2.init.i.i, implicit-def dead %at
J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
%32 = LUi64 target-flags(mips-tprel-hi) @k
%33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k
%34 = RDHWR64 %hwr29
%v1_64 = COPY %34
%35 = COPY %v1_64
%36 = DADDu %35, killed %33
%1 = LW killed %36, 0 :: (dereferenceable load 4 from @k)
J %bb.3._ZTW1k.exit, implicit-def dead %at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
%21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard
%23 = RDHWR64 %hwr29
%v1_64 = COPY %23
%24 = COPY %v1_64
%25 = DADDu %24, killed %22
%26 = ADDiu %zero, 1
SB killed %26, killed %25, 0 :: (store 1 into @__tls_guard)
%27 = LUi64 target-flags(mips-tprel-hi) @k
%28 = DADDiu killed %27, target-flags(mips-tprel-lo) @k
%29 = DADDu %24, killed %28
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
%30 = DADDiu %zero_64, 3
%a0_64 = COPY %30
JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
%31 = COPY %v0
SW %31, killed %29, 0 :: (store 4 into @k)
%2 = COPY %31
bb.3._ZTW1k.exit:
successors: %bb.4(0x40000000), %bb.5._ZTW1j.exit(0x40000000)
%3 = PHI %2, %bb.2.init.i.i, %1, %bb.1.entry._ZTW1k.exit_crit_edge
%4 = ADDu %0, %3
%37 = LUi64 target-flags(mips-highest) @_ZTH1j
%38 = DADDiu killed %37, target-flags(mips-higher) @_ZTH1j
%39 = DSLL killed %38, 16
%40 = DADDiu killed %39, target-flags(mips-abs-hi) @_ZTH1j
%41 = DSLL killed %40, 16
%42 = DADDiu killed %41, target-flags(mips-abs-lo) @_ZTH1j
BEQ64 killed %42, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
J %bb.4, implicit-def dead %at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
JAL @_ZTH1j, csr_n64, implicit-def dead %ra, implicit-def %sp
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
bb.5._ZTW1j.exit:
%44 = RDHWR64 %hwr29
%v1_64 = COPY %44
%45 = LD %43, target-flags(mips-gottprel) @j :: (load 8)
%46 = COPY %v1_64
%47 = DADDu %46, killed %45
%48 = LW killed %47, 0 :: (dereferenceable load 4 from @j)
%49 = ADDu %4, killed %48
%v0 = COPY %49
RetRA implicit %v0
...