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[X86] Enable extended comparison predicate support for SETUEQ/SETONE when targeting AVX instructions.
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Authored by craig.topper on Oct 5 2017, 5:52 PM.

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Summary

If we are using AVX512 instructions I think we can assume that all the comparison predicates are supported since we don't have an AMD implementation to compare against?

Though maybe we proved that AMD really does implement all 32 comparisons correctly in AVX1/2? We are using 0xF to create all ones on AVX1 right?

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Event Timeline

craig.topper created this revision.Oct 5 2017, 5:52 PM
RKSimon edited edge metadata.Oct 6 2017, 1:19 AM

Though maybe we proved that AMD really does implement all 32 comparisons correctly in AVX1/2? We are using 0xF to create all ones on AVX1 right?

Yes we proved that every AVX capable AMD machine (we tested Jaguar, Bulldozer, Excavator and Ryzen) correctly supported all comparison modes. Its the documentation that hasn't been fixed.

Do this for AVX instructions as well.

craig.topper retitled this revision from [X86] Enable extended comparison predicate support when targeting AVX-512 instructions. to [X86] Enable extended comparison predicate support for SETUEQ/SETONE when targeting AVX instructions..Oct 6 2017, 11:02 AM
RKSimon accepted this revision.Oct 8 2017, 3:19 AM

Possibly regenerate fast-isel-select-pseudo-cmov.ll before the patch?

LGTM whatever

This revision is now accepted and ready to land.Oct 8 2017, 3:19 AM
This revision was automatically updated to reflect the committed changes.