adding pattern for broadcastm

[RKSimon]

Please remember to create your diff with context: http://llvm.org/docs/Phabricator.html

test/CodeGen/X86/broadcastm-lowering.ll

4

Please don't use -mcpu, use -mattr instead. Something like:

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq  | FileCheck %s --check-prefix=ALL --check-prefix=AVX512DQVL

Also, should i686 triples be tested as well? Not sure if any non-legal i64 issues will arise

[zvi]

The title should have an X86 label, and can you please add a cover message in the summary?

lib/Target/X86/X86ISelLowering.cpp

6695

Would isSplatZeroExtended be a better name?
(const BuildVectorSDNode *Op, unsigned &NumElts, MVT& EltType)

6749

Please add a comment explaining the change here and in the Summary. Maybe something like:
t0 = (zext_i64 (bitcast_i8 v2i1 X))
t1 = (build_vector t0 t0)
->
(VBROADCASTM v2i1 X)

6749

Checking

[zvi]

test/CodeGen/X86/broadcastm-lowering.ll

3

instead of -mcpu=skx , you should use -mattr which is more robust to scheduling changes:
-mattr=+avx512cd,+avx512vl

and similarly for knl:
-mattr=+avx512cd

[zvi]

test/CodeGen/X86/broadcastm-lowering.ll

4

Simon has already mentioned this

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

6605

vedtor->vector

Also the first word of each sentence in the comment should be capitalized.

6628

I think this line should be indented 2 additional spaces?

6635

Am I missing something or is this variable and several above it dead?

6667

Use is512BitVector here.

6674

Does this overflow 80 columns?

[jina.nahias]

lib/Target/X86/X86ISelLowering.cpp

6635

those variables are sending as reference to this function.

[RKSimon]

test/CodeGen/X86/broadcastm-lowering.ll

4

Please can you tidy the prefixes: AVX512CD, AVX512VLCDBW and X86-AVX512VLCDBW would be more closely match convention.

[RKSimon]

Thanks please can you now commit broadcastm-lowering.ll with trunk's current codegen so that this patch shows the codegen diff?

[RKSimon]

A few minor comments

lib/Target/X86/X86ISelLowering.cpp

6607

Describe the function NumElt and EltType, also I'm not convinced that 'isSplatZeroExtended' is suitably descriptive of what the function is actually doing.

6610

unsigned NumElts = Op->getNumOperands();
unsigned Delta = NumElts;

6612

Comment describing the search you're doing in the loop

for (unsigned i = 1; i < NumElts; i++) {

6623

Comment the loop

for (unsigned i = Delta; i < NumElts; i++) {

6632

Op->getSimpleValueType(0).getScalaraSizeInBits()

[jina.nahias]

lib/Target/X86/X86ISelLowering.cpp

6607

i could not find a better name. do you have one?

[jina.nahias]

I have fixed all comments.
ping.

[m_zuckerman]

lib/Target/X86/X86ISelLowering.cpp

6604–6638

Please, add example of the pattern that you are looking for

6638

Use NumElts /Delta

6669

Why do you set the NumElt to one?
I prefer
unsigned NumElts =BVOp->getNumOperands()
and if it equal to one exit the function (early exiting)

[m_zuckerman]

lib/Target/X86/X86ISelLowering.cpp

6670

if(NumElts!=1&&SDValue ZeroExtended = isSplatZeroExtended(BVOp, NumElts, EltType))

[m_zuckerman]

lib/Target/X86/X86ISelLowering.cpp

6670

sorry without NumElts!=1

[m_zuckerman]

LGTM

[jina.nahias]

committed in r316921

lib/Target/X86/X86ISelLowering.cpp

static bool isUseOfShuffle(SDNode *N) {
   for (auto *U : N->uses()) {
     if (isTargetShuffle(U->getOpcode()))
       return true;
     if (U->getOpcode() == ISD::BITCAST) // Ignore bitcasts
       return isUseOfShuffle(U);
   }
   return false;
 }
 
+// check if the current node of build vector is a zero extended vedtor.
+// if so, return the value extended.
+static SDValue isSplatZeroExtended(const BuildVectorSDNode *Op, unsigned &NumElt,
+                                    MVT &EltType) {
+  SDValue ExtValue = Op->getOperand(0);
+  unsigned Delta = Op->getNumOperands();
+
+  for (unsigned i = 1; i < Op->getNumOperands(); i++) {
+    if (Op->getOperand(i) == ExtValue) {
+      Delta = i;
+      break;
+    }
+    if (!(Op->getOperand(i).isUndef() || isNullConstant(Op->getOperand(i))))
+      return SDValue();
+  }
+  if (!isPowerOf2_32(Delta) || Delta == 1)
+    return SDValue();
+
+  for (unsigned i = Delta; i < Op->getNumOperands(); i++) {
+    if (i % Delta == 0) {
+      if (Op->getOperand(i) != ExtValue)
+        return SDValue();
+    } else if (!(isNullConstant(Op->getOperand(i)) ||
+               Op->getOperand(i).isUndef()))
+      return SDValue();
+  }
+  unsigned EltSize =
+      Op->getSimpleValueType(0).getVectorElementType().getSizeInBits();
+  unsigned ExtVTSize = EltSize * Delta;
+  EltType = MVT::getIntegerVT(ExtVTSize);
+  NumElt = Op->getNumOperands() / Delta;
+  return ExtValue;
+}
+
 /// Attempt to use the vbroadcast instruction to generate a splat value
 /// from a splat BUILD_VECTOR which uses:
 ///  a. A single scalar load, or a constant.
 ///  b. Repeated pattern of constants (e.g. <0,1,0,1> or <0,1,2,3,0,1,2,3>).
 ///
 /// The VBROADCAST node is returned when a pattern is found,
 /// or SDValue() otherwise.
 static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
                                            const X86Subtarget &Subtarget,
                                            SelectionDAG &DAG) {
   // VBROADCAST requires AVX.
   // TODO: Splats could be generated for non-AVX CPUs using SSE
   // instructions, but there's less potential gain for only 128-bit vectors.
   if (!Subtarget.hasAVX())
     return SDValue();
 
   MVT VT = BVOp->getSimpleValueType(0);
   SDLoc dl(BVOp);
 
   assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
          "Unsupported vector type for broadcast.");
 
+  // Attempt to use VBROADCASTM
+  // from this paterrn:
+  //  a. t0 = (zext_i64 (bitcast_i8 v2i1 X))
+  //  b. t1 = (build_vector t0 t0)
+  //
+  // create (VBROADCASTM v2i1 X)
+  if (Subtarget.hasCDI() && (VT.getSizeInBits() == 512 || Subtarget.hasVLX())) {
+    MVT EltType;
+    unsigned NumElts = 1;
+    SDValue ZeroExtended = isSplatZeroExtended(BVOp, NumElts, EltType);
+    if (ZeroExtended && ZeroExtended.getOpcode() == ISD::BITCAST) {
+      SDValue BOperand = ZeroExtended.getOperand(0);
+      if (BOperand.getSimpleValueType().getVectorElementType() == MVT::i1) {
+        if ((EltType == MVT::i64 && VT.getVectorElementType() == MVT::i8) ||  //for broadcastmb2q
+            (EltType == MVT::i32 && VT.getVectorElementType() == MVT::i16)) { //for broadcastmw2d
+          SDValue Brdcst =
+              DAG.getNode(X86ISD::VBROADCASTM, dl,
+                          MVT::getVectorVT(EltType, NumElts), BOperand);
+          return DAG.getBitcast(VT, Brdcst);
+        }
+      }
+    }
+  }
+
   BitVector UndefElements;
   SDValue Ld = BVOp->getSplatValue(&UndefElements);
 
   // We need a splat of a single value to use broadcast, and it doesn't
   // make any sense if the value is only in one element of the vector.
   if (!Ld || (VT.getVectorNumElements() - UndefElements.count()) <= 1) {
     APInt SplatValue, Undef;
     unsigned SplatBitSize;
     bool HasUndef;
     // Check if this is a repeated constant pattern suitable for broadcasting.
     if (BVOp->isConstantSplat(SplatValue, Undef, SplatBitSize, HasUndef) &&
         SplatBitSize > VT.getScalarSizeInBits() &&
         SplatBitSize < VT.getSizeInBits()) {
       // Avoid replacing with broadcast when it's a use of a shuffle
       // instruction to preserve the present custom lowering of shuffles.
       if (isUseOfShuffle(BVOp) || BVOp->hasOneUse())
         return SDValue();
       // replace BUILD_VECTOR with broadcast of the repeated constants.
       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (BVOp->isConstantSplat(SplatValue, Undef, SplatBitSize, HasUndef) &&
           unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
           Ld = DAG.getLoad(
               CVT, dl, DAG.getEntryNode(), CP,
               MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
               Alignment);
           SDValue Brdcst = DAG.getNode(X86ISD::VBROADCAST, dl,
                                        MVT::getVectorVT(CVT, Repeat), Ld);
           return DAG.getBitcast(VT, Brdcst);
         } else if (SplatBitSize > 64) {
           // Load the vector of constants and broadcast it.
           MVT CVT = VT.getScalarType();
           Constant *VecC = getConstantVector(VT, SplatValue, SplatBitSize,
                                              *Ctx);
           SDValue VCP = DAG.getConstantPool(VecC, PVT);
           unsigned NumElm = SplatBitSize / VT.getScalarSizeInBits();
           unsigned Alignment = cast<ConstantPoolSDNode>(VCP)->getAlignment();
           Ld = DAG.getLoad(

test/CodeGen/X86/broadcastm-lowering.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd | FileCheck %s --check-prefix=ALL --check-prefix=AVX5CD
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown  -mattr=+avx512vl,avx512cd,+avx512bw| FileCheck %s --check-prefix=ALL --check-prefix=AVX512VLCDBW
+
+define <2 x i64> @test_mm_epi64(<8 x i16> %a, <8 x i16> %b) {
+; AVX5CD-LABEL: test_mm_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpmovsxwq %xmm0, %zmm0
+; AVX5CD-NEXT:    vpsllq $63, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmq %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vzeroupper
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqw %xmm1, %xmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %xmm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <8 x i16> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 0
+  %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %vecinit1.i.i
+}
+
+define <4 x i32> @test_mm_epi32(<16 x i8> %a, <16 x i8> %b) {
+; AVX5CD-LABEL: test_mm_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpmovsxbd %xmm0, %zmm0
+; AVX5CD-NEXT:    vpslld $31, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vzeroupper
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqb %xmm1, %xmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %xmm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <16 x i8> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 0
+  %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %vecinit3.i.i
+}
+
+define <16 x i32> @test_mm512_epi32(<16 x i32> %a, <16 x i32> %b) {
+; AVX5CD-LABEL: test_mm512_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpbroadcastd %eax, %zmm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm512_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %zmm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <16 x i32> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0
+  %vecinit15.i.i = shufflevector <16 x i32> %vecinit.i.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  ret <16 x i32> %vecinit15.i.i
+}
+
+define <8 x i64> @test_mm512_epi64(<8 x i32> %a, <8 x i32> %b) {
+; AVX5CD-LABEL: test_mm512_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; AVX5CD-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    movzbl %al, %eax
+; AVX5CD-NEXT:    vpbroadcastq %rax, %zmm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm512_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %zmm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <8 x i32> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <8 x i64> undef, i64 %conv.i, i32 0
+  %vecinit7.i.i = shufflevector <8 x i64> %vecinit.i.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  ret <8 x i64> %vecinit7.i.i
+}
+
+define <4 x i64> @test_mm256_epi64(<8 x i32> %a, <8 x i32> %b) {
+; AVX5CD-LABEL: test_mm256_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; AVX5CD-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm256_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %ymm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <8 x i32> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 0
+  %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  ret <4 x i64> %vecinit3.i.i
+}
+
+define <8 x i32> @test_mm256_epi32(<16 x i16> %a, <16 x i16> %b) {
+; AVX5CD-LABEL: test_mm256_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqw %ymm1, %ymm0, %ymm0
+; AVX5CD-NEXT:    vpmovsxwd %ymm0, %zmm0
+; AVX5CD-NEXT:    vpslld $31, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm256_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqw %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %ymm0
+; AVX512VLCDBW-NEXT:    retq
+entry:
+  %0 = icmp eq <16 x i16> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 0
+  %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  ret <8 x i32> %vecinit7.i.i
+}
+