[x86] fix pr29061

[coby]

Summary

https://bugs.llvm.org//show_bug.cgi?id=29061
Don't try referencing REX-needed regs when not on 64bit mode
Aligns to GCC

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

36825

Do you need to clear Res if this isn't true like we do in multiple other else cases?

[coby]

lib/Target/X86/X86ISelLowering.cpp

36825

It leads to in-ability to satisfy input regs:
error: couldn't allocate input reg for constraint '{di}'
so no :\.
that being said, i'm not to well familiar with this area so there might be some ways around it (i.e. Do clear, and make appropriate modifications to the subsequent code (although i'm not sure the outcome will be any 'neater')

[RKSimon]

test/CodeGen/X86/pr29061.ll

2

Expand the triple, otherwise it might cause issues depending on the buildbot:

; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s

You might be able to use utils/update_llc_test_checks.py as well

[coby]

addressed Simon's comment

[RKSimon]

LGTM

[RKSimon]

Fixed in rL314203 @coby Make sure you spell "Differential Revision: " correctly!

[coby]

In D37801#881962, @RKSimon wrote:

Fixed in rL314203 @coby Make sure you spell "Differential Revision: " correctly!

blimey
my vim has no auto-correction ;)

lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   // given register. Thus, based on the ordering of the tablegened file,
   // the "plain" GR classes might not come first.
   // Therefore, use a helper method.
   if (isGRClass(*Class)) {
     unsigned Size = VT.getSizeInBits();
     if (Size == 1) Size = 8;
     unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
     if (DestReg > 0) {
-      Res.first = DestReg;
-      Res.second = Size == 8 ? &X86::GR8RegClass
-                 : Size == 16 ? &X86::GR16RegClass
-                 : Size == 32 ? &X86::GR32RegClass
-                 : &X86::GR64RegClass;
-      assert(Res.second->contains(Res.first) && "Register in register class");
+      bool is64Bit = Subtarget.is64Bit();
+      const TargetRegisterClass *RC =
+          Size == 8 ? (is64Bit ? &X86::GR8RegClass : &X86::GR8_NOREXRegClass)
+        : Size == 16 ? (is64Bit ? &X86::GR16RegClass : &X86::GR16_NOREXRegClass)
+        : Size == 32 ? (is64Bit ? &X86::GR32RegClass : &X86::GR32_NOREXRegClass)
+      if (RC->contains(DestReg))
+        Res = std::make_pair(DestReg, RC);
     } else {
       // No register found/type mismatch.
       Res.first = 0;
       Res.second = nullptr;
     }
   } else if (isFRClass(*Class)) {
     // Handle references to XMM physical registers that got mapped into the
     // wrong class.  This can happen with constraints like {xmm0} where the

test/CodeGen/X86/pr29061.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple i386-unknown-linux-gnu < %s | FileCheck %s
+
+; Previously, a reference to SIL/DIL was being emitted
+; but those aren't available unless on a 64bit mode
+
+define void @t1(i8 signext %c) {
+; CHECK-LABEL: t1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:  .Lcfi0:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:  .Lcfi1:
+; CHECK-NEXT:    .cfi_offset %edi, -8
+; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %edi
+; CHECK-NEXT:    # kill: %DI<def> %DI<kill> %EDI<kill>
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:    retl
+entry:
+  tail call void asm sideeffect "", "{di},~{dirflag},~{fpsr},~{flags}"(i8 %c)
+  ret void
+}
+
+define void @t2(i8 signext %c) {
+; CHECK-LABEL: t2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:  .Lcfi2:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:  .Lcfi3:
+; CHECK-NEXT:    .cfi_offset %esi, -8
+; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    # kill: %SI<def> %SI<kill> %ESI<kill>
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
+entry:
+  tail call void asm sideeffect "", "{si},~{dirflag},~{fpsr},~{flags}"(i8 %c)
+  ret void
+}
+