[X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead of mcpu flag

[gadi.haber]

Summary

NFC.
Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows:
Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq
Instead of -mcpu=knl use -mattr=+avx512f

[delena]

test/CodeGen/X86/pr32329.ll

4

Please add a comment about this test: According to https://bugs.llvm.org/show_bug.cgi?id=32329
it checks DAG ISEL failure on SKX target.

[gadi.haber]

Added the following comment to pr32329.ll:
"According to https://bugs.llvm.org/show_bug.cgi?id=32329 it checks DAG ISEL failure on SKX target"

[gadi.haber]

generated new diff with all changes.

[delena]

LGTM

[RKSimon]

This was committed at rL312909

test/CodeGen/X86/avx2-intrinsics-x86.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
-; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
 
 define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
 ; AVX2-LABEL: test_x86_avx2_packssdw:
 ; AVX2:       ## BB#0:
 ; AVX2-NEXT:    vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
 ; AVX2-NEXT:    retl ## encoding: [0xc3]
 ;
 ; AVX512VL-LABEL: test_x86_avx2_packssdw:

 ; AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
 ; AVX2-NEXT:    vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
 ; AVX2-NEXT:    vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
 ; AVX2-NEXT:    vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
 ; AVX2-NEXT:    retl ## encoding: [0xc3]
 ;
 ; AVX512VL-LABEL: test_gather_mask:
 ; AVX512VL:       ## BB#0:
-; AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX512VL-NEXT:    vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
-; AVX512VL-NEXT:    vgatherdps %ymm3, (%eax,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x88]
 ; AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
+; AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
+; AVX512VL-NEXT:    vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
+; AVX512VL-NEXT:    vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
 ; AVX512VL-NEXT:    vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
 ; AVX512VL-NEXT:    retl ## encoding: [0xc3]
   %a_i8 = bitcast float* %a to i8*
   %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
                            i8* %a_i8, <8 x i32> %idx, <8 x float> %mask, i8 4) ;
 
 ;; for debugging, we'll just dump out the mask
   %out_ptr = bitcast float * %out to <8 x float> *
   store <8 x float> %mask, <8 x float> * %out_ptr, align 4
 
   ret <8 x float> %res
 }

test/CodeGen/X86/avx512-cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl  | FileCheck %s --check-prefix=ALL --check-prefix=KNL
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx  | FileCheck %s --check-prefix=ALL --check-prefix=SKX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=KNL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=SKX
 
 define double @test1(double %a, double %b) nounwind {
 ; ALL-LABEL: test1:
 ; ALL:       ## BB#0:
 ; ALL-NEXT:    vucomisd %xmm1, %xmm0
 ; ALL-NEXT:    jne LBB0_1
 ; ALL-NEXT:    jnp LBB0_2
 ; ALL-NEXT:  LBB0_1: ## %l1
entry:
   %0 = fcmp one double %x, %y
   %or = zext i1 %0 to i32
   ret i32 %or
 }
 
 define i32 @test8(i32 %a1, i32 %a2, i32 %a3) {
 ; ALL-LABEL: test8:
 ; ALL:       ## BB#0:
+; ALL-NEXT:    notl %edi
 ; ALL-NEXT:    xorl $-2147483648, %esi ## imm = 0x80000000
 ; ALL-NEXT:    testl %edx, %edx
 ; ALL-NEXT:    movl $1, %eax
 ; ALL-NEXT:    cmovel %eax, %edx
-; ALL-NEXT:    notl %edi
 ; ALL-NEXT:    orl %edi, %esi
 ; ALL-NEXT:    cmovnel %edx, %eax
 ; ALL-NEXT:    retq
   %tmp1 = icmp eq i32 %a1, -1
   %tmp2 = icmp eq i32 %a2, -2147483648
   %tmp3 = and i1 %tmp1, %tmp2
   %tmp4 = icmp eq i32 %a3, 0
   %tmp5 = or i1 %tmp3, %tmp4

test/CodeGen/X86/pr32329.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx | FileCheck %s -check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown   -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s -check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s -check-prefix=X64
 
 %struct.AA = type { i24, [4 x i8] }
 
 @obj = external local_unnamed_addr global %struct.AA, align 8
 @var_27 = external local_unnamed_addr constant i8, align 1
 @var_2 = external local_unnamed_addr constant i16, align 2
 @var_24 = external local_unnamed_addr constant i64, align 8
 @var_310 = external local_unnamed_addr global i64, align 8
 @var_50 = external local_unnamed_addr global i64, align 8

 ; X86-NEXT:  .Lcfi4:
 ; X86-NEXT:    .cfi_offset %esi, -20
 ; X86-NEXT:  .Lcfi5:
 ; X86-NEXT:    .cfi_offset %edi, -16
 ; X86-NEXT:  .Lcfi6:
 ; X86-NEXT:    .cfi_offset %ebx, -12
 ; X86-NEXT:  .Lcfi7:
 ; X86-NEXT:    .cfi_offset %ebp, -8
+; X86-NEXT:    movl obj, %edx
 ; X86-NEXT:    movsbl var_27, %eax
+; X86-NEXT:    movzwl var_2, %esi
 ; X86-NEXT:    movl var_310, %ecx
 ; X86-NEXT:    imull %eax, %ecx
-; X86-NEXT:    movl obj, %esi
 ; X86-NEXT:    addl var_24, %ecx
-; X86-NEXT:    movzwl var_2, %edi
-; X86-NEXT:    andl $4194303, %esi # imm = 0x3FFFFF
-; X86-NEXT:    leal (%esi,%esi), %edx
-; X86-NEXT:    subl %eax, %edx
-; X86-NEXT:    movl %edx, %ebx
-; X86-NEXT:    subl %edi, %ebx
-; X86-NEXT:    imull %ebx, %ecx
+; X86-NEXT:    andl $4194303, %edx # imm = 0x3FFFFF
+; X86-NEXT:    leal (%edx,%edx), %ebx
+; X86-NEXT:    subl %eax, %ebx
+; X86-NEXT:    movl %ebx, %edi
+; X86-NEXT:    subl %esi, %edi
+; X86-NEXT:    imull %edi, %ecx
 ; X86-NEXT:    addl $-1437483407, %ecx # imm = 0xAA51BE71
-; X86-NEXT:    movl $9, %edi
+; X86-NEXT:    movl $9, %esi
 ; X86-NEXT:    xorl %ebp, %ebp
-; X86-NEXT:    shldl %cl, %edi, %ebp
-; X86-NEXT:    shlxl %ecx, %edi, %edi
+; X86-NEXT:    shldl %cl, %esi, %ebp
+; X86-NEXT:    shll %cl, %esi
 ; X86-NEXT:    testb $32, %cl
-; X86-NEXT:    cmovnel %edi, %ebp
+; X86-NEXT:    cmovnel %esi, %ebp
 ; X86-NEXT:    movl $0, %ecx
-; X86-NEXT:    cmovnel %ecx, %edi
+; X86-NEXT:    cmovnel %ecx, %esi
+; X86-NEXT:    cmpl %edx, %edi
 ; X86-NEXT:    movl %ebp, var_50+4
-; X86-NEXT:    cmpl %esi, %ebx
+; X86-NEXT:    movl %esi, var_50
 ; X86-NEXT:    setge var_205
-; X86-NEXT:    imull %eax, %edx
-; X86-NEXT:    movl %edi, var_50
-; X86-NEXT:    movb %dl, var_218
+; X86-NEXT:    imull %eax, %ebx
+; X86-NEXT:    movb %bl, var_218
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: foo:
 ; X64:       # BB#0: # %entry
-; X64-NEXT:    movsbl {{.*}}(%rip), %eax
+; X64-NEXT:    movl {{.*}}(%rip), %eax
+; X64-NEXT:    movsbl {{.*}}(%rip), %r9d
+; X64-NEXT:    movzwl {{.*}}(%rip), %r8d
 ; X64-NEXT:    movl {{.*}}(%rip), %ecx
-; X64-NEXT:    imull %eax, %ecx
-; X64-NEXT:    movl {{.*}}(%rip), %edx
+; X64-NEXT:    imull %r9d, %ecx
 ; X64-NEXT:    addl {{.*}}(%rip), %ecx
-; X64-NEXT:    movzwl {{.*}}(%rip), %r8d
-; X64-NEXT:    andl $4194303, %edx # imm = 0x3FFFFF
-; X64-NEXT:    leal (%rdx,%rdx), %edi
-; X64-NEXT:    subl %eax, %edi
+; X64-NEXT:    andl $4194303, %eax # imm = 0x3FFFFF
+; X64-NEXT:    leal (%rax,%rax), %edi
+; X64-NEXT:    subl %r9d, %edi
 ; X64-NEXT:    movl %edi, %esi
 ; X64-NEXT:    subl %r8d, %esi
 ; X64-NEXT:    imull %esi, %ecx
 ; X64-NEXT:    addl $-1437483407, %ecx # imm = 0xAA51BE71
-; X64-NEXT:    movl $9, %r8d
-; X64-NEXT:    cmpl %edx, %esi
+; X64-NEXT:    movl $9, %edx
+; X64-NEXT:    # kill: %CL<def> %CL<kill> %ECX<kill>
+; X64-NEXT:    shlq %cl, %rdx
+; X64-NEXT:    movq %rdx, {{.*}}(%rip)
+; X64-NEXT:    cmpl %eax, %esi
 ; X64-NEXT:    setge {{.*}}(%rip)
-; X64-NEXT:    shlxq %rcx, %r8, %rcx
-; X64-NEXT:    imull %eax, %edi
-; X64-NEXT:    movq %rcx, {{.*}}(%rip)
+; X64-NEXT:    imull %r9d, %edi
 ; X64-NEXT:    movb %dil, {{.*}}(%rip)
 ; X64-NEXT:    retq
   entry:
   %bf.load = load i32, i32* bitcast (%struct.AA* @obj to i32*), align 8
   %bf.clear = shl i32 %bf.load, 1
   %add = and i32 %bf.clear, 8388606
   %0 = load i8, i8* @var_27, align 1
   %conv5 = sext i8 %0 to i32