[mips] Partially fix PR34391

[sdardis]

Summary

Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser
which also rendered the operand to the instruction. In some cases the
general parser could construct an MCExpr which was not a MCConstantExpr
which MipsAsmParser was expecting.

Address this by altering the special handling to cope with unexpected inputs
and fine-tune the handling of cases where an register name that is not
available in the current ABI is regarded as not a match for the custom parser
but also not as ab outright error.

Also enforces the binutils restriction that only constants are accepted.

This partially resolves PR34391.

Thanks to Ed Maste for reporting the issue!

[sdardis]

Ping.

[nitesh.jain]

LGTM.

Thanks

[sdardis]

Found an issue when doing some final testing. One of the invalid tests (test/mc/mips2/invalid-mips3.s) reports a wrong operand error, as the parser uses the generic parser rather than the operand specific parser. It parses '$a4' as an immediate and rejects it, as the register matcher doesn't match $a4 as a register as the O32 abi is in use.

[sdardis]

Address failures by handling non-constants in the parser. Also handle the differences between register names/symbols between ABIs.

[arichardson]

This fixes the crashes we had when compiling some CheriBSD kernel assembly.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
   OperandMatchResultTy
   matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
                                     StringRef Identifier, SMLoc S);
   OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
                                                      SMLoc S);
   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
   OperandMatchResultTy parseImm(OperandVector &Operands);
   OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
-  OperandMatchResultTy parseInvNum(OperandVector &Operands);
   OperandMatchResultTy parseRegisterPair(OperandVector &Operands);
   OperandMatchResultTy parseMovePRegPair(OperandVector &Operands);
   OperandMatchResultTy parseRegisterList(OperandVector &Operands);
 
   bool searchSymbolAlias(OperandVector &Operands);
 
   bool parseOperand(OperandVector &, StringRef Mnemonic);
 
public:
   void addUImmOperands(MCInst &Inst, unsigned N) const {
     if (isImm() && !isConstantImm()) {
       addExpr(Inst, getImm());
       return;
     }
     addConstantUImmOperands<Bits, 0, 0>(Inst, N);
   }
 
+  template <unsigned Bits>
+  void addInvConstantSImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    int64_t Imm = getConstantImm();
+    Imm = SignExtend64<Bits>(Imm);
+    Imm = 0 - Imm;
+    Inst.addOperand(MCOperand::createImm(Imm));
+  }
+
   template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
   void addConstantSImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     int64_t Imm = getConstantImm() - Offset;
     Imm = SignExtend64<Bits>(Imm);
     Imm += Offset;
     Imm += AdjustOffset;
     Inst.addOperand(MCOperand::createImm(Imm));
if (Parser.parseExpression(Expr)) {
     return MatchOperand_ParseFail;
   }
   Operands.push_back(
       MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy
-MipsAsmParser::parseInvNum(OperandVector &Operands) {
-  MCAsmParser &Parser = getParser();
-  const MCExpr *IdVal;
-  // If the first token is '$' we may have register operand.
-  if (Parser.getTok().is(AsmToken::Dollar))
-    return MatchOperand_NoMatch;
-  SMLoc S = Parser.getTok().getLoc();
-  if (getParser().parseExpression(IdVal))
-    return MatchOperand_ParseFail;
-  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
-  assert(MCE && "Unexpected MCExpr type.");
-  int64_t Val = MCE->getValue();
-  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-  Operands.push_back(MipsOperand::CreateImm(
-      MCConstantExpr::create(0 - Val, getContext()), S, E, *this));
-  return MatchOperand_Success;
-}
-
-OperandMatchResultTy
 MipsAsmParser::parseRegisterList(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   SmallVector<unsigned, 10> Regs;
   unsigned RegNo;
   unsigned PrevReg = Mips::NoRegister;
   bool RegRange = false;
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands;
 

lib/Target/Mips/MipsInstrInfo.td

def MipsMemSimm16AsmOperand : AsmOperandClass {
   let Name = "MemOffsetSimm16";
   let SuperClasses = [MipsMemAsmOperand];
   let RenderMethod = "addMemOperands";
   let ParserMethod = "parseMemOperand";
   let PredicateMethod = "isMemWithSimmOffset<16>";
   let DiagnosticType = "MemSImm16";
 }
 
-def MipsInvertedImmoperand : AsmOperandClass {
-  let Name = "InvNum";
-  let RenderMethod = "addImmOperands";
-  let ParserMethod = "parseInvNum";
+def MipsInvertedSImm16Operand : AsmOperandClass {
+  let Name = "InvSImm16_Relaxed";
+  let SuperClasses = [SImm16AsmOperandClass];
+  let RenderMethod = "addInvConstantSImmOperands<16>";
+  let PredicateMethod = "isConstantSImm<16>";
 }
 
 def InvertedImOperand : Operand<i32> {
-  let ParserMatchClass = MipsInvertedImmoperand;
+  let ParserMatchClass = MipsInvertedSImm16Operand;
 }
 
 def InvertedImOperand64 : Operand<i64> {
-  let ParserMatchClass = MipsInvertedImmoperand;
+  let ParserMatchClass = MipsInvertedSImm16Operand;
 }
 
 class mem_generic : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";

test/MC/Mips/macro-aliases-invalid.s

+# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 %s 2>%t1
+# RUN: FileCheck %s < %t1
+
+# Check that subu only rejects any non-constant values.
+
+.globl end
+  subu  $4, $4, %lo($start)   # CHECK: error: invalid operand for instruction
+  subu  $4, $4, $start        # CHECK: error: invalid operand for instruction
+  subu  $4, $4, %hi(end)      # CHECK: error: invalid operand for instruction
+  subu  $4, $4, end + 4       # CHECK: error: invalid operand for instruction
+  subu  $4, $4, end           # CHECK: error: invalid operand for instruction
+  subu  $4, $4, sp            # CHECK: error: invalid operand for instruction
+
+  subu  $4, %lo($start)       # CHECK: error: invalid operand for instruction
+  subu  $4, $start            # CHECK: error: invalid operand for instruction
+  subu  $4, %hi(end)          # CHECK: error: invalid operand for instruction
+  subu  $4, end + 4           # CHECK: error: invalid operand for instruction
+  subu  $4, end               # CHECK: error: invalid operand for instruction
+  subu  $4, sp                # CHECK: error: invalid operand for instruction
+
+$start:

test/MC/Mips/macro-aliases.s

+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 %s -show-inst | FileCheck %s
+
+# Test that subu accepts constant operands and inverts them when
+# rendering the operand.
+
+  subu  $4, $4, 4          # CHECK: ADDiu
+                           # CHECK; Imm:-4
+  subu  $gp, $gp, 4        # CHECK: ADDiu
+                           # CHECK; Imm:-4
+  subu  $sp, $sp, 4        # CHECK: ADDiu
+                           # CHECK; Imm:-4
+  subu  $4, $4, -4         # CHECK: ADDiu
+                           # CHECK; Imm:4
+  subu  $gp, $gp, -4       # CHECK: ADDiu
+                           # CHECK; Imm:4
+  subu  $sp, $sp, -4       # CHECK: ADDiu
+                           # CHECK; Imm:4
+  subu  $sp, $sp, -(4 + 4) # CHECK: ADDiu
+                           # CHECK: Imm:8
+
+  subu  $4, 8              # CHECK: ADDiu
+                           # CHECK; Imm:-8
+  subu  $gp, 8             # CHECK: ADDiu
+                           # CHECK; Imm:-8
+  subu  $sp, 8             # CHECK: ADDiu
+                           # CHECK; Imm:-8
+  subu  $4, -8             # CHECK: ADDiu
+                           # CHECK; Imm:8
+  subu  $gp, -8            # CHECK: ADDiu
+                           # CHECK; Imm:8
+  subu  $sp, -8            # CHECK: ADDiu
+                           # CHECK; Imm:8
+  subu  $sp, -(4 + 4)      # CHECK: ADDiu
+                           # CHECK: Imm:8
+