[InstCombine] Fix a weakness in canEvaluateZExtd around 'and' instructions

[craig.topper]

Summary

If the bitsToClear from the LHS of an 'and' comes back non-zero, but all of those bits are known zero on the RHS, we can reset bitsToClear.

Without this, the 'or' in the modified test case blocks the transform because it has non-zero bits in its RHS in those bits.

[craig.topper]

Remove TODO from test case

lib/Transforms/InstCombine/InstCombineCasts.cpp

case Instruction::Mul:
     // If the operation is an AND/OR/XOR and the bits to clear are zero in the
     // other side, BitsToClear is ok.
     if (Tmp == 0 && I->isBitwiseLogicOp()) {
       // We use MaskedValueIsZero here for generality, but the case we care
       // about the most is constant RHS.
       unsigned VSize = V->getType()->getScalarSizeInBits();
       if (IC.MaskedValueIsZero(I->getOperand(1),
                                APInt::getHighBitsSet(VSize, BitsToClear),
-                               0, CxtI))
+                               0, CxtI)) {
+        // If this is an And instruction and all of the BitsToClear are
+        // known to be zero we can reset BitsToClear.
+        if (Opc == Instruction::And)
+          BitsToClear = 0;
         return true;
       }
+    }
 
     // Otherwise, we don't know how to analyze this BitsToClear case yet.
     return false;
 
   case Instruction::Shl: {
     // We can promote shl(x, cst) if we can promote x.  Since shl overwrites the
     // upper bits we can reduce BitsToClear by the shift amount.
     const APInt *Amt;

test/Transforms/InstCombine/cast.ll

;
   %1 = icmp eq i32 %a, -2
   %2 = sext i1 %1 to i8
   %3 = xor i8 %2, -1
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
 
 ; We should be able to remove the zext and trunc here.
-; TODO: This is currently blocked because we don't realize the 'and' has cleared the extra bits that would be shifted in widening the lshr.
 define i32 @test95(i32 %x) {
 ; CHECK-LABEL: @test95(
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 6
-; CHECK-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = or i8 [[TMP3]], 40
-; CHECK-NEXT:    [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
+; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = trunc i32 %x to i8
   %2 = lshr i8 %1, 6
   %3 = and i8 %2, 2
   %4 = or i8 %3, 40
   %5 = zext i8 %4 to i32
   ret i32 %5
 }