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[InstCombine] Fix a weakness in canEvaluateZExtd around 'and' instructions
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Authored by craig.topper on Aug 20 2017, 2:53 PM.

Details

Summary

If the bitsToClear from the LHS of an 'and' comes back non-zero, but all of those bits are known zero on the RHS, we can reset bitsToClear.

Without this, the 'or' in the modified test case blocks the transform because it has non-zero bits in its RHS in those bits.

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rL LLVM

Event Timeline

craig.topper created this revision.

Remove TODO from test case

davide accepted this revision.Aug 21 2017, 5:25 AM
This revision is now accepted and ready to land.Aug 21 2017, 5:25 AM
This revision was automatically updated to reflect the committed changes.