[X86] Allow xacquire/xrelease prefixes

[coby]

Summary

Allow those prefixes on assembly code

[RKSimon]

lib/Target/X86/AsmParser/X86AsmParser.cpp

2471

Why did you move data32 to the top instead of leaving next to data16?

[coby]

Why did you move data32 to the top instead of leaving next to data16?

no particular reason. back in place

[RKSimon]

Please can you add tests for the intel-syntax acquire/release as well?

[coby]

@RKSimon : Please can you add tests for the intel-syntax acquire/release as well?

Added.

[craig.topper]

LGTM

lib/Target/X86/AsmParser/X86AsmParser.cpp

if (ComparisonCode != ~0U) {
 
       PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
     }
   }
 
   Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
 
   // Determine whether this is an instruction prefix.
-  bool isPrefix =
-    Name == "lock" || Name == "rep" ||
-    Name == "repe" || Name == "repz" ||
-    Name == "repne" || Name == "repnz" ||
-    Name == "rex64" || Name == "data16" || Name == "data32";
+  // FIXME:
+  // Enhace prefixes integrity robustness. for example, following forms
+  // are currently tolerated:
+  // repz repnz <insn>    ; GAS errors for the use of two similar prefixes
+  // lock addq %rax, %rbx ; Destination operand must be of memory type
+  // xacquire <insn>      ; xacquire must be accompanied by 'lock'
+  bool isPrefix = StringSwitch<bool>(Name)
+    .Cases("lock",
+           "rep",       "repe",
+           "repz",      "repne",
+           "repnz",     "rex64",
+           "data32",    "data16",   true)
+    .Cases("xacquire",  "xrelease", true)
+    .Cases("acquire",   "release",  isParsingIntelSyntax())
+    .Default(false);
 
   bool CurlyAsEndOfStatement = false;
   // This does the actual operand parsing.  Don't parse any more if we have a
   // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
   // just want to parse the "lock" as the first instruction and the "incl" as
   // the next one.
   if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
 

lib/Target/X86/X86InstrInfo.td

 def : MnemonicAlias<"smovb", "movsb", "att">;
 def : MnemonicAlias<"smovw", "movsw", "att">;
 def : MnemonicAlias<"smovl", "movsl", "att">;
 def : MnemonicAlias<"smovq", "movsq", "att">;
 
 def : MnemonicAlias<"ud2a",  "ud2",  "att">;
 def : MnemonicAlias<"verrw", "verr", "att">;
 
+// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release'
+def : MnemonicAlias<"acquire", "xacquire", "intel">;
+def : MnemonicAlias<"release", "xrelease", "intel">;
+
 // System instruction aliases.
 def : MnemonicAlias<"iret",    "iretw",    "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"iret",    "iretl",    "att">, Requires<[Not16BitMode]>;
 def : MnemonicAlias<"sysret",  "sysretl",  "att">;
 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
 
 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;

test/MC/X86/x86-64.s

 // CHECK: encoding: [0x48,0x09,0x37]
 
 lock xorq %rsi, (%rdi)
 // CHECK: lock
 // CHECK: encoding: [0xf0]
 // CHECK: xorq %rsi, (%rdi)
 // CHECK: encoding: [0x48,0x31,0x37]
 
+xacquire lock addq %rax, (%rax)
+// CHECK: xacquire
+// CHECK: encoding: [0xf2]
+// CHECK: lock
+// CHECK: encoding: [0xf0]
+// CHECK: addq %rax, (%rax)
+// CHECK: encoding: [0x48,0x01,0x00]
+
+xrelease lock addq %rax, (%rax)
+// CHECK: xrelease
+// CHECK: encoding: [0xf3]
+// CHECK: lock
+// CHECK: encoding: [0xf0]
+// CHECK: addq %rax, (%rax)
+// CHECK: encoding: [0x48,0x01,0x00]
 
 // rdar://8033482
 rep movsl
 // CHECK: rep
 // CHECK: encoding: [0xf3]
 // CHECK: movsl
 // CHECK: encoding: [0xa5]