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[x86] Enable some support for lowerVectorShuffleWithUndefHalf with AVX-512
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Authored by craig.topper on Aug 10 2017, 6:52 PM.

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Summary

This teaches 512-bit shuffles to detect unused halfs in order to reduce shuffle size.

We may need to refine the 512-bit exit point. I couldn't remember if we had good cross lane shuffles for 8/16 bit with AVX-512 or not.

I believe this is step towards being able to handle D36454 without a special case.

From here we need to improve our ability to combine extract_subvector with insert_subvector and other extract_subvectors. And we need to support narrowing binary operations where we don't demand all elements. This may be improvements to DAGCombiner::narrowExtractedVectorBinOp(by recognizing an insert_subvector in addition to concat) or we may need a target specific combiner.

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rL LLVM

Event Timeline

craig.topper created this revision.Aug 10 2017, 6:52 PM
RKSimon accepted this revision.Aug 11 2017, 5:21 AM

LGTM

lib/Target/X86/X86ISelLowering.cpp
12259 ↗(On Diff #110665)

256 or 512-bit vector

This revision is now accepted and ready to land.Aug 11 2017, 5:21 AM
jbhateja accepted this revision.Aug 11 2017, 6:08 AM

LGTM , I shall TRY to use this already written routine for D36454

This revision was automatically updated to reflect the committed changes.