[mips] Lift the assertion on the types that can be used with MipsGPRel

[sdardis]

Summary

Post commit review of rL308619 highlighted the need for handling N64
with -fno-pic. Testing reveale a stale assert when generating a GP
relative addressing mode.

This patch removes that assert and adds the necessary patterns for
MIPS64 to perform gp relative addressing with -fno-pic
(and the implicit -mno-abicalls + -mgpopt).

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
                 (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
 
 }
 
 // highest/higher/hi/lo relocs
 let AdditionalPredicates = [NotInMicroMips] in
 defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
 
+// gp_rel relocs
+def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
+              (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64;
+def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)),
+              (DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64;
+
 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
 def : WrapperPat<tconstpool, DADDiu, GPR64>;
 def : WrapperPat<texternalsym, DADDiu, GPR64>;
 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
 def : WrapperPat<tjumptable, DADDiu, GPR64>;
 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
 
 

llvm/trunk/lib/Target/Mips/MipsISelLowering.h

class TargetRegisterClass;
    }
 
     // This method creates the following nodes, which are necessary for
     // computing a symbol's address using gp-relative addressing:
     //
     // (add $gp, %gp_rel(sym))
     template <class NodeTy>
     SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
-                         SelectionDAG &DAG) const {
-      assert(Ty == MVT::i32);
+                         SelectionDAG &DAG, bool IsN64) const {
       SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
-      return DAG.getNode(ISD::ADD, DL, Ty,
-                         DAG.getRegister(Mips::GP, Ty),
-                         DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
-                                     GPRel));
+      return DAG.getNode(
+          ISD::ADD, DL, Ty,
+          DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
+          DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
     }
 
     /// This function fills Ops, which is the list of operands that will later
     /// be used when a function call node is created. It also generates
     /// copyToReg nodes to set up argument registers.
     virtual void
     getOpndList(SmallVectorImpl<SDValue> &Ops,
                 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
 
   if (!isPositionIndependent()) {
     const MipsTargetObjectFile *TLOF =
         static_cast<const MipsTargetObjectFile *>(
             getTargetMachine().getObjFileLowering());
     const GlobalObject *GO = GV->getBaseObject();
     if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
       // %gp_rel relocation
-      return getAddrGPRel(N, SDLoc(N), Ty, DAG);
+      return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
 
                                  // %hi/%lo relocation
     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
                                  // %highest/%higher/%hi/%lo relocation
                                  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
   }
 
   // Every other architecture would use shouldAssumeDSOLocal in here, but
lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
   if (!isPositionIndependent()) {
     const MipsTargetObjectFile *TLOF =
         static_cast<const MipsTargetObjectFile *>(
             getTargetMachine().getObjFileLowering());
 
     if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
                                        getTargetMachine()))
       // %gp_rel relocation
-      return getAddrGPRel(N, SDLoc(N), Ty, DAG);
+      return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
 
     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
   }
 
  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
 def NotCnMips    :    Predicate<"!Subtarget->hasCnMips()">,
                       AssemblerPredicate<"!FeatureCnMips">;
 def IsSym32     :     Predicate<"Subtarget->HasSym32()">,
                       AssemblerPredicate<"FeatureSym32">;
 def IsSym64     :     Predicate<"!Subtarget->HasSym32()">,
                       AssemblerPredicate<"!FeatureSym32">;
+def IsN64       :     Predicate<"Subtarget->isABI_N64()">;
+def IsNotN64    :     Predicate<"!Subtarget->isABI_N64()">;
 def RelocNotPIC :     Predicate<"!TM.isPositionIndependent()">;
 def RelocPIC    :     Predicate<"TM.isPositionIndependent()">;
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">;
 def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
                       AssemblerPredicate<"!FeatureMips16">;
 def NotDSP :          Predicate<"!Subtarget->hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"FeatureMicroMips">;

 class ASE_NOT_DSP {
   list<Predicate> InsnPredicates = [NotDSP];
 }
 
 class MADD4 {
   list<Predicate> AdditionalPredicates = [HasMadd4];
 }
 
+// Classses used for separating expansions that differ based on the ABI in
+// use.
+class ABI_N64 {
+  list<Predicate> AdditionalPredicates = [IsN64];
+}
+
+class ABI_NOT_N64 {
+  list<Predicate> AdditionalPredicates = [IsNotN64];
+}
+
 //===----------------------------------------------------------------------===//
 
 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
   let EncodingPredicates = [HasStdEnc];
 }
 
 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
   InstAlias<Asm, Result, Emit>, PredicateControl;

 
 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
 
 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>;
 
 // gp_rel relocs
 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
-              (ADDiu GPR32:$gp, tglobaladdr:$in)>;
+              (ADDiu GPR32:$gp, tglobaladdr:$in)>, ABI_NOT_N64;
 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
-              (ADDiu GPR32:$gp, tconstpool:$in)>;
+              (ADDiu GPR32:$gp, tconstpool:$in)>, ABI_NOT_N64;
 
 // wrapper_pic
 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
       MipsPat<(MipsWrapper RC:$gp, node:$in),
               (ADDiuOp RC:$gp, node:$in)>;
 
 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
 def : WrapperPat<tconstpool, ADDiu, GPR32>;

llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll

-; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \
+; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \
 ; RUN:     -relocation-model=static -mattr=+noabicalls -mgpopt \
-; RUN:   | FileCheck %s --check-prefixes=BASIC,COMMON
-; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \
+; RUN:   | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32
+; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \
 ; RUN:     -relocation-model=static -mattr=+noabicalls -mgpopt -membedded-data \
-; RUN:   | FileCheck %s --check-prefixes=EMBDATA,COMMON
+; RUN:   | FileCheck %s --check-prefixes=EMBDATA,COMMON,ADDR32
+
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN:     -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n64 \
+; RUN:   | FileCheck %s --check-prefixes=BASIC,COMMON,N64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN:     -relocation-model=static -mattr=+noabicalls,+sym32 -mgpopt -target-abi n64 \
+; RUN:   | FileCheck %s --check-prefixes=BASIC,COMMON,N64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN:     -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n32 \
+; RUN:   | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32
 
 ; Test the layout of objects when compiling for static, noabicalls environment.
 
 %struct.anon = type { i32, i32 }
 
+; Check that when synthesizing a pointer to the second element of foo, that
+; we use the correct addition operation. O32 and N32 have 32-bit address
+; spaces, so they use addiu. N64 has a 64bit address space, but has a submode
+; where symbol sizes are 32 bits. In those cases we use daddiu.
+
+; CHECK-LABEL: A1:
+; N64:       daddiu ${{[0-9]+}}, $gp, %gp_rel(foo)
+; ADDR32:    addiu ${{[0-9]+}}, $gp, %gp_rel(foo)
+
 ; BASIC: .type  s0,@object
 ; BASIC-NEXT: .section .sdata,"aw",@progbits
 
 ; EMDATA: .type  s0,@object
 ; EMDATA-NEXT: .section .rodata,"a",@progbits
 
 @s0 = constant [8 x i8] c"AAAAAAA\00", align 4