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Differential D3568

Add StatusText to the Processor class in Target.td to allow adding 'experimental' or 'highly experimental' annotations to processors.
AbandonedPublic

Authored by dsanders on Apr 30 2014, 6:55 AM.

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dsanders updated this revision to Diff 8975.Apr 30 2014, 6:55 AM
dsanders retitled this revision from to Add StatusText to the Processor class in Target.td to allow adding 'experimental' or 'highly experimental' annotations to processors..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added a subscriber: Unknown Object (MLST).
dsanders added a comment.Apr 30 2014, 7:00 AM

The follow-on which uses the StatusText field is at http://reviews.llvm.org/D3569

dsanders updated this revision to Diff 9164.May 7 2014, 6:42 AM
  • Do without the ability to mark CPU's as experimental for the moment. This removes the dependency on D3568
dsanders updated this revision to Diff 9165.May 7 2014, 6:45 AM

Undo the last change. I meant to update D3569 instead of D3568. Sorry for the noise.

emaste added a subscriber: emaste.May 7 2014, 7:09 AM
dsanders abandoned this revision.Sep 23 2014, 5:41 AM

Revision Contents

PathSize
lib/
Target/
Mips/
26 lines
3 lines
13 lines
test/
MC/
Mips/
mips1/
3 lines
3 lines
mips2/
3 lines
3 lines
mips3/
3 lines
3 lines
mips5/
3 lines
3 lines

Diff 9164

lib/Target/Mips/Mips.td

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
"Enable 'conditional move' instructions.">; "Enable 'conditional move' instructions.">;
def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
"Enable 'byte/half swap' instructions.">; "Enable 'byte/half swap' instructions.">;
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
"Enable 'count leading bits' instructions.">; "Enable 'count leading bits' instructions.">;
def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true", def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
"Enable 'FP indexed load/store' instructions.">; "Enable 'FP indexed load/store' instructions.">;
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
"Mips I ISA Support [highly experimental]">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips II ISA Support [highly experimental]",
[FeatureMips1]>;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support", "Mips32 ISA Support",
[FeatureCondMov, FeatureBitCount]>; [FeatureMips2, FeatureCondMov, FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support", "Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg, FeatureSwap, [FeatureMips32, FeatureSEInReg, FeatureSwap,
FeatureFPIdx]>; FeatureFPIdx]>;
// FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
// list but for now it doesn't matter since FPIdx isn't actually attached
// to any instructions.
def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
"MIPS III ISA Support [highly experimental]",
[FeatureMips2, FeatureGP64Bit, FeatureFP64Bit]>;
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
"Mips4", "MIPS IV ISA Support", "Mips4", "MIPS IV ISA Support",
[FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx, [FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
FeatureCondMov]>; def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
"MIPS V ISA Support [highly experimental]",
[FeatureMips4]>;
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
"Mips64", "Mips64 ISA Support", "Mips64", "Mips64 ISA Support",
[FeatureMips4, FeatureMips32, FeatureFPIdx]>; [FeatureMips5, FeatureMips32, FeatureFPIdx]>;
def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
"Mips64r2", "Mips64r2 ISA Support", "Mips64r2", "Mips64r2 ISA Support",
[FeatureMips64, FeatureMips32r2]>; [FeatureMips64, FeatureMips32r2]>;
def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
"Mips16 mode">; "Mips16 mode">;
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
Show All 11 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips processors supported. // Mips processors supported.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features> class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, MipsGenericItineraries, Features>; : Processor<Name, MipsGenericItineraries, Features>;
def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
def : Proc<"mips32", [FeatureMips32, FeatureO32]>; def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>; def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
def : Proc<"mips4", [FeatureMips4, FeatureN64]>; def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
def : Proc<"mips64", [FeatureMips64, FeatureN64]>; def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>; def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
def : Proc<"mips16", [FeatureMips16, FeatureO32]>; def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>; def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
def MipsAsmParser : AsmParser { def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0; let ShouldEmitMatchRegisterName = 0;
let MnemonicContainsDot = 1; let MnemonicContainsDot = 1;
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lib/Target/Mips/MipsSubtarget.h

Show All 31 Lines
public: public:
// NOTE: O64 will not be supported. // NOTE: O64 will not be supported.
enum MipsABIEnum { enum MipsABIEnum {
UnknownABI, O32, N32, N64, EABI UnknownABI, O32, N32, N64, EABI
}; };
protected: protected:
enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 }; enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
Mips64, Mips64r2 };
// Mips architecture version // Mips architecture version
MipsArchEnum MipsArchVersion; MipsArchEnum MipsArchVersion;
// Mips supported ABIs // Mips supported ABIs
MipsABIEnum MipsABI; MipsABIEnum MipsABI;
// IsLittle - The target is Little Endian // IsLittle - The target is Little Endian
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lib/Target/Mips/MipsSubtarget.cpp

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines if (InMips16Mode && !TM->Options.UseSoftFloat) {
InMips16HardFloat = true; InMips16HardFloat = true;
} }
PreviousInMips16Mode = InMips16Mode; PreviousInMips16Mode = InMips16Mode;
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName); InstrItins = getInstrItineraryForCPU(CPUName);
// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
// MIPS-V. They have not been tested and currently exist for the integrated
// assembler only.
if (MipsArchVersion == Mips1)
report_fatal_error("Code generation for MIPS-I is not implemented", false);
if (MipsArchVersion == Mips2)
report_fatal_error("Code generation for MIPS-II is not implemented", false);
if (MipsArchVersion == Mips3)
report_fatal_error("Code generation for MIPS-III is not implemented",
false);
if (MipsArchVersion == Mips5)
report_fatal_error("Code generation for MIPS-V is not implemented", false);
// Assert exactly one ABI was chosen. // Assert exactly one ABI was chosen.
assert(MipsABI != UnknownABI); assert(MipsABI != UnknownABI);
assert((((getFeatureBits() & Mips::FeatureO32) != 0) + assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
((getFeatureBits() & Mips::FeatureEABI) != 0) + ((getFeatureBits() & Mips::FeatureEABI) != 0) +
((getFeatureBits() & Mips::FeatureN32) != 0) + ((getFeatureBits() & Mips::FeatureN32) != 0) +
((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
// Check if Architecture and ABI are compatible. // Check if Architecture and ABI are compatible.
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test/MC/Mips/mips1/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# FIXME: Test MIPS-I instead of MIPS32 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
tlbp tlbp
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr
lwc0 c0_entrylo,-7321($s2) lwc0 c0_entrylo,-7321($s2)
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
swc0 c0_prid,18904($s3) swc0 c0_prid,18904($s3)

test/MC/Mips/mips1/valid.s

# Instructions that are valid # Instructions that are valid
# #
# FIXME: Test MIPS-I instead of MIPS32 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding: abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16 abs.s $f9,$f16
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $t5,$t1,26322 addi $t5,$t1,26322
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test/MC/Mips/mips2/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# FIXME: Test MIPS-II instead of MIPS32 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
ldc3 $29,-28645($s1) ldc3 $29,-28645($s1)
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
sdc3 $12,5835($t2) sdc3 $12,5835($t2)
tlbp tlbp
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr

test/MC/Mips/mips2/valid.s

# Instructions that are valid # Instructions that are valid
# #
# FIXME: Test MIPS-II instead of MIPS32 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding abs.d $f7,$f25 # CHECK: encoding
abs.s $f9,$f16 abs.s $f9,$f16
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $t5,$t1,26322 addi $t5,$t1,26322
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test/MC/Mips/mips3/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# FIXME: Test MIPS-III instead of MIPS-IV # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
tlbp tlbp
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr

test/MC/Mips/mips3/valid.s

# Instructions that are valid # Instructions that are valid
# #
# FIXME: Test MIPS-III instead of MIPS-IV # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding abs.d $f7,$f25 # CHECK: encoding
abs.s $f9,$f16 abs.s $f9,$f16
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $t5,$t1,26322 addi $t5,$t1,26322
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# FIXME: Test MIPS-V instead of MIPS64 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
alnv.ps $f12,$f18,$f30,$t4 alnv.ps $f12,$f18,$f30,$t4
c.eq.d $fcc1,$f15,$f15 c.eq.d $fcc1,$f15,$f15
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test/MC/Mips/mips5/valid.s

# Instructions that are valid # Instructions that are valid
# #
# FIXME: Test MIPS-V instead of MIPS64 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
.set noat .set noat
abs.d $f7,$f25 # CHECK: encoding abs.d $f7,$f25 # CHECK: encoding
abs.s $f9,$f16 abs.s $f9,$f16
add $s7,$s2,$a1 add $s7,$s2,$a1
add.d $f1,$f7,$f29 add.d $f1,$f7,$f29
add.s $f8,$f21,$f24 add.s $f8,$f21,$f24
addi $t5,$t1,26322 addi $t5,$t1,26322
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines