[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V

[dsanders]

Summary

These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

[dsanders]

• Do without the ability to mark CPU's as experimental for the moment. This removes the dependency on D3568

[vmedic]

Again, I'm not sure if the 80 characters per line limit applies to test files, since the run commands exceed this limit. One line in the td files also does that. Other then that, the patch looks good to me.

lib/Target/Mips/Mips.td

95

Exceeds 80 characters

[dsanders]

Thanks. Test files generally aren't following the 80 column limit so I don't think that's a problem.

lib/Target/Mips/Mips.td

 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
                                 "Enable 'conditional move' instructions.">;
 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
                                 "Enable 'byte/half swap' instructions.">;
 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
                                 "Enable 'count leading bits' instructions.">;
 def FeatureFPIdx       : SubtargetFeature<"fpidx", "HasFPIdx", "true",
                                 "Enable 'FP indexed load/store' instructions.">;
+def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
+                                "Mips I ISA Support [highly experimental]">;
+def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
+                                "Mips II ISA Support [highly experimental]",
+                                [FeatureMips1]>;
 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
                                 "Mips32 ISA Support",
-                                [FeatureCondMov, FeatureBitCount]>;
+                                [FeatureMips2, FeatureCondMov, FeatureBitCount]>;
 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
                                 "Mips32r2", "Mips32r2 ISA Support",
                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
                                  FeatureFPIdx]>;
+// FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
+//        list but for now it doesn't matter since FPIdx isn't actually attached
+//        to any instructions.
+def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
+                                "MIPS III ISA Support [highly experimental]",
+                                [FeatureMips2, FeatureGP64Bit, FeatureFP64Bit]>;
 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
                                 "Mips4", "MIPS IV ISA Support",
-                                [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
-                                 FeatureCondMov]>;
+                                [FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
+def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
+                                "MIPS V ISA Support [highly experimental]",
+                                [FeatureMips4]>;
 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
                                 "Mips64", "Mips64 ISA Support",
-                                [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
+                                [FeatureMips5, FeatureMips32, FeatureFPIdx]>;
 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
                                 "Mips64r2", "Mips64r2 ISA Support",
                                 [FeatureMips64, FeatureMips32r2]>;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
                                       "Mips16 mode">;
 
 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;

 
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
 //===----------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, MipsGenericItineraries, Features>;
 
+def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
+def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
+
+def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
+def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
   let MnemonicContainsDot = 1;

lib/Target/Mips/MipsSubtarget.h

 
 public:
   // NOTE: O64 will not be supported.
   enum MipsABIEnum {
     UnknownABI, O32, N32, N64, EABI
   };
 
 protected:
-  enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 };
+  enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
+                      Mips64, Mips64r2 };
 
   // Mips architecture version
   MipsArchEnum MipsArchVersion;
 
   // Mips supported ABIs
   MipsABIEnum MipsABI;
 
   // IsLittle - The target is Little Endian

lib/Target/Mips/MipsSubtarget.cpp

if (InMips16Mode && !TM->Options.UseSoftFloat) {
     InMips16HardFloat = true;
   }
 
   PreviousInMips16Mode = InMips16Mode;
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 
+  // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
+  // MIPS-V. They have not been tested and currently exist for the integrated
+  // assembler only.
+  if (MipsArchVersion == Mips1)
+    report_fatal_error("Code generation for MIPS-I is not implemented", false);
+  if (MipsArchVersion == Mips2)
+    report_fatal_error("Code generation for MIPS-II is not implemented", false);
+  if (MipsArchVersion == Mips3)
+    report_fatal_error("Code generation for MIPS-III is not implemented",
+                       false);
+  if (MipsArchVersion == Mips5)
+    report_fatal_error("Code generation for MIPS-V is not implemented", false);
+
   // Assert exactly one ABI was chosen.
   assert(MipsABI != UnknownABI);
   assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
           ((getFeatureBits() & Mips::FeatureEABI) != 0) +
           ((getFeatureBits() & Mips::FeatureN32) != 0) +
           ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
 
   // Check if Architecture and ABI are compatible.

test/MC/Mips/mips1/valid-xfail.s

 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
-# FIXME: Test MIPS-I instead of MIPS32
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
   .set noat
   tlbp
   tlbr
   tlbwi
   tlbwr
   lwc0  c0_entrylo,-7321($s2)
   lwc3  $10,-32265($k0)
   swc0  c0_prid,18904($s3)

test/MC/Mips/mips1/valid.s

 # Instructions that are valid
 #
-# FIXME: Test MIPS-I instead of MIPS32
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
 
   .set noat
   abs.d $f7,$f25          # CHECK: encoding:
   abs.s $f9,$f16
   add $s7,$s2,$a1
   add.d $f1,$f7,$f29
   add.s $f8,$f21,$f24
   addi  $t5,$t1,26322

test/MC/Mips/mips2/valid-xfail.s

 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
-# FIXME: Test MIPS-II instead of MIPS32
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
   .set noat
   ldc3  $29,-28645($s1)
   lwc3  $10,-32265($k0)
   sdc3  $12,5835($t2)
   tlbp
   tlbr
   tlbwi
   tlbwr

test/MC/Mips/mips2/valid.s

 # Instructions that are valid
 #
-# FIXME: Test MIPS-II instead of MIPS32
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
 
   .set noat
   abs.d $f7,$f25            # CHECK: encoding
   abs.s $f9,$f16
   add $s7,$s2,$a1
   add.d $f1,$f7,$f29
   add.s $f8,$f21,$f24
   addi  $t5,$t1,26322

test/MC/Mips/mips3/valid-xfail.s

 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
-# FIXME: Test MIPS-III instead of MIPS-IV
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
   .set noat
   lwc3  $10,-32265($k0)
   tlbp
   tlbr
   tlbwi
   tlbwr

test/MC/Mips/mips3/valid.s

 # Instructions that are valid
 #
-# FIXME: Test MIPS-III instead of MIPS-IV
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
 
   .set noat
   abs.d $f7,$f25 # CHECK: encoding
   abs.s $f9,$f16
   add $s7,$s2,$a1
   add.d $f1,$f7,$f29
   add.s $f8,$f21,$f24
   addi  $t5,$t1,26322

test/MC/Mips/mips5/valid-xfail.s

 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
-# FIXME: Test MIPS-V instead of MIPS64
-# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64   | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5   | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
         .set noat
   abs.ps  $f22,$f8
   add.ps  $f25,$f27,$f13
   alnv.ps $f12,$f18,$f30,$t4
   c.eq.d  $fcc1,$f15,$f15

test/MC/Mips/mips5/valid.s

 # Instructions that are valid
 #
-# FIXME: Test MIPS-V instead of MIPS64
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64   | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5   | FileCheck %s
 
         .set noat
   abs.d $f7,$f25 # CHECK: encoding
   abs.s $f9,$f16
   add $s7,$s2,$a1
   add.d $f1,$f7,$f29
   add.s $f8,$f21,$f24
   addi  $t5,$t1,26322