[mips][mt][4/7] Add IAS support for dvpe, evpe instructions.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td

class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
   let DecoderNamespace = "Mips";
   let EncodingPredicates = [HasStdEnc];
 }
 
 class OPCODE1<bits<1> Val> {
   bits<1> Value = Val;
 }
 
-def OPCODE_SC_DMT : OPCODE1<0b0>;
-def OPCODE_SC_EMT : OPCODE1<0b1>;
+def OPCODE_SC_D : OPCODE1<0b0>;
+def OPCODE_SC_E : OPCODE1<0b1>;
 
 class FIELD5<bits<5> Val> {
   bits<5> Value = Val;
 }
 
 def FIELD5_1_DMT_EMT  : FIELD5<0b00001>;
 def FIELD5_2_DMT_EMT  : FIELD5<0b01111>;
+def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
 
 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
   bits<32> Inst;
 
   bits<5> rt;
   let Inst{31-26} = 0b010000; // COP0
   let Inst{25-21} = 0b01011;  // MFMC0
   let Inst{20-16} = rt;
   let Inst{15-11} = Op1.Value;
   let Inst{10-6}  = Op2.Value;
   let Inst{5}     = sc.Value;
   let Inst{4-3}   = 0b00;
   let Inst{2-0}   = 0b001;
 }

llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td

 //===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Encodings
 //===----------------------------------------------------------------------===//
 
 class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
-                              OPCODE_SC_DMT>;
+                              OPCODE_SC_D>;
 
 class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
-                              OPCODE_SC_EMT>;
+                              OPCODE_SC_E>;
+
+class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
+                               OPCODE_SC_D>;
+
+class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
+                               OPCODE_SC_E>;
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins);
   string AsmString = !strconcat(instr_asm, "\t$rt");
   list<dag> Pattern = [];
   InstrItinClass Itinerary = Itin;
 }
 
 class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
 
 class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
 
+class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
+
+class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
+
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Definitions
 //===----------------------------------------------------------------------===//
 let hasSideEffects = 1, isNotDuplicable = 1,
     AdditionalPredicates = [NotInMicroMips] in {
   def DMT : DMT_ENC, DMT_DESC, ASE_MT;
 
   def EMT : EMT_ENC, EMT_DESC, ASE_MT;
+
+  def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
+
+  def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
 }
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Definitions
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
 
   def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
+
+  def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
+
+  def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
 }

llvm/trunk/lib/Target/Mips/MipsSchedule.td

 def II_DSRAV            : InstrItinClass;
 def II_DSRL             : InstrItinClass;
 def II_DSRL32           : InstrItinClass;
 def II_DSRLV            : InstrItinClass;
 def II_DSBH             : InstrItinClass;
 def II_DSHD             : InstrItinClass;
 def II_DSUBU            : InstrItinClass;
 def II_DSUB             : InstrItinClass;
+def II_DVPE             : InstrItinClass;
 def II_EMT              : InstrItinClass;
+def II_EVPE             : InstrItinClass;
 def II_EXT              : InstrItinClass; // Any EXT instruction
 def II_FLOOR            : InstrItinClass;
 def II_INS              : InstrItinClass; // Any INS instruction
 def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
 def II_J                : InstrItinClass;
 def II_JAL              : InstrItinClass;
 def II_JALR             : InstrItinClass;
 def II_JALR_HB          : InstrItinClass;
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_DSUB            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DROTR           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DROTR32         , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DROTRV          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DSBH            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DSHD            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DCLO            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DCLZ            , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_DVPE            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_EMT             , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_EVPE            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_EXT             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_INS             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_LUI             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVE            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVF            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN_S          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN_D          , [InstrStage<1,  [ALU]>]>,

llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td

 def : ItinRW<[GenericWriteLoad], [II_LBE, II_LBUE, II_LHE, II_LHUE, II_LWE,
                                   II_LLE]>;
 
 def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>;
 
 // MIPS MT instructions
 // ====================
 
-def : ItinRW<[GenericWriteMove], [II_DMT, II_EMT]>;
+def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
 
 
 // MIPS32R6 and MIPS16e
 // ====================
 
 def : ItinRW<[GenericWriteLoad], [II_LWPC]>;
 
 // MIPS64R6

llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
 0xc1 0x0b 0x60 0x41  # CHECK: dmt
 0xc1 0x0b 0x65 0x41  # CHECK: dmt $5
 0xe1 0x0b 0x60 0x41  # CHECK: emt
 0xe1 0x0b 0x64 0x41  # CHECK: emt $4
+0x01 0x00 0x60 0x41  # CHECK: dvpe
+0x01 0x00 0x66 0x41  # CHECK: dvpe  $6
+0x21 0x00 0x60 0x41  # CHECK: evpe
+0x21 0x00 0x64 0x41  # CHECK: evpe  $4
 

llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
 0x41 0x60 0x0b 0xc1  # CHECK: dmt
 0x41 0x65 0x0b 0xc1  # CHECK: dmt $5
 0x41 0x60 0x0b 0xe1  # CHECK: emt
 0x41 0x64 0x0b 0xe1  # CHECK: emt $4
+0x41 0x60 0x00 0x01  # CHECK: dvpe
+0x41 0x66 0x00 0x01  # CHECK: dvpe  $6
+0x41 0x60 0x00 0x21  # CHECK: evpe
+0x41 0x64 0x00 0x21  # CHECK: evpe  $4
 

llvm/trunk/test/MC/Mips/mt/invalid.s

 # RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>&1 | FileCheck %s
   dmt 4           # CHECK: error: invalid operand for instruction
   dmt $4, $5      # CHECK: error: invalid operand for instruction
   dmt $5, 0($4)   # CHECK: error: invalid operand for instruction
   emt 4           # CHECK: error: invalid operand for instruction
   emt $4, $5      # CHECK: error: invalid operand for instruction
   emt $5, 0($5)   # CHECK: error: invalid operand for instruction
+  dvpe 4          # CHECK: error: invalid operand for instruction
+  dvpe $4, $5     # CHECK: error: invalid operand for instruction
+  dvpe $5, 0($4)  # CHECK: error: invalid operand for instruction
+  evpe 4          # CHECK: error: invalid operand for instruction
+  evpe $4, $5     # CHECK: error: invalid operand for instruction
+  evpe $5, 0($5)  # CHECK: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/mt/valid.s

 # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
 # RUN:   | FileCheck %s
   dmt           # CHECK:  dmt         # encoding: [0x41,0x60,0x0b,0xc1]
   dmt $5        # CHECK:  dmt $5      # encoding: [0x41,0x65,0x0b,0xc1]
   emt           # CHECK:  emt         # encoding: [0x41,0x60,0x0b,0xe1]
   emt $4        # CHECK:  emt $4      # encoding: [0x41,0x64,0x0b,0xe1]
+  dvpe          # CHECK:  dvpe        # encoding: [0x41,0x60,0x00,0x01]
+  dvpe $6       # CHECK:  dvpe  $6    # encoding: [0x41,0x66,0x00,0x01]
+  evpe          # CHECK:  evpe        # encoding: [0x41,0x60,0x00,0x21]
+  evpe $4       # CHECK:  evpe  $4    # encoding: [0x41,0x64,0x00,0x21]
+