[X86] Adding Fast AVX2 Gather as a subtarget feature

[magabari]

Summary

This commit is a preparation for my next commit of supporting x86 AVX2 gathers in loop vectorizer.

Currently there is some processors which dont have a fast hardware support of avx2 gathers and need to disable gather generation for those processors.

test case will be provided in my next commit which support avx2 gather generation.

[RKSimon]

Wouldn't this be better done through X86TTIImpl::getGatherScatterOpCost ?

[magabari]

In D35191#803444, @RKSimon wrote:

Wouldn't this be better done through X86TTIImpl::getGatherScatterOpCost ?

It will be used there, but currently we need to distinguish in which processor we have a profitable gather implementation.
later as noted in the TODO it will be changed to give the cost per processor which is currently not possible.

[craig.topper]

lib/Target/X86/X86Subtarget.h

201

Can we call this HasFastAVX2Gather to match the getter method?

[RKSimon]

test case will be provided in my next commit which support avx2 gather generation.

Can put your next patch up for review now and make it dependent on this?

[magabari]

In D35191#805162, @RKSimon wrote:

test case will be provided in my next commit which support avx2 gather generation.

Can put your next patch up for review now and make it dependent on this?

In D35191#805162, @RKSimon wrote:

test case will be provided in my next commit which support avx2 gather generation.

Can put your next patch up for review now and make it dependent on this?

abandoned. please take at https://reviews.llvm.org/D35348

[magabari]

In D35191#807785, @magabari wrote:

In D35191#805162, @RKSimon wrote:

test case will be provided in my next commit which support avx2 gather generation.

Can put your next patch up for review now and make it dependent on this?

In D35191#805162, @RKSimon wrote:

test case will be provided in my next commit which support avx2 gather generation.

Can put your next patch up for review now and make it dependent on this?

abandoned. please take a look at https://reviews.llvm.org/D35348

lib/Target/X86/X86.td

def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
                                         "PMULLD instruction is slow">;
 // FIXME: This should not apply to CPUs that do not have SSE.
 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
                                 "IsUAMem16Slow", "true",
                                 "Slow unaligned 16-byte memory access">;
 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
                                 "IsUAMem32Slow", "true",
                                 "Slow unaligned 32-byte memory access">;
+// TODO: This should be replaced with cost function per processor later
+def FeatureFastAVX2Gather : SubtargetFeature<"fast-avx2-gathers", 
+                                "HasFastAVX2Gather", "true",
+                                "Has Fast AVX2 Gathers Support">;
 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
                                       "Support SSE 4a instructions",
                                       [FeatureSSE3]>;
 
 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
                                       "Enable AVX instructions",
                                       [FeatureSSE42]>;
 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
   FeatureADX,
   FeatureRDSEED
 ]>;
 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
                                              BDWFeatures.Value, []>;
 def : BroadwellProc<"broadwell">;
 
 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
+  FeatureFastAVX2Gather,
   FeatureMPX,
   FeatureRTM,
   FeatureXSAVEC,
   FeatureXSAVES,
   FeatureSGX,
   FeatureCLFLUSHOPT,
   FeatureFastVectorFSQRT
 ]>;

lib/Target/X86/X86Subtarget.h

protected:
   bool IsPMULLDSlow;
 
   /// True if unaligned memory accesses of 16-bytes are slow.
   bool IsUAMem16Slow;
 
   /// True if unaligned memory accesses of 32-bytes are slow.
   bool IsUAMem32Slow;
 
+  ///  TODO: This should be replaced with cost function per processor later 
+  bool HasFastAVX2Gather;
+
   /// True if SSE operations can have unaligned memory operands.
   /// This may require setting a configuration bit in the processor.
   bool HasSSEUnalignedMem;
 
   /// True if this processor has the CMPXCHG16B instruction;
   /// this is true for most x86-64 chips, but not the first AMD chips.
   bool HasCmpxchg16b;
 
public:
   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
   bool hasMWAITX() const { return HasMWAITX; }
   bool hasCLZERO() const { return HasCLZERO; }
   bool isBTMemSlow() const { return IsBTMemSlow; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isPMULLDSlow() const { return IsPMULLDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
+  bool hasFastAVX2Gather() const { return HasFastAVX2Gather; }
   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
   bool useLeaForSP() const { return UseLeaForSP; }
   bool hasFastPartialYMMorZMMWrite() const {
     return HasFastPartialYMMorZMMWrite;
   }
   bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
   bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }

lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initializeEnvironment() {
   HasSGX = false;
   HasCLFLUSHOPT = false;
   HasCLWB = false;
   IsBTMemSlow = false;
   IsPMULLDSlow = false;
   IsSHLDSlow = false;
   IsUAMem16Slow = false;
   IsUAMem32Slow = false;
+  HasFastAVX2Gather = false;
   HasSSEUnalignedMem = false;
   HasCmpxchg16b = false;
   UseLeaForSP = false;
   HasFastPartialYMMorZMMWrite = false;
   HasFastScalarFSQRT = false;
   HasFastVectorFSQRT = false;
   HasFastLZCNT = false;
   HasFastSHLDRotate = false;