[ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter

[bsmith]

Summary

The ARM64 InstPrinter does not print the preferred form of SBFM/UBFM instructions, this patch fixes this such that SBFIZ/SBFX/SXTB etc are instead printed where preferred. Additionally 64-bit variants of UXTB/H/W should never be printed since they are not part of the architecture, but rather a logical extension of the aliases.

[t.p.northover]

Hi Bradley,

This looks reasonable as a stopgap. The BFM assembly hacks are all fairly nasty though; I'm hoping to remove them soon.

Cheers.

Tim.

lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp

void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
   // SBFM/UBFM should print to a nicer aliased form if possible.
   if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
       Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
     const MCOperand &Op0 = MI->getOperand(0);
     const MCOperand &Op1 = MI->getOperand(1);
     const MCOperand &Op2 = MI->getOperand(2);
     const MCOperand &Op3 = MI->getOperand(3);
 
-    if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
-      bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
+    bool Is64Bit = (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri);
+    if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
       const char *AsmMnemonic = nullptr;
 
       switch (Op3.getImm()) {
       default:
         break;
       case 7:
-        AsmMnemonic = IsSigned ? "sxtb" : "uxtb";
+        if (IsSigned)
+          AsmMnemonic = "sxtb";
+        else if (!Is64Bit)
+          AsmMnemonic = "uxtb";
         break;
       case 15:
-        AsmMnemonic = IsSigned ? "sxth" : "uxth";
+        if (IsSigned)
+          AsmMnemonic = "sxth";
+        else if (!Is64Bit)
+          AsmMnemonic = "uxth";
         break;
       case 31:
-        // *xtw is only valid for 64-bit operations.
-        if (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri)
-          AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
+        // *xtw is only valid for signed 64-bit operations.
+        if (Is64Bit && IsSigned)
+          AsmMnemonic = "sxtw";
         break;
       }
 
       if (AsmMnemonic) {
         O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
           << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
         printAnnotation(O, Annot);
         return;
if (Op2.isImm() && Op3.isImm()) {
       }
       if (AsmMnemonic) {
         O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
           << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
         printAnnotation(O, Annot);
         return;
       }
     }
+
+    // SBFIZ/UBFIZ aliases
+    if (Op2.getImm() > Op3.getImm()) {
+      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
+        << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
+        << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
+      printAnnotation(O, Annot);
+      return;
+    }
+
+    // Otherwise SBFX/UBFX is the prefered form
+    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
+      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
+      << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
+    printAnnotation(O, Annot);
+    return;
   }
 
   // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
   // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
   // printed.
   if ((Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi ||
        Opcode == ARM64::MOVNXi || Opcode == ARM64::MOVNWi) &&
       MI->getOperand(1).isExpr()) {

test/CodeGen/AArch64/bitfield.ll

; CHECK-LABEL: test_extendw:
 
   %sxt64 = sext i32 %var to i64
   store volatile i64 %sxt64, i64* @var64
 ; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}}
 
   %uxt64 = zext i32 %var to i64
   store volatile i64 %uxt64, i64* @var64
 ; CHECK-AARCH64: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #0, #32
-; CHECK-ARM64: uxtw {{x[0-9]+}}, {{w[0-9]+}}
+; CHECK-ARM64: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #32
   ret void
 }
 
 define void @test_shifts(i32 %val32, i64 %val64) {
 ; CHECK-LABEL: test_shifts:
 
   %shift1 = ashr i32 %val32, 31
   store volatile i32 %shift1, i32* @var32

 define void @test_sext_inreg_64(i64 %in) {
 ; CHECK-LABEL: test_sext_inreg_64:
 
 ; i1 doesn't have an official alias, but crops up and is handled by
 ; the bitfield ops.
   %trunc_i1 = trunc i64 %in to i1
   %sext_i1 = sext i1 %trunc_i1 to i64
   store volatile i64 %sext_i1, i64* @var64
-; CHECK-AARCH64: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
-; CHECK-ARM64: sbfm {{x[0-9]+}}, {{x[0-9]+}}, #0, #0
+; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
 
   %trunc_i8 = trunc i64 %in to i8
   %sext_i8 = sext i8 %trunc_i8 to i64
   store volatile i64 %sext_i8, i64* @var64
 ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
 
   %trunc_i16 = trunc i64 %in to i16
   %sext_i16 = sext i16 %trunc_i16 to i64

 ; CHECK-LABEL: test_sext_inreg_from_32:
 
   %small = trunc i32 %in to i1
   %ext = sext i1 %small to i64
 
   ; Different registers are of course, possible, though suboptimal. This is
   ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit
   ; sbfx rather than just 32-bits.
-; CHECK-AARCH64: sbfx x0, x0, #0, #1
-; CHECK-ARM64: sbfm x0, x0, #0, #0
+; CHECK: sbfx x0, x0, #0, #1
   ret i64 %ext
 }
 
 
 define i32 @test_ubfx32(i32* %addr) {
 ; CHECK-LABEL: test_ubfx32:
-; CHECK-AARCH64: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
-; CHECK-ARM64: ubfm {{w[0-9]+}}, {{w[0-9]+}}, #23, #25
+; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
 
    %fields = load i32* %addr
    %shifted = lshr i32 %fields, 23
    %masked = and i32 %shifted, 7
    ret i32 %masked
 }
 
 define i64 @test_ubfx64(i64* %addr) {
 ; CHECK-LABEL: test_ubfx64:
-; CHECK-AARCH64: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
-; CHECK-ARM64: ubfm {{x[0-9]+}}, {{x[0-9]+}}, #25, #34
+; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
    %fields = load i64* %addr
    %shifted = lshr i64 %fields, 25
    %masked = and i64 %shifted, 1023
    ret i64 %masked
 }
 
 define i32 @test_sbfx32(i32* %addr) {
 ; CHECK-LABEL: test_sbfx32:
-; CHECK-AARCH64: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
-; CHECK-ARM64: sbfm {{w[0-9]+}}, {{w[0-9]+}}, #6, #8
+; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
 
    %fields = load i32* %addr
    %shifted = shl i32 %fields, 23
    %extended = ashr i32 %shifted, 29
    ret i32 %extended
 }
 
 define i64 @test_sbfx64(i64* %addr) {
 ; CHECK-LABEL: test_sbfx64:
-; CHECK-AARCH64: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
-; CHECK-ARM64: sbfm {{x[0-9]+}}, {{x[0-9]+}}, #0, #62
+; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
 
    %fields = load i64* %addr
    %shifted = shl i64 %fields, 1
    %extended = ashr i64 %shifted, 1
    ret i64 %extended
 }

test/CodeGen/AArch64/bool-loads.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
 
 @var = global i1 0
 
 define i32 @test_sextloadi32() {
 ; CHECK-LABEL: test_sextloadi32
 
   %val = load i1* @var
   %ret = sext i1 %val to i32
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
-; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm w[0-9]+, w[0-9]+, #0, #0}}
+; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfx w[0-9]+, w[0-9]+, #0, #1}}
 
   ret i32 %ret
 ; CHECK: ret
 }
 
 define i64 @test_sextloadi64() {
 ; CHECK-LABEL: test_sextloadi64
 
   %val = load i1* @var
   %ret = sext i1 %val to i64
 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
-; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm x[0-9]+, x[0-9]+, #0, #0}}
+; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1}}
 
   ret i64 %ret
 ; CHECK: ret
 }
 
 define i32 @test_zextloadi32() {
 ; CHECK-LABEL: test_zextloadi32
 

test/CodeGen/ARM64/aapcs.ll

; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
 
   %ext_short = zext i16 %short to i64
   store volatile i64 %ext_short, i64* @var64
 ; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
 
   %ext_int = zext i32 %int to i64
   store volatile i64 %ext_int, i64* @var64
-; CHECK: uxtw [[EXT:x[0-9]+]], w3
+; CHECK: ubfx [[EXT:x[0-9]+]], x3, #0, #32
 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
 
   ret void
 }
 
 declare void @variadic(i32 %a, ...)
 
   ; Under AAPCS variadic functions have the same calling convention as

test/CodeGen/ARM64/bitfield-extract.ll

 ; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
 ; RUN: llc < %s -march=arm64 | FileCheck %s
 %struct.X = type { i8, i8, [2 x i8] }
 %struct.Y = type { i32, i8 }
 %struct.Z = type { i8, i8, [2 x i8], i16 }
 %struct.A = type { i64, i8 }
 
 define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp {
 ; CHECK-LABEL: foo:
-; CHECK: ubfm
+; CHECK: ubfx
 ; CHECK-NOT: and
 ; CHECK: ret
 
   %tmp = bitcast %struct.X* %x to i32*
   %tmp1 = load i32* %tmp, align 4
   %b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1
   %bf.clear = lshr i32 %tmp1, 3
   %bf.clear.lobit = and i32 %bf.clear, 1
   %frombool = trunc i32 %bf.clear.lobit to i8
   store i8 %frombool, i8* %b, align 1
   ret void
 }
 
 define i32 @baz(i64 %cav1.coerce) nounwind {
 ; CHECK-LABEL: baz:
-; CHECK: sbfm  w0, w0, #0, #3
+; CHECK: sbfx  w0, w0, #0, #4
   %tmp = trunc i64 %cav1.coerce to i32
   %tmp1 = shl i32 %tmp, 28
   %bf.val.sext = ashr exact i32 %tmp1, 28
   ret i32 %bf.val.sext
 }
 
 define i32 @bar(i64 %cav1.coerce) nounwind {
 ; CHECK-LABEL: bar:
-; CHECK: sbfm  w0, w0, #4, #9
+; CHECK: sbfx  w0, w0, #4, #6
   %tmp = trunc i64 %cav1.coerce to i32
   %cav1.sroa.0.1.insert = shl i32 %tmp, 22
   %tmp1 = ashr i32 %cav1.sroa.0.1.insert, 26
   ret i32 %tmp1
 }
 
 define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind optsize ssp {
 ; CHECK-LABEL: fct1:
-; CHECK: ubfm
+; CHECK: ubfx
 ; CHECK-NOT: and
 ; CHECK: ret
 
   %tmp = bitcast %struct.Z* %x to i64*
   %tmp1 = load i64* %tmp, align 4
   %b = getelementptr inbounds %struct.A* %y, i64 0, i32 0
   %bf.clear = lshr i64 %tmp1, 3
   %bf.clear.lobit = and i64 %bf.clear, 1
   store i64 %bf.clear.lobit, i64* %b, align 8
   ret void
 }
 
 define i64 @fct2(i64 %cav1.coerce) nounwind {
 ; CHECK-LABEL: fct2:
-; CHECK: sbfm  x0, x0, #0, #35
+; CHECK: sbfx  x0, x0, #0, #36
   %tmp = shl i64 %cav1.coerce, 28
   %bf.val.sext = ashr exact i64 %tmp, 28
   ret i64 %bf.val.sext
 }
 
 define i64 @fct3(i64 %cav1.coerce) nounwind {
 ; CHECK-LABEL: fct3:
-; CHECK: sbfm  x0, x0, #4, #41
+; CHECK: sbfx  x0, x0, #4, #38
   %cav1.sroa.0.1.insert = shl i64 %cav1.coerce, 22
   %tmp1 = ashr i64 %cav1.sroa.0.1.insert, 26
   ret i64 %tmp1
 }
 
 define void @fct4(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct4:
; CHECK-NEXT: ret
   %shl = shl i64 %or, 2
   store i64 %shl, i64* %y, align 8
   ret void
 }
 
 define zeroext i1 @fct12bis(i32 %tmp2) unnamed_addr nounwind ssp align 2 {
 ; CHECK-LABEL: fct12bis:
 ; CHECK-NOT: and
-; CHECK: ubfm w0, w0, #11, #11
+; CHECK: ubfx w0, w0, #11, #1
   %and.i.i = and i32 %tmp2, 2048
   %tobool.i.i = icmp ne i32 %and.i.i, 0
   ret i1 %tobool.i.i
 }
 
 ; Check if we can still catch bfm instruction when we drop some high bits
 ; and some low bits
 define void @fct12(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct12:
 ; CHECK: ldr [[REG1:w[0-9]+]],
 ; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
 ; lsr is an alias of ubfm
-; CHECK-NEXT: ubfm [[REG2:w[0-9]+]], [[REG1]], #2, #29
+; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
   %0 = load i32* %y, align 8
   %and = and i32 %0, -8
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
   %or = or i32 %and, %and1
   %shl = shl i32 %or, 2
   %shr2 = lshr i32 %shl, 4
   store i32 %shr2, i32* %y, align 8
   ret void
 }
 
 ; Check if we can still catch bfm instruction when we drop some high bits
 ; and some low bits
 ; (i64 version)
 define void @fct13(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct13:
 ; CHECK: ldr [[REG1:x[0-9]+]],
 ; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
 ; lsr is an alias of ubfm
-; CHECK-NEXT: ubfm [[REG2:x[0-9]+]], [[REG1]], #2, #61
+; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60
 ; CHECK-NEXT: str [[REG2]],
 ; CHECK-NEXT: ret
   %0 = load i64* %y, align 8
   %and = and i64 %0, -8
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
   %or = or i64 %and, %and1
   %shl = shl i64 %or, 2

 ; CHECK: ldr [[REG1:w[0-9]+]],
 ; Create the constant
 ; CHECK: movz [[REGCST:w[0-9]+]], #26, lsl #16
 ; CHECK: movk [[REGCST]], #33120
 ; Do the masking
 ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
 ; CHECK-NEXT: bfm [[REG2]], w1, #16, #18
 ; lsr is an alias of ubfm
-; CHECK-NEXT: ubfm [[REG3:w[0-9]+]], [[REG2]], #2, #29
+; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
   %0 = load i32* %y, align 8
   %and = and i32 %0, 1737056
   %shr = lshr i32 %x, 16
   %and1 = and i32 %shr, 7
   %or = or i32 %and, %and1
   %shl = shl i32 %or, 2

 ; CHECK: ldr [[REG1:x[0-9]+]],
 ; Create the constant
 ; CHECK: movz w[[REGCST:[0-9]+]], #26, lsl #16
 ; CHECK: movk w[[REGCST]], #33120
 ; Do the masking
 ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
 ; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
 ; lsr is an alias of ubfm
-; CHECK-NEXT: ubfm [[REG3:x[0-9]+]], [[REG2]], #2, #61
+; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
   %0 = load i64* %y, align 8
   %and = and i64 %0, 1737056
   %shr = lshr i64 %x, 16
   %and1 = and i64 %shr, 7
   %or = or i64 %and, %and1
   %shl = shl i64 %or, 2
   %shr2 = lshr i64 %shl, 4
   store i64 %shr2, i64* %y, align 8
   ret void
 }
 
 define i64 @fct18(i32 %xor72) nounwind ssp {
 ; CHECK-LABEL: fct18:
-; CHECK: ubfm x0, x0, #9, #16
+; CHECK: ubfx x0, x0, #9, #8
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %result = and i64 %conv82, 255
   ret i64 %result
 }
 
 ; Using the access to the global array to keep the instruction and control flow.
 @first_ones = external global [65536 x i8]
if.then:                                          ; preds = %entry
   %arrayidx3 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift
   %0 = load i8* %arrayidx3, align 1
   %conv = zext i8 %0 to i32
   br label %return
 
 ; OPT-LABEL: if.end
 if.end:                                           ; preds = %entry
 ; OPT: lshr
-; CHECK: ubfm [[REG1:x[0-9]+]], [[REG2:x[0-9]+]], #32, #47
+; CHECK: ubfx [[REG1:x[0-9]+]], [[REG2:x[0-9]+]], #32, #16
   %x.sroa.3.0.extract.trunc = trunc i64 %x.sroa.3.0.extract.shift to i16
   %tobool6 = icmp eq i16 %x.sroa.3.0.extract.trunc, 0
 ; CHECK: cbz
   br i1 %tobool6, label %if.end13, label %if.then7
 
 ; OPT-LABEL: if.then7
 if.then7:                                         ; preds = %if.end
 ; OPT: lshr
 ; "and" should be combined to "ubfm" while "ubfm" should be removed by cse. 
 ; So neither of them should be in the assemble code. 
 ; CHECK-NOT: and
 ; CHECK-NOT: ubfm
   %idxprom10 = and i64 %x.sroa.3.0.extract.shift, 65535
   %arrayidx11 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom10
   %1 = load i8* %arrayidx11, align 1
   %conv12 = zext i8 %1 to i32
   %add = add nsw i32 %conv12, 16
   br label %return
 
 ; OPT-LABEL: if.end13
 if.end13:                                         ; preds = %if.end
 ; OPT: lshr
 ; OPT: trunc
-; CHECK: ubfm [[REG3:x[0-9]+]], [[REG4:x[0-9]+]], #16, #31
+; CHECK: ubfx [[REG3:x[0-9]+]], [[REG4:x[0-9]+]], #16, #16
   %tobool16 = icmp eq i16 %x.sroa.1.0.extract.trunc, 0
 ; CHECK: cbz
   br i1 %tobool16, label %return, label %if.then17
 
 ; OPT-LABEL: if.then17
 if.then17:                                        ; preds = %if.end13
 ; OPT: lshr
 ; "and" should be combined to "ubfm" while "ubfm" should be removed by cse. 

test/CodeGen/ARM64/fast-isel-conversion.ll

 ; CHECK: str x3, [sp]
 ; CHECK: ldrb w0, [sp, #15]
 ; CHECK: uxtb w0, w0
 ; CHECK: strh w0, [sp, #12]
 ; CHECK: ldrh w0, [sp, #12]
 ; CHECK: uxth w0, w0
 ; CHECK: str w0, [sp, #8]
 ; CHECK: ldr w0, [sp, #8]
-; CHECK: uxtw x3, w0
+; CHECK: ubfx x3, w0, #0, #32
 ; CHECK: str x3, [sp]
 ; CHECK: ldr x0, [sp], #16
 ; CHECK: ret
   %a.addr = alloca i8, align 1
   %b.addr = alloca i16, align 2
   %c.addr = alloca i32, align 4
   %d.addr = alloca i64, align 8
   store i8 %a, i8* %a.addr, align 1
; CHECK: sxtb x0, w0
   %conv = sext i8 %a to i64
   ret i64 %conv
 }
 
 ; Test sext i1 to i32
 define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
 entry:
 ; CHECK: sext_i1_i32
-; CHECK: sbfm w0, w0, #0, #0
+; CHECK: sbfx w0, w0, #0, #1
   %conv = sext i1 %a to i32
   ret i32 %conv
 }
 
 ; Test sext i1 to i16
 define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
 entry:
 ; CHECK: sext_i1_i16
-; CHECK: sbfm w0, w0, #0, #0
+; CHECK: sbfx w0, w0, #0, #1
   %conv = sext i1 %a to i16
   ret i16 %conv
 }
 
 ; Test sext i1 to i8
 define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
 entry:
 ; CHECK: sext_i1_i8
-; CHECK: sbfm w0, w0, #0, #0
+; CHECK: sbfx w0, w0, #0, #1
   %conv = sext i1 %a to i8
   ret i8 %conv
 }
 
 ; Test fpext
 define double @fpext_(float %a) nounwind ssp {
 entry:
 ; CHECK: fpext_
; CHECK: fcvtzu w0, d0
   %conv = fptoui double %a to i32
   ret i32 %conv
 }
 
 ; Test sitofp
 define float @sitofp_sw_i1(i1 %a) nounwind ssp {
 entry:
 ; CHECK: sitofp_sw_i1
-; CHECK: sbfm w0, w0, #0, #0
+; CHECK: sbfx w0, w0, #0, #1
 ; CHECK: scvtf s0, w0
   %conv = sitofp i1 %a to float
   ret float %conv
 }
 
 ; Test sitofp
 define float @sitofp_sw_i8(i8 %a) nounwind ssp {
 entry:

test/CodeGen/ARM64/fold-lsl.ll

 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
 ;
 ; <rdar://problem/14486451>
 
 %struct.a = type [256 x i16]
 %struct.b = type [256 x i32]
 %struct.c = type [256 x i64]
 
 define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind {
 ; CHECK-LABEL: load_halfword:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: ldrh w0, [x0, [[REG]], lsl #1]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
   %result = load i16* %arrayidx86, align 2
   ret i16 %result
 }
 
 define i32 @load_word(%struct.b* %ctx, i32 %xor72) nounwind {
 ; CHECK-LABEL: load_word:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: ldr w0, [x0, [[REG]], lsl #2]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
   %result = load i32* %arrayidx86, align 4
   ret i32 %result
 }
 
 define i64 @load_doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
 ; CHECK-LABEL: load_doubleword:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: ldr x0, [x0, [[REG]], lsl #3]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
   %result = load i64* %arrayidx86, align 8
   ret i64 %result
 }
 
 define void @store_halfword(%struct.a* %ctx, i32 %xor72, i16 %val) nounwind {
 ; CHECK-LABEL: store_halfword:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: strh w2, [x0, [[REG]], lsl #1]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
   store i16 %val, i16* %arrayidx86, align 8
   ret void
 }
 
 define void @store_word(%struct.b* %ctx, i32 %xor72, i32 %val) nounwind {
 ; CHECK-LABEL: store_word:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: str w2, [x0, [[REG]], lsl #2]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
   store i32 %val, i32* %arrayidx86, align 8
   ret void
 }
 
 define void @store_doubleword(%struct.c* %ctx, i32 %xor72, i64 %val) nounwind {
 ; CHECK-LABEL: store_doubleword:
-; CHECK: ubfm [[REG:x[0-9]+]], x1, #9, #16
+; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
 ; CHECK: str x2, [x0, [[REG]], lsl #3]
   %shr81 = lshr i32 %xor72, 9
   %conv82 = zext i32 %shr81 to i64
   %idxprom83 = and i64 %conv82, 255
   %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
   store i64 %val, i64* %arrayidx86, align 8
   ret void
 }

test/CodeGen/ARM64/shifted-sext.ll

 ; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
 ;
 ; <rdar://problem/13820218>
 
 define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #28, #7
+; CHECK: sbfiz w0, [[REG]], #4, #8
   %inc = add i8 %a, 1
   %conv1 = sext i8 %inc to i32
   %shl = shl nsw i32 %conv1, 4
   %conv2 = trunc i32 %shl to i16
   ret i16 %conv2
 }
 
 define signext i16 @extendedRightShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharToshortBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #4, #7
+; CHECK: sbfx w0, [[REG]], #4, #4
   %inc = add i8 %a, 1
   %conv1 = sext i8 %inc to i32
   %shr4 = lshr i32 %conv1, 4
   %conv2 = trunc i32 %shr4 to i16
   ret i16 %conv2
 }
 
 define signext i16 @extendedLeftShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharToshortBy8:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #24, #7
+; CHECK: sbfiz w0, [[REG]], #8, #8
   %inc = add i8 %a, 1
   %conv1 = sext i8 %inc to i32
   %shl = shl nsw i32 %conv1, 8
   %conv2 = trunc i32 %shl to i16
   ret i16 %conv2
 }
 
 define signext i16 @extendedRightShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharToshortBy8:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
 ; CHECK: sxtb [[REG]], [[REG]]
 ; CHECK: asr w0, [[REG]], #8
   %inc = add i8 %a, 1
   %conv1 = sext i8 %inc to i32
   %shr4 = lshr i32 %conv1, 8
   %conv2 = trunc i32 %shr4 to i16
   ret i16 %conv2
 }
 
 define i32 @extendedLeftShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharTointBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #28, #7
+; CHECK: sbfiz w0, [[REG]], #4, #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i32
   %shl = shl nsw i32 %conv, 4
   ret i32 %shl
 }
 
 define i32 @extendedRightShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharTointBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #4, #7
+; CHECK: sbfx w0, [[REG]], #4, #4
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i32
   %shr = ashr i32 %conv, 4
   ret i32 %shr
 }
 
 define i32 @extendedLeftShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharTointBy8:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #24, #7
+; CHECK: sbfiz w0, [[REG]], #8, #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i32
   %shl = shl nsw i32 %conv, 8
   ret i32 %shl
 }
 
 define i32 @extendedRightShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharTointBy8:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
 ; CHECK: sxtb [[REG]], [[REG]]
 ; CHECK: asr w0, [[REG]], #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i32
   %shr = ashr i32 %conv, 8
   ret i32 %shr
 }
 
 define i64 @extendedLeftShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #60, #7
+; CHECK: sbfiz x0, x[[REG]], #4, #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i64
   %shl = shl nsw i64 %conv, 4
   ret i64 %shl
 }
 
 define i64 @extendedRightShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #4, #7
+; CHECK: sbfx x0, x[[REG]], #4, #4
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i64
   %shr = ashr i64 %conv, 4
   ret i64 %shr
 }
 
 define i64 @extendedLeftShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftcharToint64By8:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #56, #7
+; CHECK: sbfiz x0, x[[REG]], #8, #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i64
   %shl = shl nsw i64 %conv, 8
   ret i64 %shl
 }
 
 define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftcharToint64By8:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
 ; CHECK: sxtb x[[REG]], w[[REG]]
 ; CHECK: asr x0, x[[REG]], #8
   %inc = add i8 %a, 1
   %conv = sext i8 %inc to i64
   %shr = ashr i64 %conv, 8
   ret i64 %shr
 }
 
 define i32 @extendedLeftShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftshortTointBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #28, #15
+; CHECK: sbfiz w0, [[REG]], #4, #16
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i32
   %shl = shl nsw i32 %conv, 4
   ret i32 %shl
 }
 
 define i32 @extendedRightShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftshortTointBy4:
 ; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfm w0, [[REG]], #4, #15
+; CHECK: sbfx w0, [[REG]], #4, #12
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i32
   %shr = ashr i32 %conv, 4
   ret i32 %shr
 }
 
 define i32 @extendedLeftShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
 entry:
; CHECK: asr w0, [[REG]], #16
   %shr = ashr i32 %conv, 16
   ret i32 %shr
 }
 
 define i64 @extendedLeftShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftshortToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #60, #15
+; CHECK: sbfiz x0, x[[REG]], #4, #16
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i64
   %shl = shl nsw i64 %conv, 4
   ret i64 %shl
 }
 
 define i64 @extendedRightShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftshortToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #4, #15
+; CHECK: sbfx x0, x[[REG]], #4, #12
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i64
   %shr = ashr i64 %conv, 4
   ret i64 %shr
 }
 
 define i64 @extendedLeftShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftshortToint64By16:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #48, #15
+; CHECK: sbfiz x0, x[[REG]], #16, #16
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i64
   %shl = shl nsw i64 %conv, 16
   ret i64 %shl
 }
 
 define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftshortToint64By16:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
 ; CHECK: sxth x[[REG]], w[[REG]]
 ; CHECK: asr x0, x[[REG]], #16
   %inc = add i16 %a, 1
   %conv = sext i16 %inc to i64
   %shr = ashr i64 %conv, 16
   ret i64 %shr
 }
 
 define i64 @extendedLeftShiftintToint64By4(i32 %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedLeftShiftintToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #60, #31
+; CHECK: sbfiz x0, x[[REG]], #4, #32
   %inc = add nsw i32 %a, 1
   %conv = sext i32 %inc to i64
   %shl = shl nsw i64 %conv, 4
   ret i64 %shl
 }
 
 define i64 @extendedRightShiftintToint64By4(i32 %a) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: extendedRightShiftintToint64By4:
 ; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfm x0, x[[REG]], #4, #31
+; CHECK: sbfx x0, x[[REG]], #4, #28
   %inc = add nsw i32 %a, 1
   %conv = sext i32 %inc to i64
   %shr = ashr i64 %conv, 4
   ret i64 %shr
 }
 
 define i64 @extendedLeftShiftintToint64By32(i32 %a) nounwind readnone ssp {
 entry:

test/MC/ARM64/aliases.s

;-----------------------------------------------------------------------------
   sbfiz x0, x0, #1, #4
   sbfx  w0, w0, #2, #3
   sbfx  x0, x0, #2, #3
   ubfiz w0, w0, #1, #4
   ubfiz x0, x0, #1, #4
   ubfx  w0, w0, #2, #3
   ubfx  x0, x0, #2, #3
 
-; CHECK: bfm  w0, w0, #31, #3
-; CHECK: bfm  x0, x0, #63, #3
-; CHECK: bfm  w0, w0, #0, #1
-; CHECK: bfm  x0, x0, #0, #1
-; CHECK: bfm  w0, w0, #2, #4
-; CHECK: bfm  x0, x0, #2, #4
-; CHECK: sbfm w0, w0, #31, #3
-; CHECK: sbfm x0, x0, #63, #3
-; CHECK: sbfm w0, w0, #2, #4
-; CHECK: sbfm x0, x0, #2, #4
-; CHECK: ubfm w0, w0, #31, #3
-; CHECK: ubfm x0, x0, #63, #3
-; CHECK: ubfm w0, w0, #2, #4
-; CHECK: ubfm x0, x0, #2, #4
+; CHECK: bfm   w0, w0, #31, #3
+; CHECK: bfm   x0, x0, #63, #3
+; CHECK: bfm   w0, w0, #0, #1
+; CHECK: bfm   x0, x0, #0, #1
+; CHECK: bfm   w0, w0, #2, #4
+; CHECK: bfm   x0, x0, #2, #4
+; CHECK: sbfiz w0, w0, #1, #4
+; CHECK: sbfiz x0, x0, #1, #4
+; CHECK: sbfx  w0, w0, #2, #3
+; CHECK: sbfx  x0, x0, #2, #3
+; CHECK: ubfiz w0, w0, #1, #4
+; CHECK: ubfiz x0, x0, #1, #4
+; CHECK: ubfx  w0, w0, #2, #3
+; CHECK: ubfx  x0, x0, #2, #3
 
 ;-----------------------------------------------------------------------------
 ; Shift (immediate) aliases
 ;-----------------------------------------------------------------------------
 
 ; CHECK: asr w1, w3, #13
 ; CHECK: asr x1, x3, #13
 ; CHECK: lsl w0, w0, #1
; CHECK: uxth w1, w2
   sxtw  x1, w2
   uxtb  x1, w2
   uxth  x1, w2
   uxtw  x1, w2
 
 ; CHECK: sxtb x1, w2
 ; CHECK: sxth x1, w2
 ; CHECK: sxtw x1, w2
-; CHECK: uxtb x1, w2
-; CHECK: uxth x1, w2
-; CHECK: uxtw x1, w2
+; CHECK: ubfx x1, x2, #0, #8
+; CHECK: ubfx x1, x2, #0, #16
+; CHECK: ubfx x1, x2, #0, #32
 
 ;-----------------------------------------------------------------------------
 ; Negate with carry
 ;-----------------------------------------------------------------------------
 
   ngc   w1, w2
   ngc   x1, x2
   ngcs  w1, w2

test/MC/ARM64/bitfield-encoding.s

;==---------------------------------------------------------------------------==
   ubfm x1, x2, #1, #15
   sbfiz wzr, w0, #31, #1
   sbfiz xzr, x0, #31, #1
   ubfiz wzr, w0, #31, #1
   ubfiz xzr, x0, #31, #1
 
 ; CHECK: bfm  w1, w2, #1, #15        ; encoding: [0x41,0x3c,0x01,0x33]
 ; CHECK: bfm  x1, x2, #1, #15        ; encoding: [0x41,0x3c,0x41,0xb3]
-; CHECK: sbfm w1, w2, #1, #15        ; encoding: [0x41,0x3c,0x01,0x13]
-; CHECK: sbfm x1, x2, #1, #15        ; encoding: [0x41,0x3c,0x41,0x93]
-; CHECK: ubfm w1, w2, #1, #15        ; encoding: [0x41,0x3c,0x01,0x53]
-; CHECK: ubfm x1, x2, #1, #15        ; encoding: [0x41,0x3c,0x41,0xd3]
-; CHECK: sbfm wzr, w0, #1, #0        ; encoding: [0x1f,0x00,0x01,0x13]
-; CHECK: sbfm xzr, x0, #33, #0       ; encoding: [0x1f,0x00,0x61,0x93]
+; CHECK: sbfx w1, w2, #1, #15        ; encoding: [0x41,0x3c,0x01,0x13]
+; CHECK: sbfx x1, x2, #1, #15        ; encoding: [0x41,0x3c,0x41,0x93]
+; CHECK: ubfx w1, w2, #1, #15        ; encoding: [0x41,0x3c,0x01,0x53]
+; CHECK: ubfx x1, x2, #1, #15        ; encoding: [0x41,0x3c,0x41,0xd3]
+; CHECK: sbfiz wzr, w0, #31, #1      ; encoding: [0x1f,0x00,0x01,0x13]
+; CHECK: sbfiz xzr, x0, #31, #1      ; encoding: [0x1f,0x00,0x61,0x93]
 ; CHECK: lsl  wzr, w0, #31           ; encoding: [0x1f,0x00,0x01,0x53]
-; CHECK: ubfm xzr, x0, #33, #0       ; encoding: [0x1f,0x00,0x61,0xd3]
+; CHECK: ubfiz xzr, x0, #31, #1      ; encoding: [0x1f,0x00,0x61,0xd3]
 
 ;==---------------------------------------------------------------------------==
 ; 5.4.5 Extract (immediate)
 ;==---------------------------------------------------------------------------==
 
   extr w1, w2, w3, #15
   extr x2, x3, x4, #1
 
 ; CHECK: extr w1, w2, w3, #15        ; encoding: [0x41,0x3c,0x83,0x13]
 ; CHECK: extr x2, x3, x4, #1         ; encoding: [0x62,0x04,0xc4,0x93]

test/MC/Disassembler/ARM64/bitfield.txt

 # RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
 
 #==---------------------------------------------------------------------------==
 # 5.4.4 Bitfield Operations
 #==---------------------------------------------------------------------------==
 
 0x41 0x3c 0x01 0x33
 0x41 0x3c 0x41 0xb3
 0x41 0x3c 0x01 0x13
 0x41 0x3c 0x41 0x93
 0x41 0x3c 0x01 0x53
 0x41 0x3c 0x41 0xd3
 
 # CHECK: bfm  w1, w2, #1, #15
 # CHECK: bfm  x1, x2, #1, #15
-# CHECK: sbfm w1, w2, #1, #15
-# CHECK: sbfm x1, x2, #1, #15
-# CHECK: ubfm w1, w2, #1, #15
-# CHECK: ubfm x1, x2, #1, #15
+# CHECK: sbfx w1, w2, #1, #15
+# CHECK: sbfx x1, x2, #1, #15
+# CHECK: ubfx w1, w2, #1, #15
+# CHECK: ubfx x1, x2, #1, #15
 
 #==---------------------------------------------------------------------------==
 # 5.4.5 Extract (immediate)
 #==---------------------------------------------------------------------------==
 
 0x41 0x3c 0x83 0x13
 0x62 0x04 0xc4 0x93
 
 # CHECK: extr w1, w2, w3, #15
 # CHECK: extr x2, x3, x4, #1