[PowerPC] avoid redundant analysis while lowering an immediate; NFC

[inouehrs]

Summary

This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate.
If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0).
This patch should not change functionality.

[nemanjai]

This makes perfect sense. LGTM.

[echristo]

Perhaps an explanatory comment? :)

-eric

[inouehrs]

Committed with explanatory comments.

[echristo]

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

710

Can uou change this routine name? (and the one below) They're pretty useless when reading to know what they mean.

[inouehrs]

@echristo In addition to getInt64Count, I feel that getInt64 is also somewhat confusing since we have getI64Imm for other purpose.
How about selectI64Imm and selectI64ImmInstrCount instead of getInt64 and getInt64Count?
Alternative names are getInt64MaterializationInstr and getInt64MaterializationInstrCount (suggested by @nemanjai)
Do you have any suggestion?

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static unsigned getInt64CountDirect(int64_t Imm) {
 
   return Result;
 }
 
 static uint64_t Rot64(uint64_t Imm, unsigned R) {
   return (Imm << R) | (Imm >> (64 - R));
 }
 
 static unsigned getInt64Count(int64_t Imm) {
   unsigned Count = getInt64CountDirect(Imm);
-  if (Count == 1)
+
+  // If the instruction count is 1 or 2, we do not need further analysis
+  // since rotate + load constant requires at least 2 instructions.
+  if (Count <= 2)
     return Count;
 
   for (unsigned r = 1; r < 63; ++r) {
     uint64_t RImm = Rot64(Imm, r);
     unsigned RCount = getInt64CountDirect(RImm) + 1;
     Count = std::min(Count, RCount);
 
     // See comments in getInt64 for an explanation of the logic below.
Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
                                     SDValue(Result, 0), getI32Imm(Lo));
   }
 
   return Result;
 }
 
 static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) {
   unsigned Count = getInt64CountDirect(Imm);
-  if (Count == 1)
+
+  // If the instruction count is 1 or 2, we do not need further analysis
+  // since rotate + load constant requires at least 2 instructions.
+  if (Count <= 2)
     return getInt64Direct(CurDAG, dl, Imm);
 
   unsigned RMin = 0;
 
   int64_t MatImm;
   unsigned MaskEnd;
 
   for (unsigned r = 1; r < 63; ++r) {