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Create TD nodes for ADDCARRY and SUBCARRY opcodes
AbandonedPublic

Authored by rampitec on Jun 20 2017, 3:11 PM.

Details

Reviewers
arsenm
deadalnix
Summary

These are nodes for newly added ISD opcodes ADDCARRY and SUBCARRY.
They are going to be first used in D34300 instead of those defined in target.

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Jun 20 2017, 3:11 PM
arsenm added inline comments.Jun 20 2017, 4:47 PM
include/llvm/Target/TargetSelectionDAG.td
161

i1 is wrong here since it will presumably be legalized to the target's boolean contents at some point, which won't necessarily be i1.

161

They probably just need to be constrained to int and the same, there's no way to constrain to the TLI hook reported types

rampitec added inline comments.Jun 20 2017, 5:12 PM
include/llvm/Target/TargetSelectionDAG.td
161

Isn't bool always i1 regardless of its target representation?

arsenm added inline comments.Jun 20 2017, 5:46 PM
include/llvm/Target/TargetSelectionDAG.td
161

No, this will be legalized to the target's boolean type. i1 isn't required to be legal for the target. i1 is only used before legalization

rampitec added inline comments.Jun 21 2017, 2:21 PM
include/llvm/Target/TargetSelectionDAG.td
161

OK, if I do not specify exact VT for the carry, then this pattern does not work any longer:

def : Pat<
    (addcarry i32:$src0, i32:$src1, i1:$src2),
    (V_ADDC_U32_e64 $src0, $src1, $src2)
>;

Since I cannot get that pattern to work there is no use of the new nodes, so I'm about to abandon the proposal.

rampitec abandoned this revision.Jun 21 2017, 2:30 PM