Create TD nodes for ADDCARRY and SUBCARRY opcodes

[rampitec]

Summary

These are nodes for newly added ISD opcodes ADDCARRY and SUBCARRY.
They are going to be first used in D34300 instead of those defined in target.

[arsenm]

include/llvm/Target/TargetSelectionDAG.td

161

i1 is wrong here since it will presumably be legalized to the target's boolean contents at some point, which won't necessarily be i1.

161

They probably just need to be constrained to int and the same, there's no way to constrain to the TLI hook reported types

[rampitec]

include/llvm/Target/TargetSelectionDAG.td

161

Isn't bool always i1 regardless of its target representation?

[arsenm]

include/llvm/Target/TargetSelectionDAG.td

161

No, this will be legalized to the target's boolean type. i1 isn't required to be legal for the target. i1 is only used before legalization

[rampitec]

include/llvm/Target/TargetSelectionDAG.td

161

OK, if I do not specify exact VT for the carry, then this pattern does not work any longer:

def : Pat<
    (addcarry i32:$src0, i32:$src1, i1:$src2),
    (V_ADDC_U32_e64 $src0, $src1, $src2)
>;

Since I cannot get that pattern to work there is no use of the new nodes, so I'm about to abandon the proposal.

include/llvm/Target/TargetSelectionDAG.td

def SDTFPExtendOp  : SDTypeProfile<1, 1, [  // fextend
   SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>
 ]>;
 def SDTIntToFPOp : SDTypeProfile<1, 1, [    // [su]int_to_fp
   SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>
 ]>;
 def SDTFPToIntOp : SDTypeProfile<1, 1, [    // fp_to_[su]int
   SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>
 ]>;
+
+def SDTCarryOp : SDTypeProfile<2, 3, [      // addcarry, subcarry
+  SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i1>, SDTCisVT<4, i1>
+]>;
+
 def SDTExtInreg : SDTypeProfile<1, 2, [     // sext_inreg
   SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
   SDTCisVTSmallerThanOp<2, 1>
 ]>;
 def SDTExtInvec : SDTypeProfile<1, 1, [     // sext_invec
   SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>,
   SDTCisOpSmallerThanOp<1, 0>, SDTCisSameSizeAs<0,1>
 ]>;

 def and        : SDNode<"ISD::AND"       , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def or         : SDNode<"ISD::OR"        , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def xor        : SDNode<"ISD::XOR"       , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def addc       : SDNode<"ISD::ADDC"      , SDTIntBinOp,
                         [SDNPCommutative, SDNPOutGlue]>;
+def addcarry   : SDNode<"ISD::ADDCARRY"  , SDTCarryOp>;
 def adde       : SDNode<"ISD::ADDE"      , SDTIntBinOp,
                         [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
 def subc       : SDNode<"ISD::SUBC"      , SDTIntBinOp,
                         [SDNPOutGlue]>;
+def subcarry   : SDNode<"ISD::SUBCARRY"  , SDTCarryOp>;
 def sube       : SDNode<"ISD::SUBE"      , SDTIntBinOp,
                         [SDNPOutGlue, SDNPInGlue]>;
 def smin       : SDNode<"ISD::SMIN"      , SDTIntBinOp,
                                   [SDNPCommutative, SDNPAssociative]>;
 def smax       : SDNode<"ISD::SMAX"      , SDTIntBinOp,
                                   [SDNPCommutative, SDNPAssociative]>;
 def umin       : SDNode<"ISD::UMIN"      , SDTIntBinOp,
                                   [SDNPCommutative, SDNPAssociative]>;