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Differential D33407

PR28129 Avoid producing vxorps to clear the fake inputs.
AbandonedPublic

Authored by dtemirbulatov on May 22 2017, 5:15 AM.

Details

Reviewers
RKSimon
spatel
craig.topper
Summary

Here we have removed vxorps operation out of AVX1_SETALLONES pattern and we let ExecDeps to clear the inputs instead.

Diff Detail

Event Timeline

dtemirbulatov created this revision.May 22 2017, 5:15 AM
dtemirbulatov abandoned this revision.May 22 2017, 6:30 PM

canceling because x86 is not currently set up to look at breaking a dependency for anything but the 2nd operand.

Revision Contents

PathSize
lib/
Target/
X86/
8 lines
10 lines
test/
CodeGen/
X86/
52 lines
2 lines
8 lines
2 lines
8 lines
12 lines
2 lines

Diff 99744

lib/Target/X86/X86InstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,110 Lines • ▼ Show 20 Linesunsigned X86InstrInfo::getPartialRegUpdateClearance(
// If any instructions in the clearance range are reading Reg, insert a // If any instructions in the clearance range are reading Reg, insert a
// dependency breaking instruction, which is inexpensive and is likely to // dependency breaking instruction, which is inexpensive and is likely to
// be hidden in other instruction's cycles. // be hidden in other instruction's cycles.
return PartialRegUpdateClearance; return PartialRegUpdateClearance;
} }
// Return true for any instruction the copies the high bits of the first source // Return true for any instruction the copies the high bits of the first source
// operand into the unused high bits of the destination operand. // operand into the unused high bits of the destination operand.
static bool hasUndefRegUpdate(unsigned Opcode) { static bool hasUndefRegUpdate(const MachineInstr &MI) {
switch (Opcode) { switch (MI.getOpcode()) {
case X86::VCVTSI2SSrr: case X86::VCVTSI2SSrr:
case X86::VCVTSI2SSrm: case X86::VCVTSI2SSrm:
case X86::Int_VCVTSI2SSrr: case X86::Int_VCVTSI2SSrr:
case X86::Int_VCVTSI2SSrm: case X86::Int_VCVTSI2SSrm:
case X86::VCVTSI2SS64rr: case X86::VCVTSI2SS64rr:
case X86::VCVTSI2SS64rm: case X86::VCVTSI2SS64rm:
case X86::Int_VCVTSI2SS64rr: case X86::Int_VCVTSI2SS64rr:
case X86::Int_VCVTSI2SS64rm: case X86::Int_VCVTSI2SS64rm:
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesstatic bool hasUndefRegUpdate(const MachineInstr &MI) {
case X86::VSQRTSSZm: case X86::VSQRTSSZm:
case X86::VSQRTSSZm_Int: case X86::VSQRTSSZm_Int:
case X86::VSQRTSDZr: case X86::VSQRTSDZr:
case X86::VSQRTSDZr_Int: case X86::VSQRTSDZr_Int:
case X86::VSQRTSDZrb_Int: case X86::VSQRTSDZrb_Int:
case X86::VSQRTSDZm: case X86::VSQRTSDZm:
case X86::VSQRTSDZm_Int: case X86::VSQRTSDZm_Int:
return true; return true;
case X86::VCMPPSYrri:
return (MI.getOperand(3).getImm() == 0xf);
} }
return false; return false;
} }
/// Inform the ExecutionDepsFix pass how many idle instructions we would like /// Inform the ExecutionDepsFix pass how many idle instructions we would like
/// before certain undef register reads. /// before certain undef register reads.
/// ///
/// This catches the VCVTSI2SD family of instructions: /// This catches the VCVTSI2SD family of instructions:
/// ///
/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
/// ///
/// We should to be careful *not* to catch VXOR idioms which are presumably /// We should to be careful *not* to catch VXOR idioms which are presumably
/// handled specially in the pipeline: /// handled specially in the pipeline:
/// ///
/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
/// ///
/// Like getPartialRegUpdateClearance, this makes a strong assumption that the /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
/// high bits that are passed-through are not live. /// high bits that are passed-through are not live.
unsigned unsigned
X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
if (!hasUndefRegUpdate(MI.getOpcode())) if (!hasUndefRegUpdate(MI))
return 0; return 0;
// Set the OpNum parameter to the first source operand. // Set the OpNum parameter to the first source operand.
OpNum = 1; OpNum = 1;
const MachineOperand &MO = MI.getOperand(OpNum); const MachineOperand &MO = MI.getOperand(OpNum);
if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
return UndefRegClearance; return UndefRegClearance;
▲ Show 20 Lines • Show All 2,267 Lines • Show Last 20 Lines

lib/Target/X86/X86InstrSSE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
} }
// We set canFoldAsLoad because this can be converted to a constant-pool // We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-ones value if folding it would be beneficial. // load of an all-ones value if folding it would be beneficial.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isPseudo = 1, SchedRW = [WriteZero] in { isPseudo = 1, SchedRW = [WriteZero] in {
def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "", def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v4i32 immAllOnesV))]>; [(set VR128:$dst, (v4i32 immAllOnesV))]>;
let Predicates = [HasAVX1Only, OptForMinSize] in { let Predicates = [HasAVX1Only] in
def AVX1_SETALLONES: I<0, Pseudo, (outs VR256:$dst), (ins), "", def AVX1_SETALLONES: I<0, Pseudo, (outs VR256:$dst), (ins), "",
[(set VR256:$dst, (v8i32 immAllOnesV))]>; [(set VR256:$dst, (v8i32 immAllOnesV))]>;
}
let Predicates = [HasAVX2] in let Predicates = [HasAVX2] in
def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "", def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
[(set VR256:$dst, (v8i32 immAllOnesV))]>; [(set VR256:$dst, (v8i32 immAllOnesV))]>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SSE 1 & 2 - Move FP Scalar Instructions // SSE 1 & 2 - Move FP Scalar Instructions
// //
▲ Show 20 Lines • Show All 7,253 Lines • ▼ Show 20 Linesdef VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
[]>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L; []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
let mayLoad = 1 in let mayLoad = 1 in
def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst), def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f128mem:$src2, u8imm:$src3), (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L; []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
} }
// To create a 256-bit all ones value, we should produce VCMPTRUEPS
// with YMM register containing zero.
// FIXME: Avoid producing vxorps to clear the fake inputs.
let Predicates = [HasAVX1Only] in {
def : Pat<(v8i32 immAllOnesV), (VCMPPSYrri (AVX_SET0), (AVX_SET0), 0xf)>;
}
multiclass vinsert_lowering<string InstrStr, ValueType From, ValueType To, multiclass vinsert_lowering<string InstrStr, ValueType From, ValueType To,
PatFrag memop_frag> { PatFrag memop_frag> {
def : Pat<(vinsert128_insert:$ins (To VR256:$src1), (From VR128:$src2), def : Pat<(vinsert128_insert:$ins (To VR256:$src1), (From VR128:$src2),
(iPTR imm)), (iPTR imm)),
(!cast<Instruction>(InstrStr#rr) VR256:$src1, VR128:$src2, (!cast<Instruction>(InstrStr#rr) VR256:$src1, VR128:$src2,
(INSERT_get_vinsert128_imm VR256:$ins))>; (INSERT_get_vinsert128_imm VR256:$ins))>;
def : Pat<(vinsert128_insert:$ins (To VR256:$src1), def : Pat<(vinsert128_insert:$ins (To VR256:$src1),
(From (bitconvert (memop_frag addr:$src2))), (From (bitconvert (memop_frag addr:$src2))),
▲ Show 20 Lines • Show All 921 Lines • Show Last 20 Lines

test/CodeGen/X86/all-ones-vector.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; X32-SSE-LABEL: allones_v32i8: ; X32-SSE-LABEL: allones_v32i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v32i8: ; X32-AVX1-LABEL: allones_v32i8:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v32i8: ; X32-AVX256-LABEL: allones_v32i8:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v32i8: ; X64-SSE-LABEL: allones_v32i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v32i8: ; X64-AVX1-LABEL: allones_v32i8:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v32i8: ; X64-AVX256-LABEL: allones_v32i8:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ret <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
} }
define <16 x i16> @allones_v16i16() nounwind { define <16 x i16> @allones_v16i16() nounwind {
; X32-SSE-LABEL: allones_v16i16: ; X32-SSE-LABEL: allones_v16i16:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16i16: ; X32-AVX1-LABEL: allones_v16i16:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v16i16: ; X32-AVX256-LABEL: allones_v16i16:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v16i16: ; X64-SSE-LABEL: allones_v16i16:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16i16: ; X64-AVX1-LABEL: allones_v16i16:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v16i16: ; X64-AVX256-LABEL: allones_v16i16:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
} }
define <8 x i32> @allones_v8i32() nounwind { define <8 x i32> @allones_v8i32() nounwind {
; X32-SSE-LABEL: allones_v8i32: ; X32-SSE-LABEL: allones_v8i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8i32: ; X32-AVX1-LABEL: allones_v8i32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8i32: ; X32-AVX256-LABEL: allones_v8i32:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8i32: ; X64-SSE-LABEL: allones_v8i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8i32: ; X64-AVX1-LABEL: allones_v8i32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8i32: ; X64-AVX256-LABEL: allones_v8i32:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
} }
define <4 x i64> @allones_v4i64() nounwind { define <4 x i64> @allones_v4i64() nounwind {
; X32-SSE-LABEL: allones_v4i64: ; X32-SSE-LABEL: allones_v4i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4i64: ; X32-AVX1-LABEL: allones_v4i64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4i64: ; X32-AVX256-LABEL: allones_v4i64:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4i64: ; X64-SSE-LABEL: allones_v4i64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4i64: ; X64-AVX1-LABEL: allones_v4i64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4i64: ; X64-AVX256-LABEL: allones_v4i64:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>
} }
define <4 x double> @allones_v4f64() nounwind { define <4 x double> @allones_v4f64() nounwind {
; X32-SSE-LABEL: allones_v4f64: ; X32-SSE-LABEL: allones_v4f64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4f64: ; X32-AVX1-LABEL: allones_v4f64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4f64: ; X32-AVX256-LABEL: allones_v4f64:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4f64: ; X64-SSE-LABEL: allones_v4f64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4f64: ; X64-AVX1-LABEL: allones_v4f64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4f64: ; X64-AVX256-LABEL: allones_v4f64:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff>
} }
define <4 x double> @allones_v4f64_optsize() nounwind optsize { define <4 x double> @allones_v4f64_optsize() nounwind optsize {
; X32-SSE-LABEL: allones_v4f64_optsize: ; X32-SSE-LABEL: allones_v4f64_optsize:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v4f64_optsize: ; X32-AVX1-LABEL: allones_v4f64_optsize:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v4f64_optsize: ; X32-AVX256-LABEL: allones_v4f64_optsize:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v4f64_optsize: ; X64-SSE-LABEL: allones_v4f64_optsize:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v4f64_optsize: ; X64-AVX1-LABEL: allones_v4f64_optsize:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v4f64_optsize: ; X64-AVX256-LABEL: allones_v4f64_optsize:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff>
} }
define <8 x float> @allones_v8f32() nounwind { define <8 x float> @allones_v8f32() nounwind {
; X32-SSE-LABEL: allones_v8f32: ; X32-SSE-LABEL: allones_v8f32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f32: ; X32-AVX1-LABEL: allones_v8f32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8f32: ; X32-AVX256-LABEL: allones_v8f32:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8f32: ; X64-SSE-LABEL: allones_v8f32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f32: ; X64-AVX1-LABEL: allones_v8f32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8f32: ; X64-AVX256-LABEL: allones_v8f32:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }
define <8 x float> @allones_v8f32_optsize() nounwind optsize { define <8 x float> @allones_v8f32_optsize() nounwind optsize {
; X32-SSE-LABEL: allones_v8f32_optsize: ; X32-SSE-LABEL: allones_v8f32_optsize:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f32_optsize: ; X32-AVX1-LABEL: allones_v8f32_optsize:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX256-LABEL: allones_v8f32_optsize: ; X32-AVX256-LABEL: allones_v8f32_optsize:
; X32-AVX256: # BB#0: ; X32-AVX256: # BB#0:
; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX256-NEXT: retl ; X32-AVX256-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8f32_optsize: ; X64-SSE-LABEL: allones_v8f32_optsize:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f32_optsize: ; X64-AVX1-LABEL: allones_v8f32_optsize:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX256-LABEL: allones_v8f32_optsize: ; X64-AVX256-LABEL: allones_v8f32_optsize:
; X64-AVX256: # BB#0: ; X64-AVX256: # BB#0:
; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX256-NEXT: retq ; X64-AVX256-NEXT: retq
ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }
define <64 x i8> @allones_v64i8() nounwind { define <64 x i8> @allones_v64i8() nounwind {
; X32-SSE-LABEL: allones_v64i8: ; X32-SSE-LABEL: allones_v64i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v64i8: ; X32-AVX1-LABEL: allones_v64i8:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v64i8: ; X32-AVX2-LABEL: allones_v64i8:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
Show All 13 Lines
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v64i8: ; X64-AVX1-LABEL: allones_v64i8:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v64i8: ; X64-AVX2-LABEL: allones_v64i8:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
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; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v32i16: ; X32-AVX1-LABEL: allones_v32i16:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v32i16: ; X32-AVX2-LABEL: allones_v32i16:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
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; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v32i16: ; X64-AVX1-LABEL: allones_v32i16:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v32i16: ; X64-AVX2-LABEL: allones_v32i16:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
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; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16i32: ; X32-AVX1-LABEL: allones_v16i32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v16i32: ; X32-AVX2-LABEL: allones_v16i32:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: allones_v16i32: ; X32-AVX512-LABEL: allones_v16i32:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v16i32: ; X64-SSE-LABEL: allones_v16i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16i32: ; X64-AVX1-LABEL: allones_v16i32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v16i32: ; X64-AVX2-LABEL: allones_v16i32:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
Show All 10 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8i64: ; X32-AVX1-LABEL: allones_v8i64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v8i64: ; X32-AVX2-LABEL: allones_v8i64:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: allones_v8i64: ; X32-AVX512-LABEL: allones_v8i64:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8i64: ; X64-SSE-LABEL: allones_v8i64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8i64: ; X64-AVX1-LABEL: allones_v8i64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v8i64: ; X64-AVX2-LABEL: allones_v8i64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
Show All 10 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v8f64: ; X32-AVX1-LABEL: allones_v8f64:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v8f64: ; X32-AVX2-LABEL: allones_v8f64:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: allones_v8f64: ; X32-AVX512-LABEL: allones_v8f64:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v8f64: ; X64-SSE-LABEL: allones_v8f64:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v8f64: ; X64-AVX1-LABEL: allones_v8f64:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v8f64: ; X64-AVX2-LABEL: allones_v8f64:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
Show All 10 Lines
; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX1-LABEL: allones_v16f32: ; X32-AVX1-LABEL: allones_v16f32:
; X32-AVX1: # BB#0: ; X32-AVX1: # BB#0:
; X32-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X32-AVX1-NEXT: retl ; X32-AVX1-NEXT: retl
; ;
; X32-AVX2-LABEL: allones_v16f32: ; X32-AVX2-LABEL: allones_v16f32:
; X32-AVX2: # BB#0: ; X32-AVX2: # BB#0:
; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X32-AVX2-NEXT: retl ; X32-AVX2-NEXT: retl
; ;
; X32-AVX512-LABEL: allones_v16f32: ; X32-AVX512-LABEL: allones_v16f32:
; X32-AVX512: # BB#0: ; X32-AVX512: # BB#0:
; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X32-AVX512-NEXT: retl ; X32-AVX512-NEXT: retl
; ;
; X64-SSE-LABEL: allones_v16f32: ; X64-SSE-LABEL: allones_v16f32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0
; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1
; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2 ; X64-SSE-NEXT: pcmpeqd %xmm2, %xmm2
; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX1-LABEL: allones_v16f32: ; X64-AVX1-LABEL: allones_v16f32:
; X64-AVX1: # BB#0: ; X64-AVX1: # BB#0:
; X64-AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X64-AVX2-LABEL: allones_v16f32: ; X64-AVX2-LABEL: allones_v16f32:
; X64-AVX2: # BB#0: ; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X64-AVX512-LABEL: allones_v16f32: ; X64-AVX512-LABEL: allones_v16f32:
; X64-AVX512: # BB#0: ; X64-AVX512: # BB#0:
; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
; X64-AVX512-NEXT: retq ; X64-AVX512-NEXT: retq
ret <16 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> ret <16 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
} }

test/CodeGen/X86/avx-basic.ll

Show All 28 Lines; CHECK-NEXT: retq
store <8 x float> zeroinitializer, <8 x float>* @x, align 32 store <8 x float> zeroinitializer, <8 x float>* @x, align 32
store <4 x double> zeroinitializer, <4 x double>* @y, align 32 store <4 x double> zeroinitializer, <4 x double>* @y, align 32
ret void ret void
} }
define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind { define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind {
; CHECK-LABEL: ones: ; CHECK-LABEL: ones:
; CHECK: ## BB#0: ## %allocas ; CHECK: ## BB#0: ## %allocas
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rdi) ; CHECK-NEXT: vmovaps %ymm0, (%rdi)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
allocas: allocas:
%ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>* %ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>*
store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x
float>* %ptr2vec615, align 32 float>* %ptr2vec615, align 32
ret void ret void
} }
define void @ones2([0 x i32]* nocapture %RET, [0 x i32]* nocapture %aFOO) nounwind { define void @ones2([0 x i32]* nocapture %RET, [0 x i32]* nocapture %aFOO) nounwind {
; CHECK-LABEL: ones2: ; CHECK-LABEL: ones2:
; CHECK: ## BB#0: ## %allocas ; CHECK: ## BB#0: ## %allocas
; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 ; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rdi) ; CHECK-NEXT: vmovaps %ymm0, (%rdi)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
allocas: allocas:
%ptr2vec615 = bitcast [0 x i32]* %RET to <8 x i32>* %ptr2vec615 = bitcast [0 x i32]* %RET to <8 x i32>*
store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32>* %ptr2vec615, align 32 store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32>* %ptr2vec615, align 32
ret void ret void
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

test/CodeGen/X86/avx-cvt-3.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef, i32 0, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
%2 = sitofp <8 x i32> %1 to <8 x float> %2 = sitofp <8 x i32> %1 to <8 x float>
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @sitofp_insert_allbits_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_insert_allbits_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_allbits_v8i32: ; X86-LABEL: sitofp_insert_allbits_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_insert_allbits_v8i32: ; X64-LABEL: sitofp_insert_allbits_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = insertelement <8 x i32> %a0, i32 -1, i32 0 %1 = insertelement <8 x i32> %a0, i32 -1, i32 0
%2 = insertelement <8 x i32> %1, i32 -1, i32 2 %2 = insertelement <8 x i32> %1, i32 -1, i32 2
%3 = insertelement <8 x i32> %2, i32 -1, i32 4 %3 = insertelement <8 x i32> %2, i32 -1, i32 4
%4 = insertelement <8 x i32> %3, i32 -1, i32 5 %4 = insertelement <8 x i32> %3, i32 -1, i32 5
%5 = sitofp <8 x i32> %4 to <8 x float> %5 = sitofp <8 x i32> %4 to <8 x float>
ret <8 x float> %5 ret <8 x float> %5
} }
define <8 x float> @sitofp_shuffle_allbits_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_shuffle_allbits_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_shuffle_allbits_v8i32: ; X86-LABEL: sitofp_shuffle_allbits_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_shuffle_allbits_v8i32: ; X64-LABEL: sitofp_shuffle_allbits_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4],ymm0[5],ymm1[6],ymm0[7]
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> <i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef, i32 -1, i32 undef>, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
%2 = sitofp <8 x i32> %1 to <8 x float> %2 = sitofp <8 x i32> %1 to <8 x float>
ret <8 x float> %2 ret <8 x float> %2
} }
define <8 x float> @sitofp_insert_constants_v8i32(<8 x i32> %a0) { define <8 x float> @sitofp_insert_constants_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_constants_v8i32: ; X86-LABEL: sitofp_insert_constants_v8i32:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm2, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7] ; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7]
; X86-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-NEXT: movl $2, %eax ; X86-NEXT: movl $2, %eax
; X86-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 ; X86-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1
; X86-NEXT: movl $-3, %eax ; X86-NEXT: movl $-3, %eax
; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sitofp_insert_constants_v8i32: ; X64-LABEL: sitofp_insert_constants_v8i32:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7]
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm2, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7] ; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7]
; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-NEXT: movl $2, %eax ; X64-NEXT: movl $2, %eax
; X64-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1
; X64-NEXT: movl $-3, %eax ; X64-NEXT: movl $-3, %eax
; X64-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X64-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
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test/CodeGen/X86/avx-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%res = and <8 x i32> %1, %2 %res = and <8 x i32> %1, %2
%bc = bitcast <8 x i32> %res to <8 x float> %bc = bitcast <8 x i32> %res to <8 x float>
ret <8 x float> %bc ret <8 x float> %bc
} }
define <4 x double> @test_mm256_andnot_pd(<4 x double> %a0, <4 x double> %a1) nounwind { define <4 x double> @test_mm256_andnot_pd(<4 x double> %a0, <4 x double> %a1) nounwind {
; X32-LABEL: test_mm256_andnot_pd: ; X32-LABEL: test_mm256_andnot_pd:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm2, %ymm2, %ymm2
; X32-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 ; X32-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
; X32-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; X32-NEXT: vxorps %ymm2, %ymm0, %ymm0
; X32-NEXT: vandps %ymm1, %ymm0, %ymm0 ; X32-NEXT: vandps %ymm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_andnot_pd: ; X64-LABEL: test_mm256_andnot_pd:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm2, %ymm2, %ymm2
; X64-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 ; X64-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
; X64-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; X64-NEXT: vxorps %ymm2, %ymm0, %ymm0
; X64-NEXT: vandps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = bitcast <4 x double> %a0 to <4 x i64> %1 = bitcast <4 x double> %a0 to <4 x i64>
%2 = bitcast <4 x double> %a1 to <4 x i64> %2 = bitcast <4 x double> %a1 to <4 x i64>
%3 = xor <4 x i64> %1, <i64 -1, i64 -1, i64 -1, i64 -1> %3 = xor <4 x i64> %1, <i64 -1, i64 -1, i64 -1, i64 -1>
%res = and <4 x i64> %3, %2 %res = and <4 x i64> %3, %2
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test/CodeGen/X86/pr28129.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64
define <4 x double> @cmp4f64_domain(<4 x double> %a) { define <4 x double> @cmp4f64_domain(<4 x double> %a) {
; X86-LABEL: cmp4f64_domain: ; X86-LABEL: cmp4f64_domain:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp4f64_domain: ; X64-LABEL: cmp4f64_domain:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i64> %sext = sext <4 x i1> %cmp to <4 x i64>
%mask = bitcast <4 x i64> %sext to <4 x double> %mask = bitcast <4 x i64> %sext to <4 x double>
%add = fadd <4 x double> %a, %mask %add = fadd <4 x double> %a, %mask
ret <4 x double> %add ret <4 x double> %add
} }
define <4 x double> @cmp4f64_domain_optsize(<4 x double> %a) optsize { define <4 x double> @cmp4f64_domain_optsize(<4 x double> %a) optsize {
; X86-LABEL: cmp4f64_domain_optsize: ; X86-LABEL: cmp4f64_domain_optsize:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp4f64_domain_optsize: ; X64-LABEL: cmp4f64_domain_optsize:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i64> %sext = sext <4 x i1> %cmp to <4 x i64>
%mask = bitcast <4 x i64> %sext to <4 x double> %mask = bitcast <4 x i64> %sext to <4 x double>
%add = fadd <4 x double> %a, %mask %add = fadd <4 x double> %a, %mask
ret <4 x double> %add ret <4 x double> %add
} }
define <8 x float> @cmp8f32_domain(<8 x float> %a) { define <8 x float> @cmp8f32_domain(<8 x float> %a) {
; X86-LABEL: cmp8f32_domain: ; X86-LABEL: cmp8f32_domain:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp8f32_domain: ; X64-LABEL: cmp8f32_domain:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer
%sext = sext <8 x i1> %cmp to <8 x i32> %sext = sext <8 x i1> %cmp to <8 x i32>
%mask = bitcast <8 x i32> %sext to <8 x float> %mask = bitcast <8 x i32> %sext to <8 x float>
%add = fadd <8 x float> %a, %mask %add = fadd <8 x float> %a, %mask
ret <8 x float> %add ret <8 x float> %add
} }
define <8 x float> @cmp8f32_domain_optsize(<8 x float> %a) optsize { define <8 x float> @cmp8f32_domain_optsize(<8 x float> %a) optsize {
; X86-LABEL: cmp8f32_domain_optsize: ; X86-LABEL: cmp8f32_domain_optsize:
; X86: # BB#0: ; X86: # BB#0:
; X86-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cmp8f32_domain_optsize: ; X64-LABEL: cmp8f32_domain_optsize:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm1, %ymm1, %ymm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 ; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer
%sext = sext <8 x i1> %cmp to <8 x i32> %sext = sext <8 x i1> %cmp to <8 x i32>
%mask = bitcast <8 x i32> %sext to <8 x float> %mask = bitcast <8 x i32> %sext to <8 x float>
%add = fadd <8 x float> %a, %mask %add = fadd <8 x float> %a, %mask
ret <8 x float> %add ret <8 x float> %add
} }

test/CodeGen/X86/vector-pcmp.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: test_pcmpgtb_256: ; AVX1-LABEL: test_pcmpgtb_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtb_256: ; AVX2-LABEL: test_pcmpgtb_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
Show All 11 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test_pcmpgtw_256: ; AVX1-LABEL: test_pcmpgtw_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtw_256: ; AVX2-LABEL: test_pcmpgtw_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
Show All 11 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test_pcmpgtd_256: ; AVX1-LABEL: test_pcmpgtd_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtd_256: ; AVX2-LABEL: test_pcmpgtd_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
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; ;
; AVX1-LABEL: test_pcmpgtq_256: ; AVX1-LABEL: test_pcmpgtq_256:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_pcmpgtq_256: ; AVX2-LABEL: test_pcmpgtq_256:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
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test/CodeGen/X86/xop-intrinsics-fast-isel.ll

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%res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) %res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2)
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_cmov_si256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) { define <4 x i64> @test_mm256_cmov_si256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
; X32-LABEL: test_mm256_cmov_si256: ; X32-LABEL: test_mm256_cmov_si256:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vxorps %ymm3, %ymm3, %ymm3
; X32-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3 ; X32-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3
; X32-NEXT: vxorps %ymm3, %ymm2, %ymm3 ; X32-NEXT: vxorps %ymm3, %ymm2, %ymm3
; X32-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X32-NEXT: vandps %ymm2, %ymm0, %ymm0
; X32-NEXT: vandps %ymm3, %ymm1, %ymm1 ; X32-NEXT: vandps %ymm3, %ymm1, %ymm1
; X32-NEXT: vorps %ymm1, %ymm0, %ymm0 ; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_mm256_cmov_si256: ; X64-LABEL: test_mm256_cmov_si256:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vxorps %ymm3, %ymm3, %ymm3
; X64-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3 ; X64-NEXT: vcmptrueps %ymm3, %ymm3, %ymm3
; X64-NEXT: vxorps %ymm3, %ymm2, %ymm3 ; X64-NEXT: vxorps %ymm3, %ymm2, %ymm3
; X64-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64-NEXT: vandps %ymm2, %ymm0, %ymm0
; X64-NEXT: vandps %ymm3, %ymm1, %ymm1 ; X64-NEXT: vandps %ymm3, %ymm1, %ymm1
; X64-NEXT: vorps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2)
ret <4 x i64> %res ret <4 x i64> %res
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