[GlobalISel][X86] Prioritize Tablegen-erated instruction selection. NFC

[igorb]

Summary

Prioritizes Tablegen-erated instruction selection over C++ instruction selection.
Remove G_ADD/G_SUB C++ selection - implemented by Tablegen.

[guyblank]

LGTM

lib/Target/X86/X86InstructionSelector.cpp

58 ↗

(On Diff #97216)

does the comment need updating?

[igorb]

Thanks for the review!

lib/Target/X86/X86InstructionSelector.cpp

58 ↗

(On Diff #97216)

Thanks

[dsanders]

Thanks for doing this. It will allow me to add a test for the predicates related to the optsize attribute.

llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp

public:
 
   bool select(MachineInstr &I) const override;
 
 private:
   /// tblgen-erated 'select' implementation, used as the initial selector for
   /// the patterns that don't require complex C++.
   bool selectImpl(MachineInstr &I) const;
 
-  // TODO: remove after selectImpl support pattern with a predicate.
+  // TODO: remove after suported by Tablegen-erated instruction selection.
   unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
   unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
-  unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const;
-  unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const;
   unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
                           uint64_t Alignment) const;
 
   bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
                       MachineFunction &MF) const;
   bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
                          MachineFunction &MF) const;
   bool selectFrameIndex(MachineInstr &I, MachineRegisterInfo &MRI,
if (!isPreISelGenericOpcode(Opcode)) {
 
     // TODO: handle more cases - LOAD_STACK_GUARD, PHI
     return true;
   }
 
   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
          "Generic instruction has unexpected implicit operands\n");
 
-  // TODO: This should be implemented by tblgen, pattern with predicate not
-  // supported yet.
+  if (selectImpl(I))
+     return true;
+
+  DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
+
+  // TODO: This should be implemented by tblgen.
   if (selectBinaryOp(I, MRI, MF))
     return true;
   if (selectLoadStoreOp(I, MRI, MF))
     return true;
   if (selectFrameIndex(I, MRI, MF))
     return true;
   if (selectConstant(I, MRI, MF))
     return true;
   if (selectTrunc(I, MRI, MF))
     return true;
 
-  return selectImpl(I);
+  return false;
 }
 
 unsigned X86InstructionSelector::getFAddOp(LLT &Ty,
                                            const RegisterBank &RB) const {
 
   if (X86::VECRRegBankID != RB.getID())
     return TargetOpcode::G_FADD;
 
if (Ty == LLT::scalar(32)) {
     } else if (STI.hasSSE1()) {
       return X86::SUBPSrr;
     }
   }
 
   return TargetOpcode::G_FSUB;
 }
 
-unsigned X86InstructionSelector::getAddOp(LLT &Ty,
-                                          const RegisterBank &RB) const {
-
-  if (X86::VECRRegBankID != RB.getID())
-    return TargetOpcode::G_ADD;
-
-  if (Ty == LLT::vector(4, 32)) {
-    if (STI.hasAVX512() && STI.hasVLX()) {
-      return X86::VPADDDZ128rr;
-    } else if (STI.hasAVX()) {
-      return X86::VPADDDrr;
-    } else if (STI.hasSSE2()) {
-      return X86::PADDDrr;
-    }
-  }
-
-  return TargetOpcode::G_ADD;
-}
-
-unsigned X86InstructionSelector::getSubOp(LLT &Ty,
-                                          const RegisterBank &RB) const {
-
-  if (X86::VECRRegBankID != RB.getID())
-    return TargetOpcode::G_SUB;
-
-  if (Ty == LLT::vector(4, 32)) {
-    if (STI.hasAVX512() && STI.hasVLX()) {
-      return X86::VPSUBDZ128rr;
-    } else if (STI.hasAVX()) {
-      return X86::VPSUBDrr;
-    } else if (STI.hasSSE2()) {
-      return X86::PSUBDrr;
-    }
-  }
-
-  return TargetOpcode::G_SUB;
-}
-
 bool X86InstructionSelector::selectBinaryOp(MachineInstr &I,
                                             MachineRegisterInfo &MRI,
                                             MachineFunction &MF) const {
 
   const unsigned DefReg = I.getOperand(0).getReg();
   LLT Ty = MRI.getType(DefReg);
   const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
 
   unsigned NewOpc = I.getOpcode();
 
   switch (NewOpc) {
   case TargetOpcode::G_FADD:
     NewOpc = getFAddOp(Ty, RB);
     break;
   case TargetOpcode::G_FSUB:
     NewOpc = getFSubOp(Ty, RB);
     break;
-  case TargetOpcode::G_ADD:
-    NewOpc = getAddOp(Ty, RB);
-    break;
-  case TargetOpcode::G_SUB:
-    NewOpc = getSubOp(Ty, RB);
-    break;
   default:
     break;
   }
 
   if (NewOpc == I.getOpcode())
     return false;
 
   I.setDesc(TII.get(NewOpc));