ARM: support stack probe emission for Windows on ARM

[abdulras]

Summary

This introduces the stack lowering emission of the stack probe function for
Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where
any page allocation which crosses a page boundary of the following guard page
will cause a page fault. This page fault must be handled by the kernel to
ensure that the page is faulted in. If this does not occur and a write access
any memory beyond that, the page fault will go unserviced, resulting in an
abnormal program termination.

The watermark for the stack probe appears to be at 4080 bytes (for accommodating
the stack guard canaries and stack alignment). Follow suit and emit it at that
water mark (this would ideally be done similarly where if SSP is disabled, we
would use the 4096 value).

[rengolin]

Hi Saleem,

The code seems a bit too specific (ie. Function symbols and registers) but I can't see a better way of doing this in a generic way. If no one has a better idea, apart from my other comments, looks good to me.

thanks,
--renato

lib/Target/ARM/ARMFrameLowering.cpp

192

A better comment here would be good

290

Maybe make it a constant, name it appropriately and comment on the constant?

321

I don't know much about the Windows ABI, but are those registers fixed by it? Or are them just the "next available GPRs on either side"?

[abdulras]

lib/Target/ARM/ARMFrameLowering.cpp

192

Fair enough.

290

I think I want to split it out into a function and base it on whether SSP is enabled or not. But, we can extract it now rather than later.

321

The R4 is definitely fixed. I use R12 as it is intra-procedural scratch, and this usage is in the stack setup.

The interface for __chkstk on WoA is as follows:

R4 = 32-bit *words* to be allocated
call __chkstk
Adjust SP by value in R4 (now containing bytes)

This is what the ABI/API is and we have no choice in the matter unfortunately.

[rengolin]

lib/Target/ARM/ARMFrameLowering.cpp

321

Ok, I'm happy with this.

[abdulras]

This has been committed already, just closing off the revision.

docs/Extensions.rst

.. code-block:: gas
   .globl Symbol1
   Symbol1:
   .long 1
 
   .section secName, "dr", discard, "Symbol2"
   .globl Symbol2
   Symbol2:
   .long 1
+
+Target Specific Behaviour
+=========================
+
+Windows on ARM
+--------------
+
+Stack Probe Emission
+^^^^^^^^^^^^^^^^^^^^
+
+The reference implementation (Microsoft Visual Studio 2012) emits stack probes
+in the following fashion:
+
+.. code-block:: gas
+
+  movw r4, #constant
+  bl __chkstk
+  sub.w sp, sp, r4
+
+However, this has the limitation of 32 MiB (±16MiB).  In order to accomodate
+larger binaries, LLVM supports the use of ``-mcode-model=large`` to allow a 4GiB
+range via a slight deviation.  It will generate an indirect jump as follows:
+
+.. code-block:: gas
+
+  movw r4, #constant
+  movw r12, :lower16:__chkstk
+  movt r12, :upper16:__chkstk
+  blx r12
+  sub.w sp, sp, r4
+

lib/Target/ARM/ARMFrameLowering.cpp

 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/Function.h"
+#include "llvm/IR/Module.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 static cl::opt<bool>
 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),

 
 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock &MBB = MF.front();
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo  *MFI = MF.getFrameInfo();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   MachineModuleInfo &MMI = MF.getMMI();
   MCContext &Context = MMI.getContext();
+  const TargetMachine &TM = MF.getTarget();
   const MCRegisterInfo *MRI = Context.getRegisterInfo();
   const ARMBaseRegisterInfo *RegInfo =
-    static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
+    static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
   const ARMBaseInstrInfo &TII =
-    *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
+    *static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
   assert(!AFI->isThumb1OnlyFunction() &&
          "This emitPrologue does not support Thumb1!");
   bool isARM = !AFI->isThumbFunction();
-  unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
+  unsigned Align = TM.getFrameLowering()->getStackAlignment();
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
   unsigned NumBytes = MFI->getStackSize();
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
   unsigned FramePtr = RegInfo->getFrameRegister(MF);
   int CFAOffset = 0;
 
   // Determine the sizes of each callee-save spill areas and record which frame
emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
                  MachineInstr::FrameSetup);
     CFAOffset -= ArgRegsSaveSize;
     unsigned CFIIndex = MMI.addFrameInst(
         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
   }
 
-  if (!AFI->hasStackFrame()) {
+  if (!AFI->hasStackFrame() &&
+      !(NumBytes >= 4080 /* 4096 */ && STI.isTargetWindows())) {
     if (NumBytes - ArgRegsSaveSize != 0) {
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
                    MachineInstr::FrameSetup);
       CFAOffset -= NumBytes - ArgRegsSaveSize;
       unsigned CFIIndex = MMI.addFrameInst(
           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex);
if (AFI->getNumAlignedDPRCS2Regs() > 0) {
     // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
     // leaves the stack pointer pointing to the DPRCS2 area.
     //
     // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
     NumBytes += MFI->getObjectOffset(D8SpillFI);
   } else
     NumBytes = DPRCSOffset;
 
+  if (STI.isTargetWindows()) {
+    if (NumBytes >= 4080 /* 4096 */) {
+      uint32_t NumWords = NumBytes >> 2;
+
+      if (NumWords < 65536)
+        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
+                       .addImm(NumWords));
+      else
+        BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
+          .addImm(NumWords);
+
+      switch (TM.getCodeModel()) {
+      case CodeModel::Small:
+      case CodeModel::Medium:
+      case CodeModel::Default:
+      case CodeModel::Kernel:
+        BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
+          .addImm((unsigned)ARMCC::AL).addReg(0)
+          .addExternalSymbol("__chkstk")
+          .addReg(ARM::R4, RegState::Implicit);
+        break;
+      case CodeModel::Large:
+      case CodeModel::JITDefault: {
+        LLVMContext &Ctx = MF.getMMI().getModule()->getContext();
+        const GlobalValue *F =
+          Function::Create(FunctionType::get(Type::getVoidTy(Ctx), false),
+                           GlobalValue::AvailableExternallyLinkage, "__chkstk");
+
+        BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
+          .addGlobalAddress(F);
+        BuildMI(MBB, MBBI, dl, TII.get(ARM::BLX))
+          .addReg(ARM::R12, RegState::Kill)
+          .addReg(ARM::R4, RegState::Implicit);
+        break;
+      }
+      }
+
+      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
+                                          ARM::SP)
+                                  .addReg(ARM::SP, RegState::Define)
+                                  .addReg(ARM::R4, RegState::Kill)
+                                  .setMIFlags(MachineInstr::FrameSetup)));
+      NumBytes = 0;
+    }
+  }
+
   unsigned adjustedGPRCS1Size = GPRCS1Size;
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
     if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes)) {
       if (LastPush == GPRCS1Push) {
         FramePtrOffsetInPush += NumBytes;
         adjustedGPRCS1Size += NumBytes;
         NumBytes = 0;

test/CodeGen/ARM/Windows/chkstk.ll

+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 %s -o - \
+; RUN:  | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
+
+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -code-model=large %s -o - \
+; RUN:  | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
+
+define arm_aapcs_vfpcc void @check_watermark() #0 {
+entry:
+  %buffer = alloca [4080 x i8], align 1
+  ret void
+}
+
+; CHECK-DEFAULT-CODE-MODEL: check_watermark:
+; CHECK-DEFAULT-CODE-MODEL:   movw r4, #1020
+; CHECK-DEFAULT-CODE-MODEL:   bl __chkstk
+; CHECK-DEFAULT-CODE-MODEL:   sub.w sp, sp, r4
+
+; CHECK-LARGE-CODE-MODEL: check_watermark:
+; CHECK-LARGE-CODE-MODEL:   movw r12, :lower16:__chkstk
+; CHECK-LARGE-CODE-MODEL:   movt r12, :upper16:__chkstk
+; CHECK-LARGE-CODE-MODEL:   movw r4, #1020
+; CHECK-LARGE-CODE-MODEL:   blx r12
+; CHECK-LARGE-CODE-MODEL:   sub.w sp, sp, r4
+
+attributes #0 = { nounwind }
+